Instrumentation
Figure 1 . Typical microprocessor c a r d set
Microprocessors Part I: Bridging the Gap Raymond E. Dessy, Peter Janse-Van Vuuren, and Jonathan A. Titus Virginia Polytechnic Institute and State University Biacksburg, Va. 24061
During the last year a new word has appeared in the ever-changing vocabulary of news and business magazines— microprocessors.These are the large-scale integrated (LSI) circuits that are at the heart of a revolution in the entertainment industry (PONG!), the large retail stores (pointof-sale or POS equipment), and more recently in automated analytical instrumentation (the digital self-computing gas chromatograph). The significance and importance of this new technological development to the analytical chemist is that a microprocessor in conjunction with memory, control circuitry, and data input and output lines (the I/O bus) constitutes a microcomputer. The function of the LSI microprocessor chip(s) in this configuration is the same as that of the central processing unit (CPU) in larger computers. In other words, the complex circuitry necessary for the decoding of instructions and control of the resultant logical operations of the computer (the function of a CPU) has been micronized into a single (!) integrated circuit chip, hence, a microprocessor. The extent to which LSI chips are currently incorporated into computers and in future designs makes microcomputers rather ill-defined devices since no criterion exists, or is likely to exist, which delineates the area where microcomputers leave off and minicomputers begin. Indeed, as many manufacturers begin to emulate their existing minicomputers, previously assembled from medium-scale integrated circuit components, with LSI chips the grey area will become even broader. What is the significance of the microcomputer from the viewpoint of the analytical chemist? Most minicomputer manufacturers are committed to the philosophy of developing machines with increasingly powerful computational capabilities, often to the exclusion of
their less powerful and less expensive progenitors. In a decentralized configuration, minicomputers with up to 64,000 words of memory and 5 million words of disk storage and high-speed peripherals, such as line printers and CRT terminals, often provide an attractive logistical and economical alternative to a single massive data processing installation such as the proverbial IBM 360 or 370 systems. Fully equipped minicomputers offer all the advantages of higherlevel languages such as BASIC or FORTRAN which are human oriented and which ease the cost of program generation. Manufacturers provide programs called EXECUTIVES to supervise these high-level languages as well as data acquisition programs which are usually written in a language more closely related to the machine operations called ASSEMBLY or MACHINE Language. However, as the executive programs become more sophisticated, the vendor and the end user begin to spend more for the programs (software) to run the equipment than the equipment (hardware) itself, especially when a single large computer is to service the needs of a large number of instruments attached to it. At this point, the system becomes so complicated, interactive, and interlocked that the average chemist is more than happy to let the computing center personnel assume responsibility. But with this responsibility goes control of the design or modification of the system—often resulting in dissatisfaction at the bench level in system function, flexibility, and expandability. A solution to this problem would be to devote a single minicomputer (with a minimum of memory and peripheral devices such as 2K of memory and a single teletype) to the control and data acquisition of a single instrument (a dedicated system) or a cluster of these dedicated systems as satellites to a larger CPU that is responsible for data ma-
ANALYTICAL CHEMISTRY, VOL. 46, NO. 11, SEPTEMBER 1974 • 917 A
nipulation and storage (a hierarchical system). However, current costs may preclude this approach. Alternatively, each instrument could have a hard-wired front-end or data reduction unit associated with it, similar to the peak detectors often found on gas chromatography equipment. For the average chemist this represents a formidable electronics design problem, and the end product is inflexible. Changing it to meet future needs is very difficult. Microcomputers offer an interesting opportunity to implement such dedicated and hierarchical applications at relatively modest cost, but with complete flexibility. In the case of dedicated systems, microcomputers are installed in lieu of the more powerful but more expensive minicomputer systems where a careful analysis of needs indicates that the latter are an overkill to the specific problem. They will increasingly replace hard-wired front-ends to provide for low initial cost and future flexibility and expandability. It is now possible to conceive of all moderately sophisticated analytical equipment being delivered with an inboard microcomputer for closed-loop control and optimization of the instrument conditions, as well as data collection and reduction. Completely operational microcomputers that are entirely adequate to service single instruments at data acquisition speeds of up to 1000-3000 digital data words/sec are available for about $1000. Multi-instrument installations in which relatively slow data rates place not too stringent speed requirements on control and data acquisition are also accommodated. Microcomputers thus bridge the gap that has existed between hardware implementation of automation and the use of minicomputers. It is the purpose of this article to provide some perspectives and an overview of this exciting new development in analytical instrumentation. In Part I we will focus on: • the most attractive feature of a microcomputer, i.e., the modular nature of the hardware components required to configure microcomputers with variable operational capabilities • an outline of the basic principles of interfacing external devices, such as analytical instruments, to the input/ output (I/O) bus of the microcomputer • the powerful software instruction set utilized by the microprocessor and which is principally responsible for its operation as a full-fledged CPU. In Part II we will: • describe in detail a potential application in which the flexibility of the microcomputer as a control and data acquisition device will be illustrated • spotlight some of the advantages and disadvantages of microcomputers • summarize the application of microcomputers as relatively inexpensive instructional equipment for providing "hands-on" and "hands-in" experience in the teaching of digital techniques and applications in the analytical laboratory. For those unfamiliar with digital electronics or interfacing principles in general, background material may be found in two review articles that have appeared in ANALYTICAL C H E M I S T R Y : "Computer Interfacing" (7) and "Instant Interfacing" (2). Hardware The description of hardware which follows is based on what is necessary to configure the Intel 8008 microprocessor into a microcomputer. This LSI chip is second-sourced, and four vendors can provide total systems for the end user. A typical system is shown in Figure 1. The different types of microprocessors are operationally very similar, and it is relatively easy to extrapolate the basic principles outlined below to other microcomputers and microprocessors. Many other manufacturers provide, or are claiming to provide, microprocessors. The key components typically required to configure a
microcomputer involve: • the microprocessor or micro CPU—the "head-quarters" of all computer operations and the following external components: • memory—read/write and read-only for program and data storage • external control circuitry—for synchronization and generation of control signals • device decoder—for generation of special control signals for external devices • interrupt input port—to force external control of the microprocessor. These are illustrated in Figure 2a. To complete the basic components required by the microcomputer to communicate with external devices, it is also necessary to include the following which will be added to our circuitry later in the article: • output latches • input ports—both to control and synchronize data transfer to and from the microprocessor. The elements incorporated into the Intel 8008 microprocessor are: • an instruction register associated with powerful and sophisticated internal decoding and control logic • an accumulator and seven 8-bit general-purpose registers used in conjunction with flags, i.e., CARRY, SIGN, and ZERO • a 14-bit program counter associated with a 14-bit, seven-register stack. All these elements are present on the single microprocessor chip. Figure 2b represents a simplified diagram of these components. CPU/Memory. The Central Processing Unit (CPU) is an arithmetic and logic unit that is associated with a memory. The memory consists of solid-state devices in which each "word" is made up of 8 binary digits (bits) of information. Part of the memory is random access memory (RAM) that the CPU can write data into, or read data from. Another portion of the memory is preprogrammed and can be read from only (read only memory or ROM). A series of commands (really binary numbers that are decoded by the CPU and cause certain operations to take place) is stored in memory and then executed one-at-a-time, usually sequentially. This is a program or software. The program may be stored in RAM or ROM; it is common to store the operating program in ROM and use RAM for data manipulation and storage. Program Counter. When a program is to be executed, a 14-bit register in the CPU is loaded with the address of the first instruction to be executed, and it is "fetched" by the CPU from memory, decoded, and the CPU sets itself up to perform the desired operation. The program counter is automatically incremented at this point so that it is set to indicate the location of the next instruction to be executed. General Registers. Typically, the initial instructions in a program would involve loading one of the seven generalpurpose registers within the CPU (A, B, C, D, E, H, and L). The first of these registers is called the A register or accumulator. It is in this register that we perform the arithmetic (add, substract) and Boolean functions (and, or, compare). Carry, Sign, and Zero CPU Flags. The A register has associated with it an extension bit, called the carry. Upon addition with carry, or subtraction with underflo, this bit gets set to a 1. The A register and its carry extension are really a circular register, and rotation of the contents is possible under software command. Such operations will be discussed in a later section. There are two other "flag" bits associated with the CPU. These are the sign and zero flag bits. Their contents will reveal information concerning the contents of the A register, or the results of Boolean operations. For example:
9 1 8 A • ANALYTICAL CHEMSTRY, VOL. 46, NO. 1 1 , SEPTEMBER 1974
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Figure 2 b . Internal architecture of microprocessor ANALYTICAL CHEMISTRY, VOL. 46, NO. 1 1 , SEPTEMBER 1974 • 919 A
8 Interrupt Request Lines
8 Interrupt Acknowledge Lines
MICROCOMPUTER 8 Select Device for Input Lines
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ORIGINAL
CONDITIONS
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200 8 + 200 8 = 400 8 . The largest 8-bit number is 377; thus, the result of the addition is zero, with a carry; just like 9 + 1 = 10, where the result is a zero with a carry. The appro priate flags are set as indicated. The other six registers allow storage of constants and counters. These registers may be incremented or decre mented by software commands. Data can be transferred from one register to another by software also. High and Low Memory Address Registers. An opera tion that is important early in most programs is the ability to read data from memory or store data in memory. When this is desired, the location of that memory cell is loaded into the two registers called Η and L. Two 8-bit registers have been used for this task; using one register would per mit addressing of only 256 memory cells—(2 8 ), too small a memory for most applications. Only 14 bits of these regis ters are used, thus allowing direct addressing of 16K words of memory! The Stack. Another common function in programming is a jump to a subroutine, implying that we want to branch
off to perform a commonly used operation and return to the main program where we left it. In order to accomplish this, the contents of the program counter at the time of the jump-to-subroutine request is "pushed-down" into the stack, a 7-word X 14-bit set of registers associated with the CPU. The program counter itself now contains the address information pointing to the subroutine instructions. When we wish to return from the subroutine, the old address in formation is "popped-up" in the stack and back into the program counter by a software command called a RE TURN. The microprocessor has computational capabilities, and these will be discussed in subsequent paragraphs; however, it is the function of this article to emphasize the hardware necessary to input and output data into and out from the CPU (Figure 3). Select Device/In and Out Pulses. The pathway in and out of the CPU is a set of bidirectional data lines, eight in number. The operational circuitry in the CPU accepts or places information on these lines only at certain times. (The complex multiplexing accomplishing this is not shown in the drawings for clarity; from this point on, the drawings will show separated INPUT and OUTPUT BUSSES). Be cause of this criticality in timing, and the fact that we usu ally want many input and output devices to be attached to the microcomputer, but only have a single input or output device activated at a time, the CPU has I/O control circuit ry associated with it. When data are to be input to the CPU, a software command causes the external control cir cuitry to issue a pulse called IN, and the device decoder to issue a pulse unique to each device called SELECT DE VICE. These activate or enable a a device called a GATE which momentarily places the desired information from the input device onto the bidirectional I/O lines. The micro computer accomplishes this by means of tri-state logic. It is configured as shown in Figure 4. Tri-State Gate (Input Port). Tri-state logic is con structed so that output is enabled only when the CON-
922 A • ANALYTICAL CHEMISTRY, VOL. 46, NO. 11, SEPTEMBER
1974
I O Bus
Data Bit Select Dev In
In Control Line
Out
J Data Bit ] to CPU
(8 Gates Per Input Port) Select Device Pulse — In Pulse —
Figure 4. Tri-state logic configuration
Data Bit
TROL LINE is held at a logic 0. In this condition the DATA BIT at the input is "gated" to the output. When the control line is a logic 1, the output looks like a high impedence or open circuit.
)ata bit 1 0 1 or 0
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Output 1 0 Hi Ζ
A set of 8 bits is called an INPUT PORT, and we can "strobe" data onto the Data Bus from them by momentari ly grounding the CONTROL line associated with the PORT. This is done by ORing (OR gates and other inte grated circuit components are discussed in ref. 1 and 2) the SELECT DEVICE and IN signals together and connecting them to the CONTROL input of that port. Many devices may be attached to the CPU by using a unique SELECT DEVICE pulse for each port (Figure 5). Commonly, device decoders provide eight such pulses for input. Data Latch (Output Port). When data are to be output (Figure 6), a software command causes the control logic to issue two signals, called SELECT DEVICE and OUT, which activate or enable a device called a LATCH, which accepts the data on the bidirectional I/O lines at that in stant and holds them (examine Figure 6 for latch opera tion) for use by the output device. Since we wish to latch, or hold, data available on the Data Bus only during the pe riod that OUT is 0, and since many different devices are connected to the Data Bus in parallel, logical NORing of a SELECT DEVICE pulse and OUT is used to cause the clock input on a DATA LATCH to go to a logic 1 momen tarily, when and only when, the desired data are made available by the software and CPU action. Each device in the external world that requires latched data must have a data latch associated with it. Eight SELECT DEVICE pulses are available for output control in the configuration shown. External Flags. It is necessary for the CPU to know when external devices require service, either for input or output. Depending on the timing criteria, one of two meth ods is ordinarily used to synchronize the operation of the CPU and external devices. The first of these involves the external device creating a signal called FLAG which can be sensed by the CPU. This is done by having the CPU query a SENSE REGISTER (an input port to which the flags are attached) periodically, to ascertain whether any device requires service. If it senses such a condition, appropriate software will cause the is suance of the SELECT DEVICE and FUNCTION (IN or
Input
Output
Figure 5. Connection of input ports to I/O bus
OUT) pulses appropriate to that device. Eight separate de vices can be sensed using one gate input. Flags are usually built from flip-flops (Figure 7). This method involves sufficient software to properly identify the device and direct the program to the service routine for that device. Under certain conditions, usually involving very rapid input or output, or long periods be tween I/O, such a method is inadequate or inefficient. Interrupt Request and Acknowledge. To meet such needs, external devices can generate another signal called I N T E R R U P T REQUEST when I/O is needed (Figure 7). This interrupts the existing program, and automatically causes the following operations: • stores the program counter in the stack (just like a call to subroutine) • generates an I N T E R R U P T ACKNOWLEDGE signal that clears the flag, letting the device know its interrupt re quest has been accepted • vectors (jumps) to the service routine for the device by "jamming" a jump command called a VECTOR instruction (created by external hardware) into the CPU for execution. These will be discussed in the Software section. The microcomputer has the hardware to control eight devices in this manner. Those familiar with PDP-11 archi tecture will recognize that the microprocessor architecture is rather sophisticated. The emphasis up to now has been on hardware. But the flexibility of the microcomputer lies in its ability to be pro grammed for a given task by software. Software
A set of instructions called a program (software) is neces sary to allow the microcomputer to accomplish anything. Programming for analytical instruments will be discussed in Part II of this paper. For the moment, we need to focus on the topic of input/output commands and the basic in struction set.
924A • ANALYTICAL CHEMISTRY, VOL. 46, NO. 11, SEPTEMBER 1974
I/O Bus
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Figure 6. Connection of output ports to I/O bus
Input/Output Programming. All data flow to and from the microcomputer with respect to the outside world takes place via the A register. All data inputs must be activated during and only during the duration of a CPU generated pulse called IN. To distinguish between external devices, the CPU simultaneously produces a unique SELECT DEVICE pulse in response to the specific software command initiating data transfer; e.g., Octal code 111 113
The SELECT DEVICE and FUNCTION pulse (IN or OUT) are, as shown previously, gated together to form a single pulse that activates the device, and causes data transfer. Vector Instructions. Memory in a microcomputer might be configured as follows: MEMORY
ADDRESS
-1777 8
Mnemonic equivalent I N P 4 generates S E L E C T D E V I C E I N P 4 and I N I N P 5 generates S E L E C T D E V I C E I N P 5 and I N
RAM 14008 -1377 8 ROM
Similarly, data can be output from A during and only during the duration of a pulse called OUT. This and unique SELECT DEVICE pulses are generated by specific software commands: e.g., Octal code 125 131 133
Mnemonic equivalent OUT2 generates S E L E C T D E V I C E OUT2 and O U T OUT4 generates SELECT D E V I C E OUT4 and O U T OUT5 generates S E L E C T D E V I C E O U T 5 and OUT
0077 8
(vector space) -0000s a total of 102410 (IK) words of memory. The microcomputer is configured to have available a number of instructions which will effectively cause a jump to certain specified ROM locations called VECTOR SPACE. These are the VECTOR INSTRUCTIONS:
926 A ' · ANALYTICAL CHEMISTRY, VOL. 46, NO. 11, SEPTEMBER 1974
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Goes to Logic 1 Flarj Signât (hi CPU)
Unes to Loan 0 Interrupt Request f to CPU) Interrupt Acknowledge (from CPU I ι clears, flag) Figure 7. Flip-flop used as flag
Octal code 075 065 055 045 035 025 015 005
Operation H a r d w a r e equivalent performed ( I n t e r r u p t request) Vectors t o 0070 IR7 Vectors to 0060 IR6 Vectors t o 0050 IR5 Vectors t o 0040 IR4 Vectors t o 0030 IR3 Vectors t o 0020 IR2 Vectors t o 0010 IR1 Vectors t o 0000 IRQ V E C T O R = J u m p automatically
These actions may also be initiated by hardware action. As mentioned, available to the microcomputer user is a se ries of bus connections labeled I N T E R R U P T REQUEST. When momentarily grounded they effectively cause execu tion of the indicated vector command, as well as saving the current program counter in the stack and generating an ac knowledge signal. This allows one to write programs beginning in 00X0 and continuing through 00X7, which can initiate access to more lengthy service routines in ROM or RAM memory, wherev er a device needs service. These would normally contain an appropriate input or output software command. A software RETURN command permits the CPU to return to the point in the main program where it was interrupted, after service is accomplished, by "popping" the stack. In our microcomputer these interrupt requests can be di vided into two classes determined by when they are recog nized by the processor: • IMMEDIATE requests: recognized at the end of exe cution of the instruction during which the request was made • DEFERRED requests: these are recognized only at the time the software instruction OUT2 is executed. This allows the user to divide his external devices into two groups: those that require almost immediate attention and those that may be checked periodically to see if action is necessary. At each interrupt the register contents (A, B, C, D, Ε, Η, and L) and the flag status bits must usually be saved. This permits the machine to be returned to the condition it was in at the time of the interrupt after exit from the service routine for the device requesting service. Since this is a te dious memory-consuming process, it is usually desirable to arrange for IMMEDIATE interrupts to be as uncomplicat ed as possible (in terms of register and flag alterations) and to use DEFERRED interrupt operation at times in the pro gram when complex SAVE routines are not needed. This
can be at the end of repetitively called subroutines when no meaningful data are in registers or the flag bits. Complex interrupt service should be avoided. It is time consuming in both execution and in program preparation for it. Instruction Set. Once the data from an analytical in strument are read into the A register, it must be operated upon in some way. The instruction set in the 8008 micro processor involves over 150 commands. Each of these com mands is a number which can be decoded by the CPU and the appropriate operation performed. For human utiliza tion each number has a short mnemonic equivalent associ ated with it. A few examples are given below using the mnemonic equivalents utilized in our laboratories. Octal code Mnemonic LOAD INSTRUCTIONS 301 LDAB Load 307 LDAM Load 310 LDBA Load 370 LDMA Load MATH 201 221 010 011
OPERATIONS ADDB SUBB INCB DECB
Instruction performed A from Β * A from M e m o r y Β from A M e m o r y from A
A d d Β to A S u b t r a c t Β from A Increment Β Decrement Β
BOOLEAN OPERATIONS 241 ANDB Logical A N D Β w i t h A 271 COMB Compare Β with A 251 XORB Logical Exclusive OR Β with A 261 IORB Inclusive OR Β w i t h A ROTATE A REGISTER R o t a t e A Left 002 RALT Rotate A Right 012 RART R o t a t e A Left T h r u C a r r y 022 RALC Rotate A Right Thru Carry 032 RARC * Refer to registers. A = accumulator; B , C, D , E , H , a n d L = general-purpose registers. T h e above commands do not affect the program counter. For branching two types of jump commands are available. Normal J U M P instructions JPxx) examine the flags, and if the condition specified in the command is met, alters the program counter to the desired address, BUT does not cause the old program counter to be stored in the stack. J U M P TO SUBROUTINE (JSxx) instructions DO store the old program counter in the stack. For this reason, they are associated with RETURN commands that "pop" the stack at the end of the subroutine. Let's examine jumps re quiring a True Carry (=1): these are J P T C (jump on a true carry) and JSTC (jump to subroutine on true carry).
9 2 8 A • A N A L Y T I C A L CHEMISTRY, VOL. 46, NO. 1 1 , SEPTEMBER
JUMPS
jump IF carry flag = 1 T ^ I , continue
JPTC fix
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j u m p t o subroutine I F carry flag = 1 =^1, continue
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LWCONDITIONAL False Carry ( = 0) .False Zero (reg ^ 0) False Sign (reg is + ) T r u e Carry ( = 1 ) True Zero (reg = 0 ) T r u e Sign (reg is — )
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FLAG C O N D I T I O N NEEDED
JUMP COMMANDS 104 JPUN 100 JPFC 110 JPFZ 120 JPFS 140 JPTC 150 JPTZ 160 JPTS
CLRA NOOP HALT
COMMANDS RTUN RTFC RTFZ RTFS RTTC RTTZ RTTS
COMMANDS Clear A N o Operation Stop C P U
It is obvious with these commands that rather sophisti cated data manipulation is possible. A number can be input, then examined to see if it falls between certain limits by COMpare commands, and then appropriate action taken by J u m P commands depending upon the status of the flags called CARRY, ZERO, and SIGN. In fact, the in struction set is more powerful than that of the ubiquitous PDP-8 which has played such an important role in labora tory automation. With this background, Part II of this article in next month's INSTRUMENTATION will present a typical applica tion of microprocessors—the construction of a differential stripping electrochemical apparatus. The strong points and shortcomings of microprocessors will be examined, and some suggestions made on how to get started. References (1) (2)
CIRCLE 2 ON READER SERVICE CARD 930 A • ANALYTICAL CHEMISTRY, VOL. 46, NO. 1 1 , SEPTEMBER
E. Dessy and J. A. Titus, Anal. Chem., 45 (2), 124A (1973). E. Dessy and J. A. Titus, ibid., 46 (3), 294A (1974).
1974
