Letter Cite This: Nano Lett. XXXX, XXX, XXX−XXX
pubs.acs.org/NanoLett
Monolayer Molybdenum Disulfide Transistors with Single-AtomThick Gates Yibo Zhu,† Yijun Li,† Ghidewon Arefe,† Robert A. Burke,‡,§ Cheng Tan,† Yufeng Hao,∥ Xiaochi Liu,†,⊥ Xue Liu,# Won Jong Yoo,⊥ Madan Dubey,‡ Qiao Lin,† and James C. Hone*,† †
Department of Mechanical Engineering, Columbia University, New York, New York 10027, United States Sensors and Electron Devices Directorate, U.S. Army Research Laboratory, Adelphi, Maryland 20783, United States § General Technical Services LLC, Wall Township, New Jersey 07727, United States ∥ National Laboratory of Solid State Microstructures, College of Engineering and Applied Sciences, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China ⊥ Samsung-SKKU Graphene/2D Center (SSGC), Department of Nano Science and Technology, SKKU Advanced Institute of Nano-Technology (SAINT), Sungkyunkwan University, Suwon 16419, Korea # Division of Physics and Applied Physics, School of Physical and Mathematical Sciences, Nanyang Technological University 637371, Singapore ‡
S Supporting Information *
ABSTRACT: Two-dimensional transition-metal dichalcogenides (TMDs) are unique candidates for the development of next-generation electronic devices. However, the large contact resistance between metal and the monolayer TMDs have significantly limited the devices’ performance. Also, the integration of ultrathin high-k dielectric layers with TMDs remains difficult due to the lack of dangling bonds on the surface of TMDs. We present monolayer molybdenum disulfide field-effect transistors with bottom local gates consisting of monolayer graphene. The atomic-level thickness and surface roughness of graphene facilitate the growth of high-quality ultrathin HfO2 and suppress gate leakage. Strong displacement fields above 8 V/nm can be applied using a single graphene gate to electrostatically dope the MoS2, which reduces the contact resistances between Ni and monolayer MoS2 to 2.3 kΩ·μm at low gate voltages. The devices exhibit excellent switching characteristics including a near-ideal subthreshold slope of 64 millivolts per decade, low threshold voltage (∼0.5 V), high channel conductance (>100 μS/μm), and low hysteresis. Scaled devices with 50 and 14 nm channels as well as ultrathin (5 nm) gate dielectrics show effective immunity to short-channel effects. The device fabricated on flexible polymeric substrate also exhibits high performance and has a fully transparent channel region that is desirable in opticalrelated studies and practical applications. KEYWORDS: Molybdenum disulfide, graphene gate, high-k dielectric, short channel, field-effect transistor
T
chemical vapor deposition (CVD)-derived 2D materials introduces impurities trapped at the interface of materials and substrates. Direct metal deposition typically results in large contact resistance between metal and monolayer TMDs.20,21 The use of unconventional contact materials such as graphene,8 doped TMDs,22 or Co/hBN23 structures can reduce the contact resistance but complicates device fabrication. Likewise, the integration of reliable, uniform, and ultrathin dielectric layers with TMDs remains difficult because of the lack of dangling bonds on the TMDs surfaces.24,25 Despite significant progress toward each of these challenges,26−29 integrated
wo-dimensional (2D) materials with intrinsic atomic-level thicknesses have become strong candidates for the development of deeply scaled field-effect transistors and novel device architectures.1−9 Transition-metal dichalcogenides (TMDs), of which molybdenum disulfide (MoS2) is the most widely studied, are especially attractive because of their nonzero bandgap, mechanical flexibility, and optical transparency.10−14 Scalable device fabrication is made possible by the recently reported wafer-scale growth of monolayer TMDs,6,15−18 which are more suitable for fabrication of short-channel devices than their multilayer counterparts.7,19 However, realizing the potential of these materials in practical devices requires addressing critical device fabrication and materials issues, particularly: (1) utilizing TMD films with high quality and minimal contamination during transfer and processing, (2) achieving low-resistance contacts, and (3) integration with high-quality ultrathin dielectrics. Conventional wet transfer of © XXXX American Chemical Society
Received: March 18, 2018 Revised: April 17, 2018 Published: May 16, 2018 A
DOI: 10.1021/acs.nanolett.8b01091 Nano Lett. XXXX, XXX, XXX−XXX
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foil was first electrochemically delaminated onto a thermally oxidized silicon substrate (see the Experimental section for details).30,31 The electrochemical delamination is more timeand cost-efficient than conventional wet-etching transfer and can effectively prevent impurities in the Cu substrate from adhering to graphene, thereby leading to cleaner and flatter graphene surfaces. The transferred graphene was then patterned using oxygen plasma etching with 1.2 nm thick Ti as the etch mask (Figure S1a), which later also served as the seed layer for HfO2 deposition. This physically evaporated (deposition rate 0.1 Å/s)32 ultrathin Ti layer was found to effectively protect graphene from the O2 plasma etching (Figure S1a) and help retain the high conductivity of graphene after etching (Figure S1b). The patterning process utilized here avoided the use of hard-to-remove negative-tone resist and minimized contamination to graphene during fabrication. Next, HfO2 was deposited using atomic-layer deposition (ALD), followed by aligned wet−dry transfer of the CVD MoS2 monolayers (Figures 1b and S1b). Briefly, the MoS2 was delaminated onto an elastomer stamp, thoroughly cleaned, and then transferred onto the graphene/HfO2 stack with alignment. Our transfer method provided notable improvement in handling CVD MoS2 monolayers compared to the direct pickup using a polymer stamp (Figure S1e). Compared to typical wet transfer that directly picks MoS2 from water onto the device substrate, the wet-dry transfer reduced trapping of contaminants at the interface of MoS2 and gate oxide and, thus, can enhance gate coupling as well as reduce hysteresis and charge scattering. The Raman spectrum (Figure 1c) of the MoS2/HfO2/graphene stack displayed E12g and A1g bands separated by 19 cm−1 as well as the G and 2D bands, which were characteristic of MoS2 and graphene monolayers, respectively. The strong and spatially uniform signals of MoS2 A1g band and graphene G band in Raman mapping verified the lack of damage to the MoS2 flakes and the bottom graphene gates. Metal contacts (Ni/Au) to MoS2 were defined lithographically to serve as source and drain electrodes (Figure 1d). The average surface roughness of a fabricated MoS2 channel was approximately 0.4 nm (Figure 1e), indicating an atomically flat surface. The use of monolayer graphene as a back gate provided a major improvement in the quality of the dielectric layer. Figure 2a shows the measured leakage current through graphene-gated devices with TiO2/HfO2 gate dielectric stack. When the thickness of HfO2 (tHf) was 16 nm (Figure S2a) or the total oxide thickness (tox) was 17.2 nm, the gate leak current remained below 10 pA before the breakdown of the dielectric at a gate bias of 10 V. This breakdown field of 0.58 V/nm (Figure 2b) is close to the breakdown field of ALD oxide on polished Si substrates33 and approximately twice the value measured with metal bottom gate (Figure S2b and ref 34). Upon decrease of the HfO2 thickness, the breakdown field increased: when tHf was 4 nm or tox was 5.2 nm, the breakdown field was increased to 1 V/nm (Figure 2b), in agreement with a previously reported value.19 We speculate that the improved performance arises from the flatness and low profile of the graphene, which provides a uniform dielectric thickness and eliminates field concentration at edges and sharp points found in thicker metal electrodes (Figure 2c). The dielectric constant of the HfO2/ TiO2 layer was verified using a double-gate graphene FET (Figure 2c), in which the back-gate capacitor was 287 nm SiO2 and the top-gate capacitor consisted of 16 nm HfO2 and 1.2 nm TiO2. The ratio of the top-gate capacitance (CTG) and the back-
devices combining clean CVD films, low contact resistance, and reliable high-k dielectrics have not yet been demonstrated. Here, we present high-performance field-effect transistors derived from chemical vapor deposited (CVD) monolayer MoS2 films with graphene bottom gates. The single-atom-thick graphene shrinks the height of the gate electrode to physical limit and provides a smooth surface for growth of ultrathin high-quality dielectric layers that can achieve electrostatic doping levels above 4.6 × 1013 cm−2. The strong electrostatic control of the contact region leads to low contact resistances down to 2.3 kΩ·μm between Ni and monolayer MoS2 at low gate voltages. These devices achieve near-ideal subthreshold slope (SS = 64 millivolts per decade) at room temperature with negligible hysteresis. Scaled devices with 50 and 14 nm short channels and 5 nm gate dielectric also showed excellent switching characteristics. Furthermore, the graphene gate makes the device highly transparent on flexible polymeric substrate, which is ready for optical-related studies and their applications. By the exploitation of the unique properties of 2D materials and the seamless combination of multiple techniques for material preparation and device fabrication, this work demonstrates a path to the scalable fabrication of highperformance devices using monolayer semiconductors. Results and Discussion. The devices used in this study consist of a monolayer MoS2 channel, contacted by Ni/Au metal electrodes, atop a monolayer graphene back-gate with a thin high-k dielectric layer (Figure 1a). Graphene grown on Cu
Figure 1. Device structure and microscopy characterization. (a) Schematic of the graphene bottom local-gate MoS2 field effect transistor. (b) Optical microscope photo of the MoS2 dry-transferred onto the graphene/HfO2. (c) Raman spectroscopy of the MoS2 and graphene. Inset: Raman mapping of the A1g band (green) and the graphene 2D band (red) over the labeled triangular MoS2 flake in panel b. (d) False-colored scanning electron microscope (SEM) image of a fabricated MoS2 channel contact to metal source and drain electrodes. Yellow: Ni/Au contact. Green: MoS2 on HfO2/graphene. (e) Atomic-force microscope (AFM) image measured along the white dash line in panel d. The surface roughness of the channel region was approximately 0.4 nm. B
DOI: 10.1021/acs.nanolett.8b01091 Nano Lett. XXXX, XXX, XXX−XXX
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can be attributed to the large Rc and the large lateral access resistance (Ru) of ungated MoS2. In this partially gated device, the large Rc and Ru, independent of VGG, significantly slowed the increase of IDS and limited the saturation level of IDS, which led to a high SS and a low on-state current. In contrast, when the graphene gate was extended to gate both the MoS2 channel and the contact region (fully gated), the device turned on more quickly, with a subthreshold slope of 72 millivolts per decade. In addition, the on-state conductance exceeded 10 μS/μm, giving an on-to-off ratio of 107 at a low gate voltage of VGG = 2 V with a threshold voltage (Vth) of 0.4 V. Using transmission line method (Figure 2f) we extracted Rc for the fully gated devices, which reached values as low as 2.3 kΩ·μm at a gate voltage 8.8 V above Vth, corresponding to a displacement field above 8 V/nm or a carrier density of 4.6 × 1013 cm−2. This combination of high carrier density and low contact resistance is critical to reduce the contact resistance and to meet the requirements of the International Technology Roadmap for Semiconductors (ITRS), but has been scarcely demonstrated using undoped monolayer MoS2 at low-gate voltages.18,21 We also note that this approach is simpler and more reliable than other methods used to reduce contact resistance. For instance, local chemical doping and phase transformation can reduce Rc and Ru but generally suffer from low stability. Dual-gate operation, in which the contact areas are gated independently of the channel, gives rise to more negative threshold voltages and complicates device fabrication and operation.7 Importantly, both chemical treatment and dual-gating make device scaling more difficult.35 Based on these results, in the following sections, we examine the performance of devices with the graphene gate extending under the contact region. First, shrinking the channel length for devices with tHf = 16 nm results in a commensurate increase in output current (IDS) to above 70 μA/μm for a 600 nm channel (Figure 3a) and above 100 μA/μm for a 400 nm channel (Figure 3b) at a source-drain voltage (VDS) of 1 V. Both the output curves (IDS−VDS) and the transport characteristics (IDS− VGG) showed saturation stages of IDS at VGG of 6 V. At a higher bias, the current increased more rapidly, possibly due to bandto-band tunneling. The field-effect carrier mobilities μFE (without the exclusion of Rc) ranged from 11.4 to 21.4 cm2 V−1 s−1 (Figure 3c) for channel lengths from 400 nm to 1 μm. These values are comparable with the best results so far reported for CVD monolayer MoS2 at room temperature and similar channel lengths.36 To meet the requirements of the ITRS, the contact resistance can be further reduced to improve the carrier mobility (for example, by using cleaner metal contacts37 or tailoring the metal work function).23 Figure 3d shows the performance of a device with Lch = 1.5 μm and tHf reduced to 8 nm. The device exhibited a SS of 64 millivolts per decade over 3 orders of magnitude in IDS, approaching the thermodynamic limit for field effect transistors at room temperature. Also, the unrecognizable hysteresis (∼46 mV) allowed the device to be turned on and off at low gate voltages (−0.7 to +1.7 V) with a high on-to-off ratio of 2.7 × 108 (Figure S3). This low hysteresis indicates a lack of trapped charges in the dielectric stack, reflecting the lack of dangling bonds in graphene, clean transfer of MoS2, and high-quality HfO2 growth. Also, to evaluate the consistency of the device performance, we fabricated an additional device consisting of eight channels gated by two independent graphene gates (Figure 3e). These channels show highly consistent performance (Figure S4), including low SS values of 67.5 ± 2.6
Figure 2. Characterization of dielectric-layer properties and contact resistance. (a) Gate-leak current IG as a fuction of the gate voltage VG measured with a graphene gate. (b) Breakdown field (EBD) and voltage (VBD) for the graphene-gated devices as a function of the total dielectric thickness (tox). (c) Transport characteristics measured using a double-gate graphene FET (inset) by sweeping top-gate voltage (VTG) at different VSiG values; tHf = 16 nm. (d) Plot of the top-gate Dirac point voltage (VTD) as a function of VSiG. The ratio of the topgate capacitance (CTG) to the SiO2 capacitance (CSiG) was approximately 70. (e) Architectures and transport characteristics of the partially gated and fully gated devices. The channel lengths of both devices were 1.5 μm. (f) Extraction of RC using the transmission line method for the graphene-gated device. Inset: gate-voltage dependence of RC. Error bars represent the standard error of the linear fitting.
gate capacitance (CSiG) was 70, leading to an estimated effective dielectric constant (εox) of 16.4 for the HfO2/TiO2 layer (Figure 2d), consistent with the expected dielectric constants of the HfO2/TiO2 stack (see section 2.2 in the Supporting Information for the calculation of εox). Notably, the large dielectric constant and the high breakdown field of the thin dielectric layer allow the wide modulation of carrier density. For instance, when tHf = 16 nm, an applied gate voltage of 10 V can induce a carrier density of 5.4 × 1013 cm−2. Figure 2e illustrates the influence of the graphene back-gate configuration on the contact resistance and overall device performance using long-channel (1.5 μm) devices made with a relatively thick HfO2 layer (tHf = 16 nm). First, resembling conventional MOSFET configurations, the graphene gate was designed to only gate the channel region (partially gated). Upon sweeping the graphene gate voltage (VGG), the device turned on with a subthreshold slope of 120 millivolts per decade. The channel conductance was saturated at 0.4 μS/μm with a low on-to-off ratio of 105. This suboptimal performance C
DOI: 10.1021/acs.nanolett.8b01091 Nano Lett. XXXX, XXX, XXX−XXX
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Figure 3. Electrical characterization of device performance. (a−c) Characterization of devices with tHf = 16 nm. (a) Output curves (IDS as a function of VDS at different VGG values) for a 600 nm channel. VGG increased from 0 to 9.5 V in 0.5 V steps and then to 9.8 V. (b) Transport characteristics of a 400 nm channel. Inset: transconductance gm as a function of VGG. (c) Field-effect carrier mobilities at different channel length. (d−f) Performance of devices with tHf = 8 nm. (d) Transport characteristics of one device with Lch = 1.5 μm, showing a SS of 64 mV per decade and unrecognizable hysteresis. Inset: zoomed-in section of the subthreshold regime. (e) Microscope photo of a device consisting of eight channels gated by two independent graphene gates. (f) Box plot of the performance parameters for the eight channels.
millivolts per decade, high on-to-off ratios of 1.1 ± 0.9 × 108, and low Vth values of 0.52 ± 0.10 V (Figure 3f). Next, we examine devices with much shorter channel lengths. In such devices, use of an ultrathin dielectric layer is critical to mitigate short channel effects which typically include a decrease in the on-to-off ratio and an increase in SS. In general, the length of the channel that can be effectively controlled by the gate should be 5 to 10 times the natural length scale defined by λ=
εMoS2 εox
Overall, the results reported above represent to date the best performance of intrinsic monolayer MoS2-based FET with standard device configuration, including direct metal contact, single gate electrode, and solid dielectrics (Table 1). To satisfy the requirement of high-performance devices, it is necessary to continue to lower the contact resistance and enhance the electrostatics.19 Moreover, to enable the scalable fabrication of the device, the growth and transfer of graphene and MoS2 needs to be optimized to achieve defect-free and wrinkle-free large-scale monolayers. Finally, we preliminarily examined the performance of the device fabricated on flexible polyethylene naphthalate (PEN) film. The device can be fabricated on the transparent and flexible polymeric substrate thanks to the low temperature (200 °C) needed in the entire fabrication process. With a 17.2 nm thick oxide layer sandwiched between the monolayer graphene and MoS2, the channel region was highly transparent under normal light conditions (Figure 5a). Despite the increased gate leak, the thin-film transistor exhibited excellent switching characteristics, including a low SS of 75.5 millivolts per decade and an on-to-off ratio of 4.8 × 107 (Figure 5b). The increase in the gate leak was attributable to the large roughness of the PEN, and the strain built within the solid dielectric layer during fabrication and handling of the device. Improved insulation of the dielectric under bending status would be needed toward fully flexible devices in the future (for example, by reducing the surface roughness or using more-flexible dielectric materials).11,14 In summary, the bottom local gate consisting of monolayer graphene made it possible to apply strong displacement field through the ultrathin high-k dielectrics. The MoS2 can thus be heavily doped to drastically reduce the contact resistance between the monolayer CVD MoS2 and the metal contact. This improved both the subthreshold performance and the on-state current to a level close to low-power device requirements for
toxt MoS2 , where εMoS2 (3.3)28 and εox are, respec-
tively, the dielectric constants for MoS2 and the gate dielectric and tMoS2 (0.7 nm) and tox (5.2 nm) are, respectively, the thicknesses of the MoS2 and the gate dielectric. Here, we used 4 nm HfO2 with 1.2 nm TiO2 as the gate dielectric for fabrication of short-channel devices, such that εox was 13.3 (see section 2.2 in the Supporting Information) and λ was 0.95 nm, which should be suitable for devices with 10 nm or even shorter channels. We fabricated 50 and 14 nm channels using a twostep lithography and lift-off process (Figurer S5). The gate leak current through the 5.2 nm oxide was tens of picoamps when VGG was below 5 V, which would still allow for effective gate modulation of the channel. The 50 nm device exhibited SS values of 73 millivolts per decade, on-state current exceeding 240 μA/μm and an on-to-off ratio of 3.5 × 107 (Figure 4a,b) at a VDS of 1.6 V. The total source-drain resistance was 6.7 kΩ·μm, close to the value of 3Rc (6.9 kΩ·μm). There was no appreciable saturation stage through the transport characteristics, reflecting the fact that Rc rapidly decreased with VGG to maintain a nearly linear increase of IDS. The 14 nm device showed slight short-channel effects yet a still-reasonable SS of 86.5 millivolts per decade and an on-to-off ratio of 3.3 × 106 (Figure 4c,d) a VDSof 0.1 V. For both channel lengths, the onto-off ratio decreased with VDS (Figure 4e) but remained higher than 105 when VDS was below 2 V, demonstrating effective immunity to short-channel effects. D
DOI: 10.1021/acs.nanolett.8b01091 Nano Lett. XXXX, XXX, XXX−XXX
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Figure 5. Device performance on transparent flexible substrate. (a) Optical microscope photos of a device fabricated on flexible PEN substrate. The thickness of the HfO2 is 16 nm. The upper panel shows the highly transparent MoS2 and graphene gate under normal light conditions, which becomes visible by increasing the contrast (lower left). The lower right is a photograph of a fabricated device. (b) Measurement of the transport characteristics showing a subthreshold slope of 75.5 millivolts per decade.
only benefit device fabrication but also enable the study of material properties under high displacement fields. Also, the bottom-gate design with excellent optical transparency hold promise in various applications such as biosensors, photodetectors, and display backplanes. Experimental Section. Device Fabrication. To transfer the CVD graphene, poly(methyl methacrylate) (PMMA 495 K) was first spin-coated on the graphene grown on copper as a supporting layer. In electrochemical delamination, a twoterminal electrochemical cell was used that consisted of the PMMA/Gr/Cu as a cathode, a bare Cu foil as an anode, and NaOH aqueous solution as electrolyte. The delaminated PMMA/Gr layer was then transferred to a fresh water bath and picked up using the SiO2/Si substrate. The PMMA layer was dissolved in chloroform, and a clean and flat region of graphene was identified under a microscope for use. The geometry of the graphene gate was then defined using e-beam lithography (Elionix ELS-G100), followed by the deposition of 1.2 nm thick Ti using e-beam evaporation (Angstrom EvoVac) at high vacuum (10−7 Torr) and low rate (0.1 Å/s). The Ti layer was allowed to naturally oxidize in air to serve as an etch mask and seed layer for ALD. Metal lead (Ti/Au) to the bottom graphene gate was then patterned lithographically, and the graphene not protected by the Ti layer was etched away using oxygen plasma. HfO2 was deposited using ALD (Fiji G2)
Figure 4. Characterization of short-channel devices. SEM images and transport characteristics of a 50 nm channel (panels a and b) and a 14 nm channel (panels c and d). tHf = 4 nm. The SS was 73 millivolts per decade for the 50 nm channel (VDS = 1.6 V) and 86.5 millivolts per decade for the 14 nm channel (VDS = 0.1 V). (e) On-to-off ratio as a function of VDS. The on-to-off ratio decreased with VDS but remained above 105.
ITRS. Thanks to the enhanced electrostatic gating effect, there was no significant degradation in the device performance upon scaling of the channel length down to 14 nm. This study provides a chemical-free, energy-friendly, and scalable method of achieving high doping levels of 2D materials, which may not
Table 1. Comparison of Device Performance of MoS2-Based FETs MoS2 thickness multilayer
monolayer
six layers 4.5 nm 3−8.6 nm three to five layers 2−7 nm exfoliated monolayer
CVD monolayer
contact material
SSa (millivolts per decade)
conductanceb (μS/μm)
Vth (V)
ref
Cr/Au Au Ni Cr/Au Ni/Au Au graphene Ni Ti/Au Ti/Au Al-ZnO Ni/Au
62 N/Ac 60d 65−74 158 74 75 62d 200 500 116 64−86.5
1 100 350 180 110 5 170 0.3 1 6 1 150
−1 +2 −0.1 −2 −2 −3 −0.7 +0.1 −1 +2 +0.69 ∼0.5
38 21 33 39 2 10 28 33 40 6 41 this work
SS values at room temperature. bThe values reflect the maximum IDS/VDS according to the literature. cN/A indicates “not applicable”. dNegative capacitor (NC) used as gate capacitor to reduce the SS.
a
E
DOI: 10.1021/acs.nanolett.8b01091 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters at 200 °C with tetrakis(dimethylamido)hafnium (TDMAHf) as a precursor. The CVD single-crystal monolayer MoS2 was then aligned to the graphene gate and transferred onto the device (Figure S1). Source and drain contacts (Ni/Au) to MoS2 were defined using e-beam lithography and e-beam evaporation to finish the device. To fabricate devices on PEN, the PEN film (125 μm thick) with one-side adhesion was first attached on a polished Si substrate and baked at 160 °C for 1 min to enhance the adhesion. This allowed us to transfer materials and fabricate electrodes using the same procedure as described above for fabrication on rigid SiO2/Si substrate. Characterization. The Raman spectra of the transferred MoS2 and the bottom graphene gate was taken using a Raman spectroscopy equipped with a 100× microscope (Renishaw) using a pump laser of λ = 532 nm. Measurements of the surface roughness of the fabricated device and the deposition rate of the HfO2 were performed using atomic force microscopy (Park Systems or Bruker FastScan). Scanning electron microscopy images of the devices were taken using Zeiss Sigma VP with an accelerating voltage of 5 kV. Electrical Measurements. Transport characteristics of the devices were measured in a Cascade probe station with a semiconductor analyzer (Agilent 4155C). In measurements of the HfO2/TiO2 dielectric constant using the double-gate graphene FET, a low source-drain bias of 1 mV was used to avoid the generation of a drain-induced nonuniform electrical field along the channel. All measurements were performed at room temperature in air.
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1420634). Y.Z. and Y.L. acknowledge support by Chinese Scholarship Council (grant nos. 201206250034 and 201606210346). The device fabrication made use of the cleanrooms of Columbia Nano Initiative and CUNY ASRC.
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ASSOCIATED CONTENT
S Supporting Information *
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.8b01091. Additional details on the procedures of graphene gate fabrication and wet−dry transfer of CVD MoS2, device characterization, calculation of the effective dielectric constant, statistics of device performance, and shortchannel devices. Figures showing the device fabrication and transfer of MoS2, characterization of the breakdown field of the dielectric stack, transport characteristics, and the fabrication process for sub-20 nm channels. (PDF)
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AUTHOR INFORMATION
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*E-mail:
[email protected]. Phone (212) 854-6244. ORCID
Yibo Zhu: 0000-0003-4323-1290 Won Jong Yoo: 0000-0002-3767-7969 Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS In this work, device fabrication was primarily supported by National Science Foundation (grant no. ECCS-1509760). Electrical testing and characterization was supported by the National Research Foundation of Korea (NRF) Global Research Laboratory (GRL) Program (grant no. 2016K1A1A2912707) and the U.S. NSF MRSEC program through Columbia in the Center for Precision Assembly of Superstratic and Superatomic Solids (grant no. DMRF
DOI: 10.1021/acs.nanolett.8b01091 Nano Lett. XXXX, XXX, XXX−XXX
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DOI: 10.1021/acs.nanolett.8b01091 Nano Lett. XXXX, XXX, XXX−XXX
