Letter pubs.acs.org/NanoLett
Monolithically Integrated InGaAs Nanowires on 3D Structured Silicon-on-Insulator as a New Platform for Full Optical Links Hyunseok Kim,† Alan C. Farrell,† Pradeep Senanayake,† Wook-Jae Lee,*,† and Diana L. Huffaker†,‡ †
Department of Electrical Engineering, University of California Los Angeles, Los Angeles, California 90095, United States California Nano-Systems Institute, University of California Los Angeles, Los Angeles, California 90095, United States
‡
S Supporting Information *
ABSTRACT: Monolithically integrated III−V semiconductors on a silicon-on-insulator (SOI) platform can be used as a building block for energy-efficient on-chip optical links. Epitaxial growth of III−V semiconductors on silicon, however, has been challenged by the large mismatches in lattice constants and thermal expansion coefficients between epitaxial layers and silicon substrates. Here, we demonstrate for the first time the monolithic integration of InGaAs nanowires on the SOI platform and its feasibility for photonics and optoelectronic applications. InGaAs nanowires are grown not only on a planar SOI layer but also on a 3D structured SOI layer by catalyst-free metal−organic chemical vapor deposition. The precise positioning of nanowires on 3D structures, including waveguides and gratings, reveals the versatility and practicality of the proposed platform. Photoluminescence measurements exhibit that the composition of ternary InGaAs nanowires grown on the SOI layer has wide tunability covering all telecommunication wavelengths from 1.2 to 1.8 μm. We also show that the emission from an optically pumped single nanowire is effectively coupled and transmitted through an SOI waveguide, explicitly showing that this work lays the foundation for a new platform toward energy-efficient optical links. KEYWORDS: Nanowire, nanopillar, InGaAs, monolithic integration, optical interconnects, optical links
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compound semiconductors on silicon has also been studied through flip-chip integration,22,23 wafer bonding,24,25 and heteroepitaxy26,27 to utilize the high gains of III−V materials. Heteroepitaxial growth has been less highlighted than flip-chip integration and wafer bonding techniques because of the difficulties stemming from large lattice mismatch, differences of thermal expansion coefficients, and crystal structures between III−V epitaxial layer and silicon substrate. Although flip-chip integration and wafer bonding are more straightforward techniques to integrate III−V materials on silicon, the sacrifice of III−V wafers results in these techniques suffering from high manufacturing costs.28 Recently, dislocation-free epitaxial growth of III−V nanowires on silicon has been demonstrated using metal−organic chemical vapor deposition (MOCVD), owing to the small nanowire cross-section that enables the nanowire to accommodate and relax strain from the lattice-mismatched silicon without metamorphic buffer layers.29 There have been reports on several photonic devices30−33 monolithically integrating InGaAs nanowires on Si because the InGaAs nanowire is one of the attractive ternary materials for photonics and optoelectronic applications due to its wide bandgap tunability covering nearinfrared and telecommunication wavelengths.34 However, high
ptical links (OLs) have begun to emerge as a potential solution for energy-efficient (green) data centers because of the increase of global dependence on web-based electronic commerce that consumes the output of about 30 nuclear plants worldwide.1−3 Because OLs offer low power consumption, large communication bandwidth, and long transmission distance, they are being explored extensively for board-toboard,4,5 chip-to-chip,6,7 and on-chip8−10 data links as a replacement for copper-based wires. Over the past few years, the board-to-board and the chip-to-chip (intraboard) interconnects using vertical-cavity surface-emitting lasers have become well-established. Many researchers have reported on the development of chip-level (intrachip) photonic components such as light sources,11,12 electro-optical modulators,13−15 and photodetectors.16−18 However, full OLs on silicon or silicon-on-insulator (SOI) including lasers and photodetectors, which link the electrical and optical elements, integrated on the same chip toward monolithic large-scale integration and CMOS-compatible processes are still required for energy and cost efficiency. Germanium lasers on silicon through bandgap engineering have attracted much attention in recent years due to the ease of monolithic integration and their compatibility with the CMOS process.19−21 However, the optical gain of germanium lasers needs to be further improved for practical applications, which is in contrast to germanium photodetectors on silicon which are already successfully used for OLs.21 The integration of III−V © XXXX American Chemical Society
Received: November 30, 2015 Revised: February 18, 2016
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DOI: 10.1021/acs.nanolett.5b04883 Nano Lett. XXXX, XXX, XXX−XXX
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Figure 1. Schematic illustrations of InGaAs nanowires on an SOI platform for OL components. (a) Nanowire arrays on a planar SOI. (b) Nanowire arrays on grating structures. (c) Single nanowire on a waveguide structure.
buried oxide (BOx) layer thickness of 2 μm, and a Si substrate thickness of 675 μm is used for the nanowire growth. The SOI layer was first thinned by thermally oxidizing the SOI layer and removing the thermal oxide using a 6:1 buffered oxide etch (BOE) solution. Because particular SOI layer thicknesses are required for respective applications and operation regimes, we show the validity and practicality of the proposed platform by integrating nanowires on a thinned SOI substrate. Here, the SOI layer thickness was reduced from 2 μm to 220 nm. The thinned wafer was then patterned into gratings and rib waveguides by dry etching, using an e-beam resist as an etchmask. The depth of the Si trenches was controlled to be 180 nm. After stripping the etch-mask, a 20 nm-thick Si3N4 layer was deposited using low pressure chemical vapor deposition (LPCVD), and nanoholes were patterned on the Si3N4 layer by e-beam lithography and dry etching. Predefined alignment markers were used to precisely align the position of the nanoholes on the 3D structured SOI layer. A detailed description of the sample preparation procedure can be found in Supporting Information. The nanowire growth was carried out by catalyst-free SAE using a low-pressure (60 Torr) Emcore D-125 MOCVD system, where hydrogen was used as a carrier gas. The precursors used were trimethylindium (TMIn), trimethylgallium (TMGa), and tertiarybutylarsine (TBAs). The native oxide on the exposed Si was stripped using a 6:1 BOE solution for 30 s and rinsed using deionized water for 20 s followed by drying with compressed nitrogen gas. The sample was then directly loaded into the MOCVD chamber. The reactor temperature was ramped up to 870 °C under hydrogen ambient and held for 10 min to remove the native oxide possibly formed while transferring the sample into the chamber. After thermal etching of the native oxide, the temperature was ramped down to the nanowire growth temperature, where the growth temperature was fixed to 670 °C. TMIn, TMGa, and TBAs were then turned on simultaneously to initiate the InGaAs growth, and the flow rates of the precursors were kept constant during the nanowire growth step. To tune the Indium and Gallium composition in the nanowires, we have grown several samples under different TMIn and TMGa flow rate. The partial pressure of TMIn and TMGa was varied from 1.55 × 10−5 atm to 3.27 × 10−5 atm and from 3.52 × 10−5 atm to 4.69 × 10−5 atm, respectively, while the total group III flow was kept constant within 5% error. Assuming that TMIn and TMGa were fully decomposed in the reactor, In/(In + Ga) flux was varied from 25% to 48%. The partial pressure of TBAs was fixed to 8.31 × 10−4 atm and the V/III flow rate ratio was fixed to 13. After the growth, the samples were cooled down under TBAs overpressure to prevent desorption of arsenic from the InGaAs nanowires.
performance nanowire-based on-chip laser sources and photodetectors for on-chip optical communication are still challenging. In order to achieve full OLs for low power consumption and cost efficiency, it is essential that the active components are monolithically integrated on 3D structured SOI substrates, such as waveguides and gratings. Such components can be obtained by catalyst-free selective-area epitaxy (SAE) which offers a large degree of freedom in device design including photonic crystal cavities, and nanowire-based photodetectors and light sources. In this Letter, we show for the first time monolithically integrated InGaAs nanowires on 3D structured SOI substrates as well as planar SOI substrates by catalyst-free SAE. InGaAs nanowires integrated on SOI gratings and SOI waveguides suggest the feasibility of nanowire-based photonic components as a new platform for OLs. It is also demonstrated that the composition of InGaAs nanowires can be broadly tuned, covering the telecommunication wavelengths of both 1.31 and 1.55 μm. To prove the validity of the new platform for the proposed nanowire-based photonic devices, we experimentally show light emission from an SOI grating, which is coupled with an optically pumped single nanowire through a waveguide. The proposed platform based on nanowires offers an original approach for compact and energy-efficient OLs. The proposed nanowire-based SOI platform is illustrated in Figure 1. Vertical III−V nanowires are monolithically integrated on SOI substrates, where dielectric masks on SOI layers control the position of the nanowires. The nanowire arrays grown on planar substrates, the most straightforward structure as shown in Figure 1a can be used not only as passive photonic crystal devices,35 but also as photonic crystal cavities.36 However, the leakage of photons into the underlying substrate degrades the vertical confinement, which challenges the realization of high quality (Q) factor photonic crystal cavities without detaching the nanowires from the substrate.36 Recently, we have theoretically shown that a well-designed nanowire arrays on SOI grating structures, as shown in Figure 1b, can greatly improve the Q factor by enhancing the vertical confinement, resulting in this structure being suitable for on-chip monolithic light sources.37 Lastly, a single nanowire standing on an SOI rib waveguide (Figure 3c) can be used either as (1) a compact light source where the emitted light is directly coupled into the underlying waveguide, and/or (2) a photodetector having a submicron size and ultralow capacitance for energy-efficient onchip OLs, which can substitute current Ge-based photodetectors having the size of ∼10 μm (length) × 2 μm (width) × 0.25 μm (height)3.22 To demonstrate the proposed nanowire-based SOI platform, a lightly p-doped (boron, 10 Ω·cm) SOI (111) wafer (SEH America Inc., USA) with an SOI layer thickness of 2 μm, a B
DOI: 10.1021/acs.nanolett.5b04883 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters We adopted a vapor−solid (VS) SAE method for our growth, because the precise positioning of the nanowires is essential for our proposed platform. While many of the previously reported methods depend on different growth mechanisms such as self-assembled growth on a bare Si substrate,33 growth from a mechanically roughened surface,38 and growth from dispersed Au catalysts,39 these methods lack nanowire position controllability. The vapor−liquid−solid (VLS) growth using a Au catalyst lift-off process40 or group III droplet positioning41 is able to control the nanowire position, but such catalyst-assisted VLS growth modes are known to suffer from deep-level trap formation by Au incorporation as well as the nanowire compositional inhomogeneity.42 Thus, the catalyst-free VS SAE method is seemingly adequate approach, while this method is relatively unexplored and less understood technique. So far, only two groups from Hokkaido University43 and Technical University of Munich44 have reported the growth of InGaAs nanowires on Si with this method using MOCVD and molecular beam epitaxy (MBE), respectively. However, In-rich nature of the reported InxGa1−xAs nanowires (x = 0.743 and x = 0.64−1.044) implies that InGaAs nanowires having emission spectra covering telecommunication wavelengths are still unexplored even on a bulk Si. The InGaAs nanowires grown on the SOI platform is shown in Figure 2, in which In/(In + Ga) flux during the growth was set to 43%. All images are taken from different areas of the same sample, and the diameter of the nanoholes on the mask was 40 nm. The pitch of the nanowire arrays on the planar surface is 1000 nm (Figure 2a) and 500 nm (Figure 2b), where the total array size is both 50 × 50 μm2. In Figure 2c, the SOI grating has a period of 600 nm, a duty cycle of 50%, and a total size of 5 × 5 μm2. The SOI waveguide in Figure 2d has the width of 440 nm, where a single nanowire is standing on the waveguide center. First of all, it should be highlighted that InGaAs nanowires are grown successfully both on the planar surfaces and the 3D structured surfaces under the same growth condition. To the best of our knowledge, this is the first time that vertical nanowires are integrated on 3D structured substrates. The nanowire arrangements and the substrate structures shown in Figure 2a and b, Figure 2c, and Figure 2d directly correspond to the schematics in Figure 1a, Figure 1b, and Figure 1c, respectively. This explicitly confirms that it is possible to monolithically integrate InGaAs nanowires on the proposed platform. Given that the position-controlled nanowire growth is achieved regardless of the array size and the substrate structures, this flexibility makes the proposed platform very powerful in such a way that various photonics and optoelectronics components can be simultaneously integrated. Interestingly, the size and the aspect ratio of the nanowires are all similar except for the case when nanowires are densely packed in a large array (Figure 2b). In the cases when the nanowires are sparsely spaced in a large array (Figure 2a), densely spaced in a small array (Figure 2c), and when there is only a single nanowire (Figure 2d), the morphology of the nanowires are all similar, having the diameter of 210 nm and the height of 1100 nm within 6% error. On the other hand, the nanowires densely spaced in a large array (Figure 2b) show the diameter of 170 nm and the height of 1300 nm, suggesting that the nanowires are thinner and taller. Meanwhile, the effect of the substrate trenches on the nanowire morphology is not observed. This can be explained by the considering the
Figure 2. SEM images of InGaAs nanowires on an SOI platform. Nanowire arrays on planar areas with (a) 1000 nm pitch and (b) 500 nm pitch. Insets in (a) and (b) show magnified images of nanowires in each array. (c) Nanowire array on a grating structure. (d) Single nanowire on an SOI waveguide structure. All images are tilted 30° from the normal view.
mechanism of the VS SAE nanowire growth. In the catalyst-free nanowire growth, there are three sources of adatoms contributing to the vertical nanowire growth; (1) adatoms directly incorporating on the top facet of a nanowire, (2) adatoms adsorbed on the nanowire side facets diffusing to the nanowire tip, and (3) adatoms on the mask surface area diffusing to nearby nanowires; where the contribution from the side facet adsorption dominates the other two sources.45−47 Because the amount of adatoms adsorbed on the side facets is identical in the nanowires having the same diameter,45 the dimensions of the nanowires grown from the same size of the nanoholes should also be similar, as evidenced in Figure 2a, c, and d. This also clarifies why the trenches around the nanowires do not visibly affect the nanowire growth. Assuming that the trenches do not affect the carrier gas flow on the surface, these trenches act just as additional paths for the adatoms on the mask surface to diffuse. In the same manner, the sidewalls of the trenches can be regarded as additional mask areas. Therefore, the presence of trenches can be interpreted as an increase of the effective mask area per nanowire. Although the effect of trenches on the nanowire morphology is not observed due to the minor contribution of the mask surface diffusion on the growth, we predict that nanowires will grow larger in height and diameter if surrounding trenches are deep enough. To conclude, the effects coming from different array C
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Figure 3. (a) Normalized photoluminescence spectra of InGaAs nanowire arrays grown by different In/(In + Ga) flux, measured at 77 K. (b) In/(In + Ga) composition of InGaAs nanowires as a function of In/(In+Ga) flux.
has not been achieved yet in the position-controlled InGaAs nanowire on Si system. Although the solid-phase composition of group III materials in the III−III−V system directly follows the gas-phase composition in the case of film growth,53 the amount of indium incorporated in the nanowires was larger than the Indium flux in our case, as shown in Figure 3b. This is due to the different growth mechanisms between the film growth and the selective-area nanowire growth. Unlike the case of film growth where adatoms are directly absorbed on top of the film, there are additional sources contributing to the nanowire growth such as the mask diffusion and the re-evaporation from the mask. Although a complete theory quantitatively explaining the contribution of respective sources in the nanowire growth is not established yet, we suspect that the reason indium composition in the solid phase is larger than that in the gas phase is because indium has longer diffusion length and higher evaporation rate than gallium on the masked area.42,54 To further investigate the material quality of the InGaAs nanowires on the SOI platform, we performed cross-sectional SEM and transmission electron microscopy (TEM) measurements of the In0.32Ga0.68As nanowires on the SOI grating structure where the diameter of nanoholes for the nanowire growth was 90 nm. The sample is sliced by focused ion beam (FIB) etching for TEM measurements, as shown in Figure 4a. The cross-sectional SEM images in Figure 4a and b clearly show the 3D structured SOI layer on top of the buried oxide layer, and also the InGaAs nanowires vertically grown on top of the SOI grating structure with fine alignment. Stacking faults are observed along the nanowire (Figure 4c,d), which is also reported for InGaAs nanowires grown on Si by VS SAE.42,43 Although stacking faults are undesirable crystal defects degrading electrical and optical properties, we believe that the stacking faults can be eliminated by precisely controlling the growth temperature and the V/III flow rate ratio.42 It is also worth mentioning that there is no threading dislocation observed in Figure 4e despite a lattice mismatch as large as 6.6% between InGaAs and Si. In contrast, although a compliant SOI substrate instead of a Si substrate is known to improve the quality of the epitaxial layer grown on top by releasing the strain,55 III−V films grown on SOI substrates still exhibit high density of threading dislocations.56 This strongly supports our claim that the proposed nanowire-based platform is a promising alternative for the next-generation photonics and optoelectronics applications.
sizes and from the structures on the surfaces are not substantial enough to be reflected on the size of the nanowires. The remaining question is why the nanowires in a dense and large array (Figure 2b) grow thinner and taller than the others. We attribute this as a result of increased V/III flow rate ratio around the dense nanowire arrays. The diffusion coefficient of group III adatoms on the nanowire {1−10} side facets increases under high As pressure,48 and this leads the III−As nanowires to grow taller and thinner to a certain extent as the V/III flow rate ratio increases.49 As group III materials tend to be depleted much faster than Arsenic during the competitive absorption process by dense nanowires,50 the local V/III flow rate ratio is the largest around the dense and large array (Figure 2b), leading to the thinnest and the tallest nanowires. From this observation, we suspect that the axial growth and lateral overgrowth could be effectively and individually engineered by using proper nanohole arrangements and compensation patterns, which can augment the proposed platform by giving additional flexibility. The optical property of the InGaAs nanowires grown on the SOI layer under different In/(In + Ga) flux is investigated by photoluminescence (PL) measurement. The nanowire arrays are optically pumped using a 660 nm diode laser with 900 μW pump power, which corresponds to the pump power density of approximately 4.6 kW/cm2. The emission spectra are measured using Fourier transform infrared spectroscopy at 77 K. To prevent CO2 and H2O absorption, the measurement is performed in a nitrogen-purged box. Figure 3a shows the normalized PL spectra of four InGaAs nanowire arrays grown under different In/(In + Ga) flux ranging from 25% to 48%. It is found that the peak emission wavelengths vary from 1175 nm (25% indium flux) to 1755 nm (48% indium flux), indicating a wide range of compositional tunability covering telecommunication wavelengths. For more detailed analysis, solid-phase material compositions in the nanowires are calculated from the PL spectra. We applied the Varshni formula51 and used the bowing parameter of −0.475 eV52 to derive the Indium composition. Assuming that the bandgap is kBT/2 below the peak emission energy and the strain in the nanowire is fully relaxed, the solid-phase In/(In+Ga) compositions are varied from 32% (In0.32Ga0.68As) to 64% (In0.64Ga0.36As) by changing the Indium flux from 25% to 48% as shown in Figure 3b. kB and T denote the Boltzmann constant and the temperature, respectively. In other words, we have successfully demonstrated the InGaAs nanowires with intermediate In and Ga compositions covering telecommunication wavelengths, which D
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Figure 4. (a) Cross-sectional SEM images of an InGaAs nanowire array on a grating structure viewed at an angle. (b) Magnified SEM image of the dashed box in (a) viewed at a horizontal direction. (c) Cross-sectional TEM image of a middle part of a nanowire. (d) TEM image of bottom part of a nanowire. (e) Magnified TEM image of the dashed box in (d).
Lastly, the validity of the proposed platform is substantiated by experimentally showing that InGaAs nanowires can be used as light sources directly coupling into SOI waveguides. A single nanowire standing on an SOI waveguide (Figure 5a) is optically pumped using a 633 nm He−Ne laser with 1200 μW pump power, which is equivalent to the pump power density of 6.1 kW/cm2, and the emission spectra are measured on the waveguide edge as well as on top of the nanowire to investigate the coupling characteristics. The emission spectra were measured using an InGaAs focal plane array detector with a 50× objective lens oriented normal to the substrate. The nanowire is positioned on the center of the SOI rib waveguide, where the waveguide has a rib height of 220 nm, a rib width of 440 nm, and a slab height of 40 nm. The length of the waveguide between the nanowire and the waveguide edge is 500 μm, and a grating coupler is patterned at the waveguide edge to couple out the light and measure its spectra on the normal direction (Figure 5b). All measurements were performed at room temperature without nitrogen purging. The spectrally integrated images in Figure 5c and d represent the spatial emission intensities measured on top of the nanowire and the waveguide edge diffracted by the grating coupler, respectively. This result explicitly shows that nanowires on SOI waveguides can be employed as active components, such as ultracompact light sources and photodetectors. The nominal efficiency calculated from the spectra in Figure 5e is 0.57%, which is derived by dividing the integrated emission intensity measured on the waveguide edge by that on the nanowire. Thus, this efficiency takes into account (1) the coupling-in efficiency, which is the portion of the emitted light coupling into the SOI waveguide, (2) the propagation loss of the SOI waveguide, and (3) the coupling-out efficiency on the waveguide edge. On the other hand, optical simulations have predicted that the coupling efficiency of a single nanowire emitter with an underlying SOI waveguide will be around 1.0%. Thus, the measured efficiency reasonably matches with the theoretical efficiency, considering that the sidewall roughness of the SOI waveguide, the coupling-out efficiency on the waveguide edge, and the collection efficiency of the objective
Figure 5. SEM images of (a) a single InGaAs nanowire on an SOI waveguide and (b) a waveguide edge. The length of the waveguide is 500 μm. Spectrally integrated images measured on (c) the nanowire region and (d) the waveguide edge by optically pumping the nanowire. (e) Photoluminescence spectra measured on the nanowire region and the waveguide edge at room temperature. The emission from the waveguide edge is magnified 30 times for visibility. All scale bars in (a)−(d) represent 2 μm.
lens on top of the nanowire and the waveguide edge are not taken into account in the simulation. We note that although the intensity of the light coupling out of the waveguide is much weaker than the emission measured from the nanowire itself due to the low coupling efficiency, the efficiency can be greatly improved by introducing cavity structures.57 In conclusion, for the first time, we have shown that threading dislocation-free InGaAs nanowires can be epitaxially grown on 3D structured SOI layers as well as planar SOI layers with a position controllability and a wide composition tunability. These features allow a high degree of freedom in designing nanowire-based devices such as rod-type photonic crystals. We have also proposed a novel nanowire-based SOI platform for energy-efficient on-chip OLs by demonstrating a single nanowire acting as a light source where the emitted light directly couples into a SOI waveguide. We believe that the proposed nanowire-based SOI platform provides the opportunity for the next-generation on-chip optical communication systems as a stepping stone.
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ASSOCIATED CONTENT
S Supporting Information *
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b04883. E
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Detailed sample preparation procedures, additional optical property characterization of nanowires, and the comparison of nanowires grown on SOI with bulk Si (PDF)
AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors gratefully acknowledge the generous financial support of this research by AFOSR (through FA9550-15-10324) and by NSF (through ECCS-1202591 and DMR1309137). The authors also would like to thank Yangjung Lee at the University of California, Los Angeles, for helpful discussions.
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