Multilevel MoS2 Optical Memory with Photoresponsive Top Floating

Jun 25, 2019 - Optoelectronic memory devices, whose states can be controlled using electrical optical signals, are receiving much attention for their ...
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Cite This: ACS Appl. Mater. Interfaces 2019, 11, 25306−25312

Multilevel MoS2 Optical Memory with Photoresponsive Top Floating Gates Sung Hyun Kim, Sum-Gyun Yi, Myung Uk Park, ChangJun Lee, Myeongjin Kim, and Kyung-Hwa Yoo* Department of Physics, Yonsei University, 50 Yonsei-ro, Seoul 03722, Republic of Korea

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ABSTRACT: Optoelectronic memory devices, whose states can be controlled using electrical optical signals, are receiving much attention for their potential applications in image sensing and parallel data transmission and processes. Here, we report MoS2-based devices with top floating gates of Au, graphene, and MoS2. Unlike conventional floating gate memory devices, our devices have the photoresponsive floating gate at the top, acting as a charge trapping layer. Stable and reliable switching with an on/off ratio of ∼106 and a retention time of >104 s is achieved by illumination with 405 nm light pulses as well as application of gate voltage pulses. However, upon illumination with 532 or 635 nm light pulses, multilevel optical memory effects are observed, which are dependent on the wavelength and the optical exposure dosage. In addition, compared to the device employing a graphene floating gate, the device with an MoS2 floating gate is more sensitive to light, suggesting that the multilevel optical memory properties originate from photoexcited carriers in the top floating gate and can be modulated by adjusting the top floating gate materials. The structure of the top floating gate may open up a new way to novel optoelectronic memory devices. KEYWORDS: multilevel nonvolatile optical memory, photoresponsive top floating gate, optoelectronic devices, 2D flash memory, MoS2

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INTRODUCTION

memory effects result from photogenerated carriers in the channel layer. Herein, we report MoS2-based devices with a top floating gate of Au, graphene, or MoS2, as shown in Figures 1b and 2a− c. Unlike the reported hybrids10−12 and conventional floating gate memory devices,20 the floating gate is at the top, and the MoS2 channel layer is below it. Hysteric source−drain current (ISD)−gate voltage (VG) transfer curves and electrostatic force microscopy (EFM) images revealed that the top floating gate acted as a charge trapping layer, although it was at the top. Accordingly, all devices exhibited nonvolatile memory effects with an on/off ratio of ∼106 and a retention time of >104 s. Furthermore, the devices with a photoresponsive top floating gate, such as graphene or MoS2, could be controlled by light pulses and gate voltage pulses. In particular, upon illumination with 532 or 635 nm light pulses, multilevel optical memory properties were observed, because the photon energy of these light pulses was lower than the tunneling barrier height from the top floating gate to the MoS2 channel. These multilevel optical memory states were dependent on the wavelength and linearly responsive to the light exposure dosage, suggesting that the device with the photoresponsive top floating gate can be applied as a filter-free color image sensor.

Atomically thin two-dimensional materials such as graphene, semiconducting transition-metal dichalcogenides, and insulating hexagonal boron nitride (hBN) are promising building blocks for next-generation electronic and optoelectronic devices because of their unique electrical, optical, and mechanical properties.1−6 Among them, optoelectronic memory devices, whose states can be modulated using electrical and optical signals, are attracting increasing attention for their potential applications in image capturing and visual information processes, integrated photonics, in-memory computing, neuromorphic computing, and parallel data transmission and processes.7−19 Recently, optical memory properties were reported in MoS2/graphene,7 MoS2/functionalized SiO2,8 and CuIn7Se11,9 in which the optical memory effects originate from photoinduced charge trapping and detrapping in defects and disorders. However, these devices are unsuitable for practical applications because of their low on/off ratio and short retention. Multibit nonvolatile optical memory effects with a retention time of >104 s were reported in various hybrids, including WSe2/hBN,10 MoS2/cross-linked poly(4-vinylphenol)/Au nanoparticles,11 and MoS2/hBN/graphene,12 where charges are stored in hBN, Au nanoparticles, or graphene, instead of defects. In these hybrids, a channel layer is at the top, and a charge trapping layer is under it; thus, the optical © 2019 American Chemical Society

Received: March 28, 2019 Accepted: June 25, 2019 Published: June 25, 2019 25306

DOI: 10.1021/acsami.9b05491 ACS Appl. Mater. Interfaces 2019, 11, 25306−25312

Research Article

ACS Applied Materials & Interfaces

Figure 1. (a) ISD−VG transfer curve measured for an MoS2 FET by sweeping VG from −50 to +50 V and then back to −50 V. The inset shows a schematic of the structure of the MoS2 FET. (b) Schematic of the structure of device I. (c) Optical image of the fabricated device I. (d) ISD−VG transfer curve measured for device I by sweeping VG from −50 to +50 V and then back to −50 V. The inset shows the ISD−VG transfer curve on the logarithm scale. (e) Retention test of device I with a reading voltage of VSD = 0.1 V. The on and off states were induced by applying gate voltage pulses of −40 and +40 V, respectively, with a pulse width of 1 ms. The inset shows the endurance performance of device I with a reading voltage of VSD = 0.1 V. See Figure S1 for more cycles. (f) Energy band diagram of device I (flat band diagram). χ and φ represent the electron affinity and work function, respectively. The energy band diagrams of device I upon application of (g) high positive gate voltage pulse and (h) high negative gate voltage pulse. (i) EFM images measured for device I in the off (top) and on (bottom) states. (j) Line profiles of the height and EFM signals obtained via AFM (Figure S2) and EFM images of device I. The yellow color indicates the region of the Au floating gate.

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retention time of >2 × 104 s. We also performed an endurance test by repeatedly applying gate voltage pulses of −40 or +40 V with a pulse width of 1 ms (inset of Figures 1d and S1). Stable and reliable switching with an on/off ratio of 106 was achieved over 100 cycles. These results suggest that the Au pattern served as a charge trapping layer or floating gate. Thus, device I exhibited nonvolatile memory effects similar to those of conventional flash memory devices, although the structure of device I differed from that of conventional flash memory devices, in which the charge trapping layer is placed between a channel and a control gate.20,21 The proposed energy band diagrams for device I are shown in Figure 1f−h. The energy band gap (Eg) and electron affinity (χ) are approximately 1.2 and 4 eV, respectively, for the multilayer MoS224 and 6 and 2 eV, respectively, for hBN.25 The workfunction (φ) is 4.4 and 5.1 eV for MoS2 and Au, respectively (Figure 1f).24 When a high positive voltage is applied to VG (VG ≫ 0), the Fermi energy level of the MoS2 channel shifts upward, and the hBN tunnel barrier becomes triangular because the applied gate voltage is not fully screened by MoS2 (Figure 1g).26 Consequently, the electrons tunnel from the MoS2 channel to the Au through hBN, most likely via the Fowler−Nordheim tunneling. However, when VG = 0, electron tunneling between MoS2 and Au is not allowed, because of the high tunneling barrier. Thus, if a high positive voltage pulse is applied to VG, the electrons transferred from the MoS2 at VG ≫ 0 are trapped in the Au, leading to the off

RESULTS AND DISCUSSION First, we fabricated an MoS2 field-effect transistor (FET) by transferring a mechanically exfoliated few-layer MoS2 flake (3 nm) onto an hBN (20 nm)/SiO2/p++-Si substrate. As reported previously,21,22 the ISD−VG transfer curves measured by sweeping VG from −50 to +50 V and back to −50 V exhibited typical n-type semiconducting behavior without hysteresis (Figure 1a), where the highly doped Si substrate was used as a gate electrode. Next, we transferred an hBN flake (16 nm) onto the MoS2 layer. This transferred hBN flake did not change the ISD−VG transfer curves. Subsequently, we formed an Au pattern (30 nm) on the hBN layer (device I, Figure 1b,c). Interestingly, the ISD−VG transfer curves measured for device I exhibited large hysteresis (Figure 1d). Because no hysteresis was observed before depositing the Au pattern, the hysteresis was considered to be directly associated with the Au pattern. Similar hysteric ISD−VG transfer curves were reported for MoS2 devices with a structure similar to that shown in Figure 1b.23 To investigate whether device I exhibits nonvolatile memory effects, we measured the ISD at VSD = 0.1 V over time after a voltage pulse of −40 or +40 V with a pulse width of 1 ms was applied to VG (Figure 1e). The voltage pulses of −40 and +40 V caused switching to the high on current of ∼1.7 × 10−7 A and the low off current of ∼1.6 × 10−13 A, respectively, and the on and off currents remained almost unchanged for 2 × 104 s, indicating that device I was a nonvolatile memory device with a 25307

DOI: 10.1021/acsami.9b05491 ACS Appl. Mater. Interfaces 2019, 11, 25306−25312

Research Article

ACS Applied Materials & Interfaces

Figure 2. (a) Schematics of the structures of devices II and III. Optical images of devices (b) II and (c) III. (d) ISD−VG transfer curves measured for devices II (black) and III (red) by sweeping VG from −40 to +40 V and then back to −40 V. The inset shows the ISD−VG transfer curve on the logarithm scale. (e) Endurance performance of device II with a reading voltage of VSD = 0.1 V. The on and off states were induced by applying gate voltage pulses of −40 and +40 V, respectively, with a pulse width of 1 ms. See Figure S3a for more cycles. The inset shows the endurance performance of device II with a reading voltage of VSD = 0.1 V. The on state was induced via illumination with the 405 nm light pulse, whereas the off state was induced by applying a gate voltage pulse of +40 V with a pulse width of 1 ms. (f) ISD of device II measured at VSD = 0.1 V when light pulses were applied every 30 s, with a wavelength (λ) of 532 nm, an exposure time (Δt) of 0.1 s, and different laser powers. (g) ISD of device II measured at VSD = 0.1 V when light pulses (Δt = 0.1 s, P = 4 nW) with λ = 532 (green) and 635 (red) nm were applied every 30 s. (h) ISD of device III measured at VSD = 0.1 V when light pulses (Δt = 0.1 s) with λ = 532 (green) and 635 (red) nm were applied every 30 s. (i) ISD measured for devices II and III at VSD = 0.1 V when light pulses (P = 2 nW and λ = 532 nm) with different pulse widths were applied every 30 s.

I. These findings indicate that the structure with a top floating gate (e.g., devices I and II) can be regarded as a new structure of the nonvolatile memory device. In device II, the photoresponsive charge trapping layer is on top, in contrast to the conventional floating gate memory devices; therefore, it can possibly be controlled by light as well as the gate voltage. To investigate this, we measured the ISD when a 405 nm laser with a power (P) of 1 nW was turned on for 0.1 s and then turned off (inset of Figure 2e). Upon illumination, the ISD increased from ∼2.1 × 10−13 to 2.7 × 10−7 A, and the high on current was maintained even when the light was turned off. Subsequently, when a voltage pulse of +40 V with a pulse width of 1 ms was applied to VG, the ISD returned to the low off current. Similar to the case of gate voltage pulses, the on/off ratio was approximately 106 and the retention time was >2 × 104 s (Figure S3b), indicating that device II can be controlled by light pulses as well as gate voltage pulses. Figure 2f shows the ISD measured at VSD = 0.1 V while a 532 nm laser with different laser powers was repeatedly turned on for 0.1 s and off for 30 s. Unlike the case of the 405 nm laser, the 532 nm light pulses did not increase the ISD to the high on current. The increase in the ISD was significantly smaller during illumination, and when the light was off, the ISD returned to a value higher than the initial value and remained at this value. Furthermore, each time the light pulses were applied, the ISD increased almost linearly with respect to the number of light pulses, and the increment of the ISD was dependent on the laser power. Similar measurements were carried out using a 635 nm

state. On the other hand, if a negative voltage pulse is applied to VG, the Fermi energy level of the MoS2 channel shifts downward (Figure 1h). Thus, the tunneling barrier from the Au to the MoS2 channel is lowered, and the electrons are transferred back to the MoS2 channel from the Au, leading to the on state. To confirm that the Au pattern really played a role of charge trapping layer, we obtained EFM images for device I after applying gate voltage pulses of +40 or −40 V with a pulse width of 1 ms (Figure 1i). Distinct electrostatic potentials between the off and on states were observed only in the Au pattern (Figure 1j). Because negative EFM signals indicate the accumulation of negative charges,27,28 the EFM images support that the off state resulted from the trapping of electrons in the Au floating gate, whereas the on state was caused by the release of electrons from the Au floating gate. Next, we fabricated a device with a graphene top floating gate (device II, Figure 2a,b) to investigate whether the memory effects also occur with a top floating gate of a material other than Au. Similar to device I, large hysteresis was observed in the ISD−VG transfer curve of device II measured by sweeping from −40 to +40 V and then back to −40 V (Figure 2d). Figure 2e shows the ISD measured at the VSD = 0.1 V after the repeated application of gate voltage pulses of −40 or +40 V with a pulse width of 1 ms. Stable and reliable switching behaviors with an on/off ratio of approximately 106 and a retention time of >2 × 104 s were obtained over 300 cycles (Figures 2e and S3a), which are comparable to those of device 25308

DOI: 10.1021/acsami.9b05491 ACS Appl. Mater. Interfaces 2019, 11, 25306−25312

Research Article

ACS Applied Materials & Interfaces

Figure 3. (a) Energy band diagram of device II in a flat band state. Energy band diagrams of device II upon (b,c) application of a high positive gate voltage pulse and upon illumination with (d) 405, (e) 532, and (f) 635 nm light pulses. Φ represents the tunneling barrier height from the top floating gate to the MoS2 channel. (g) Energy band diagram of device III in a flat band state. (h,i) Energy band diagrams of device III upon application of a high positive gate voltage pulse and upon illumination with (j) 405, (k) 532, and (l) 635 nm light pulses.

remained nearly unchanged for >2 × 103 s, confirming that the multilevel optical memory states were nonvolatile. To explain the multilevel optical memory effects observed for device II, we propose the energy band diagrams shown in Figure 3a−f, where the workfunction of graphene is assumed to be 4.56 eV.29 Similar to the case of device I, if a high positive voltage pulse is applied to VG, electrons tunnel from the MoS2 channel to the graphene floating gate through hBN because of the lowered tunneling barrier, leading to the off state (Figure 3b,c). Then, if light is illuminated, the electrons trapped in graphene are photoexcited. The tunneling barrier height (Φ) from the graphene floating gate to the MoS2 channel is estimated to be approximately 2.56 eV. Thus, upon illumination with a 405 nm (3.05 eV) light pulse, electrons trapped in the graphene acquire enough energy from photons to tunnel from the graphene floating gate to the MoS2 channel; thus, almost all electrons in the graphene transfer back to the MoS2 channel, leading to a high on current (Figure 3d). However, if 532 nm (2.33 eV) or 635 nm (1.95 eV) light pulses are applied, all electrons in the graphene do not have enough energy to tunnel to the MoS2 channel; thus, only a fraction of electrons are transferred back to the MoS2 channel (Figure 3e,f). The number of transferred electrons depends on the wavelength and the optical exposure doses given by P·Δt. Thus, the observed multilevel optical memory effects, which

laser (Figure S4). As with the 532 nm laser, the ISD increased stepwise, and its increment was dependent on the laser power. However, at the same laser power, the increase in the ISD was smaller under the 635 nm light pulses than under the 532 nm light pulses (Figure 2g). For further investigation, a device with an MoS2 top floating gate was fabricated (device III, Figure 2c). The ISD−VG transfer curves of device III exhibited large hysteresis, as for device II (Figure 2d). In addition, when 532 or 635 nm light pulses with a pulse width of 0.05 s were applied every 30 s, stepwise and wavelength-dependent increases in the ISD were observed (Figure 2h). To compare the optical memory properties between devices II and III, we measured the ISD at VSD = 0.1 V for devices II and III when 532 nm light pulses with P = 2 nW and different pulse widths (Δt) were applied every 30 s (Figure 2i). For both devices, the ISD increased more rapidly with the increase of Δt. However, device III exhibited a significantly faster increase of the ISD compared to device II. We performed similar measurements using the 635 nm laser and found similar behaviors (Figure S5a,b), indicating that the multilevel optical memory properties were dependent on the properties of the top floating gate. To estimate the retention time of the optical memory states, the ISD was continuously measured in the dark over time after the application of 50 light pulses with λ = 635 nm, a period of 30 s, and different Δt (Figure S5a,b). The ISD 25309

DOI: 10.1021/acsami.9b05491 ACS Appl. Mater. Interfaces 2019, 11, 25306−25312

Research Article

ACS Applied Materials & Interfaces

Figure 4. (a) ISD of device II measured at VSD = 0.1 V when light pulses (λ = 532 nm, P = 4 nW) with different exposure times were repeatedly applied for switching to the on state, followed by the application of gate voltage pulses of +40 V with a pulse width of 1 ms for switching to the off state. (b) ISD of device II measured at VSD = 0.1 V when light pulses (λ = 532 nm, Δt = 0.1 s) with different laser powers were repeatedly applied for switching to the on state, followed by the application of gate voltage pulses of +40 V with a pulse width of 1 ms for switching to the off state. (c) ISD of device III measured at VSD = 0.1 V when light pulses (λ = 532 nm, P = 1 nW) with different exposure times were repeatedly applied for switching to the on state, followed by the application of gate voltage pulses of +40 V with a pulse width of 1 ms for switching to the off state. (d) Plot of the increment of ISD (ΔISD) vs the light exposure dosage (P·Δt) based on the data obtained at λ = 532 and 635 nm for devices II and III. The data measured at λ = 635 nm are shown in Figure S6.

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CONCLUSIONS In summary, we demonstrated MoS2-based devices with a top floating gate of graphene or MoS2 as optoelectronic nonvolatile memory devices that are erased optically and read and programmed electrically. Unlike the conventional floating gate memory devices, our devices have the photosensitive floating gate at the top, functioning as the charge trapping layer. Stable and reliable switching with an on/off ratio of ∼106 and a retention time of >104 s was achieved via illumination with 405 nm light pulses and application of gate voltage pulses. However, when 532 or 635 nm light pulses were applied, multilevel optical memory effects were observed, which were dependent on the wavelength and the optical exposure dosage. These optical memory properties were explained according to the number of electrons transferred from the top floating gate to the MoS2 channel, because the electron tunneling barrier height from the floating gate to the MoS2 channel through hBN was lower than 3.06 eV and higher than 2.33 eV. In addition, the device with an MoS2 floating gate was more sensitive to light than the device with a graphene floating gate, indicating that the multilevel optical memory effects originated from photoexcited carriers in the top floating gate rather than in the channel layer. Compared with the conventional floating gate memory devices, our devices have the following advantages: it is easy to access the light source because of the structure of the top floating gate, and the multilevel optical memory states can be modulated by adjusting the top floating gate materials.

are dependent on the wavelength and the light exposure dosage, are understood in terms of the number of transferred electrons. Figure 3g−i illustrates the energy band diagrams of device III. The only difference from device II is the tunneling barrier height. For device III, the tunneling barrier height from the MoS2 floating gate to the MoS2 channel is approximately 2.4 eV, which is lower than that for device II. Thus, under the same optical exposure, more electrons are transferred from the MoS2 floating gate to the MoS2 channel than in device II, yielding a larger increase in ISD. Finally, to demonstrate the multilevel optical memory states, light pulses with different exposure times or laser powers were employed for the on state, and the gate voltage pulse of +40 V was applied for the off state (Figures 4a−c and S6). For devices II and III, distinct multilevels were achieved using light pulses with different exposure times and laser powers. In Figure 4d, the increment of ISD (ΔISD) is plotted as a function of P·Δt. ΔISD increased linearly with respect to P·Δt, and its slope was dependent on the wavelength, suggesting that the device with the photoresponsive top floating gate can be applied as a filter-free color image sensor. In addition, devices II and III exhibited different slopes. These results indicate that the multilevel optical memory states are possibly modulated by the top floating gate materials. 25310

DOI: 10.1021/acsami.9b05491 ACS Appl. Mater. Interfaces 2019, 11, 25306−25312

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ACS Applied Materials & Interfaces

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METHODS

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ASSOCIATED CONTENT

(2) Lee, G.-H.; Yu, Y.-J.; Cui, X.; Petrone, N.; Lee, C.-H.; Choi, M. S.; Lee, D.-Y.; Lee, C.; Yoo, W. J.; Watanabe, K.; Taniguchi, T.; Nuckolls, C.; Kim, P.; Hone, J. Flexible and Transparent MoS2 FieldEffect Transistors on Hexagonal Boron Nitride-Graphene Heterostructures. ACS Nano 2013, 7, 7931−7936. (3) Lee, G.-H.; Cui, X.; Kim, Y. D.; Arefe, G.; Zhang, X.; Lee, C.-H.; Ye, F.; Watanabe, K.; Taniguchi, T.; Kim, P.; Hone, J. Highly Stable, Dual-Gated MoS2 Transistors Encapsulated by Hexagonal Boron Nitride with Gate-Controllable Contact, Resistance, and Threshold Voltage. ACS Nano 2015, 9, 7019−7026. (4) Xia, F.; Wang, H.; Xiao, D.; Dubey, M.; Ramasubramaniam, A. Two-Dimensional Material Nanophotonics. Nat. Photonics 2014, 8, 899−907. (5) Britnell, L.; Ribeiro, R. M.; Eckmann, A.; Jalil, R.; Belle, B. D.; Mishchenko, A.; Kim, Y. J.; Gorbachev, R. V.; Georgiou, T.; Morozov, S. V.; Grigorenko, A. N.; Geim, A. K.; Casiraghi, C.; Neto, A. H. C.; Novoselov, K. S. Strong Light-Matter Interactions in Heterostructures of Atomically Thin Films. Science 2013, 340, 1311−1314. (6) Geim, A. K.; Grigorieva, I. V. Van der Waals Heterostructures. Nature 2013, 499, 419−425. (7) Roy, K.; Padmanabhan, M.; Goswami, S.; Sai, T. P.; Ramalingam, G.; Raghavan, S.; Ghosh, A. Graphene−MoS2 Hybrid Structures for Multifunctional Photoresponsive Memory Devices. Nat. Nanotechnol. 2013, 8, 826−830. (8) Lee, J.; Pak, S.; Lee, Y.-W.; Cho, Y.; Hong, J.; Giraud, P.; Shin, H. S.; Morris, S. M.; Sohn, J. I.; Cha, S.; Kim, J. M. Monolayer Optical Memory Cells Based on Artificial Trap-Mediated Charge Storage and Release. Nat. Commun. 2017, 8, 14734. (9) Lei, S.; Wen, F.; Li, B.; Wang, Q.; Huang, Y.; Gong, Y.; He, Y.; Dong, P.; Bellah, J.; George, A.; Ge, L.; Lou, J.; Halas, N. J.; Vajtai, R.; Ajayan, P. M. Optoelectronic Memory using Two-Dimensional Materials. Nano Lett. 2014, 15, 259−265. (10) Xiang, D.; Liu, T.; Xu, J.; Tan, J. Y.; Hu, Z.; Lei, B.; Zheng, Y.; Wu, J.; Neto, A. H. C.; Liu, L.; Chen, W. Two-Dimensional Multibit Optoelectronic Memory with Broadband Spectrum Distinction. Nat. Commun. 2018, 9, 2966. (11) Lee, D.; Hwang, E.; Lee, Y.; Choi, Y.; Kim, J. S.; Lee, S.; Cho, J. H. Multibit MoS2 Photoelectronic Memory with Ultrahigh Sensitivity. Adv. Mater. 2016, 28, 9196−9202. (12) Tran, M. D.; Kim, H.; Kim, J. S.; Doan, M. H.; Chau, T. K.; Vu, Q. A.; Kim, J.-H.; Lee, Y. H. Two-Terminal Multibit Optical Memory via van der Waals Heterostructure. Adv. Mater. 2019, 31, 1807075. (13) Wang, Q.; Wen, Y.; Cai, K.; Cheng, R.; Yin, L.; Zhang, Y.; Li, J.; Wang, Z.; Wang, F.; Wang, F.; Shifa, T. A.; Jiang, C.; Yang, H.; He, J. Nonvolatile Infrared Memory in MoS2/PbS van der Waals Heterostructures. Sci. Adv. 2018, 4, No. eaap7916. (14) Chen, J.-Y.; Chiu, Y.-C.; Li, Y.-T.; Chueh, C.-C.; Chen, W.-C. Nonvolatile Perovskite-Based Photomemory with a Multilevel Memory Behavior. Adv. Mater. 2017, 29, 1702217. (15) Tan, H.; Liu, G.; Zhu, X.; Yang, H.; Chen, B.; Chen, X.; Shang, J.; Lu, W. D.; Wu, Y.; Li, R.-W. An Optoelectronic Resistive Switching Memory with Integrated Demodulating and Arithmetic Functions. Adv. Mater. 2015, 27, 2797−2803. (16) Kim, Y. L.; Jung, H. Y.; Park, S.; Li, B.; Liu, F.; Hao, J.; Kwon, Y.-K.; Jung, Y. J.; Kar, S. Voltage-Switchable Photocurrents in SingleWalled Carbon Nanotube-Silicon Junctions for Analog and Digital Optoelectronics. Nat. Photonics 2014, 8, 239−243. (17) Lee, M.; Lee, W.; Choi, S.; Jo, J.-W.; Kim, J.; Park, S. K.; Kim, Y.-H. Brain-Inspired Photonic Neuromorphic Devices using Photodynamic Amorphous Oxide Semiconductors and their Persistent Photoconductivity. Adv. Mater. 2017, 29, 1700951. (18) Liu, T.; Xiang, D.; Zheng, Y.; Wang, Y.; Wang, X.; Wang, L.; He, J.; Liu, L.; Chen, W. Nonvolatile and Programmable Photodoping in MoTe2 for Photoresist-Free Complementary Electronic Devices. Adv. Mater. 2018, 30, 1804470. (19) Wang, Y.; Liu, E.; Gao, A.; Cao, T.; Long, M.; Pan, C.; Zhang, L.; Zeng, J.; Wang, C.; Hu, W.; et al. Negative Photoconductance in van Der Waals Heterostructure-Based Floating Gate Phototransistor. ACS Nano 2018, 12, 9513−9520.

Device Fabrication. MoS2-based devices with top floating gates of Au, graphene, and MoS2 were fabricated, as shown in Figure S7. First, hBN flakes (15−21 nm) were mechanically exfoliated from an hBN single crystal (HQ graphene) using tape, and a selected hBN flake was transferred onto an SiO2 /Si substrate using the polydimethylsiloxane (PDMS) stamping method.2,30 Subsequently, a channel MoS2 flake (5−15 nm) exfoliated from an MoS2 single crystal (SPI Supplies) was stacked on the hBN layer using the PDMS stamping method, and Cr (5 nm)/Au (50 nm) electrodes were fabricated using electron-beam lithography and lift-off techniques. Prior to further processing, the fabricated MoS2 FET device was characterized by measuring the ISD−VG transfer curves to check the MoS2 channel. After that, another hBN flake (5−17 nm) was transferred onto the MoS2 channel layer, and an Au floating gate (30 nm) was patterned on the hBN layer using electron-beam lithography and lift-off techniques for the device with the Au top floating gate (device I). On the other hand, for the devices with graphene (device II) and MoS2 (device III), mechanically exfoliated graphene (3−10 nm) and MoS2 (15 nm) were transferred onto the hBN layer using the PDMS stamping method, respectively. The thickness of each layer for devices I, II, and III is summarized in Table S1. Measurements. Atomic force microscopy (AFM) and EFM images were acquired using an atomic force microscope (Park NX10, Park Systems) with a Cr−Au conducting cantilever (NSC36). To characterize the optoelectronic properties, the devices were placed in a homemade vacuum chamber with an optical window. Electrical measurements were carried out using a semiconductor characterizer (4200-SCS, Keithley) and light was illuminated through the optical window. The light exposure time was controlled using an optical shutter (SB5/M Aperture and SC10 controller, Thorlabs).

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.9b05491.

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Endurance performance of devices I and II; AFM image of device I; 635 nm real-time illumination test of device II; different read-currents after different illumination time; switching test with different illumination time; device fabrication procedures; and table of each layer’s thickness of the devices (PDF)

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. ORCID

Sung Hyun Kim: 0000-0001-5408-7920 Kyung-Hwa Yoo: 0000-0001-9186-3095 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work has been financially supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (grant no. 2016R1A2B3011980).

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REFERENCES

(1) Wang, Q. H.; Kalantar-Zadeh, K.; Kis, A.; Coleman, J. N.; Strano, M. S. Electronics and Optoelectronics of Two-Dimensional Transition Metal Dichalcogenides. Nat. Nanotechnol. 2012, 7, 699− 712. 25311

DOI: 10.1021/acsami.9b05491 ACS Appl. Mater. Interfaces 2019, 11, 25306−25312

Research Article

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DOI: 10.1021/acsami.9b05491 ACS Appl. Mater. Interfaces 2019, 11, 25306−25312