Observation of Single Electron Transport via Multiple Quantum States

Letter pubs.acs.org/NanoLett

Observation of Single Electron Transport via Multiple Quantum States of a Silicon Quantum Dot at Room Temperature Sejoon Lee,*,† Youngmin Lee,† Emil B. Song,‡ and Toshiro Hiramoto§ †

Department of Semiconductor Science, Dongguk UniversitySeoul, Seoul 100-715, Korea Electrical Engineering Department, University of California, Los Angeles, California 90095, United States § Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan ‡

S Supporting Information *

ABSTRACT: Single electron transport through multiple quantum levels is realized in a Si quantum-dot device at room-temperature conditions. The energy spacing of more than triple the omnipresent thermal energy is obtained from an extremely small ellipsoidal Si quantum dot, and high charge stability is attained through a construction of the gate-allaround structure. These properties may move us a step closer to practical applications of quantum devices at elevated temperatures. An in-depth analysis on the transport behavior and quantum structure is presented. KEYWORDS: Silicon, quantum dot, large quantum-level spacings, room temperature

R

must be able to observe a reliable behavior of electron transport via the quantum states of the QD. Two fundamental conditions should be concurrently satisfied to practically exploit the quantum states of a semiconductor QD at room temperature environment. First, the physical size of the QD must be sufficiently small enough to ensure both a charging energy and a quantum level spacing greater than the ubiquitous thermal energy of 26 meV. Next, a deliberate and steadfast capacitor-structure must be devised to control the quantum states of the constituent charges. The former will provide stability, while the latter will allow controllability. Only recently, due to the difficulty in reducing parasitic effects, Shin et al.18 have reported on the room-temperature charge stability of a Si nanoisland from a miniaturized Si fin-FET structure. Here we report on the observation of multiple large quantum-level spacing with extreme charge stability in a Si SET at room-temperature conditions. The quantum structure of the Si QD is analyzed by examining the single-electron transport properties of the Si QD SET with a gate-all-around (GAA) structure. Figure 1a schematically illustrates the three-dimensional structure of the Si QD SET. The device is fabricated from a Si nanowire-channel metal−oxide−semiconductor field-effect transistor (MOSFET), where the Si QD and the tunnel barriers are self-formed by a volumetric undulation process.19−23 First, a [110] Si nanowire (w ∼ 40 nm, l ∼ 200 nm) is patterned on a semi-insulating (100) silicon-on-insulator

ecent advances in nanoscale fabrication technologies have created ample opportunities to realize sub 10 nm size quantum devices.1,2 Among these modules, a single electron transistor, where the electrons transport one by one through a quantum dot (QD), has garnered great attention because of its potential for high-speed, low-power, and qubit applications.3−6 Particularly, for its compatibility with silicon process technology, silicon (Si) single electron transistors (SETs) have been considered as a viable candidate to overcome current limits in complementary metal−oxide−semiconductor (CMOS) electronics.7,8 As scaling continues to reduce power, increase performance, and cut cost, CMOS devices inevitably suffer from large leakage currents induced by quantum tunnelling. This could be detrimental beyond the 10 nm node, which is mainly the realm of quantum mechanics. Rather than opposing such quantum effects, an approach to exploit the natural trend may be sensible. Lately, several interesting concepts such as the ratchet effect, turnstile effect, stochastic data process, and so forth, have been proposed to utilize the macroscopic features of Si QD SETs.9−17 However, the underlying mechanisms are solely based on the capacitive charging energy (i.e., classical Coulomb blockade effect), which is dictated by the extrinsic property of the QD and not the electronic quantum states of the QD itself. By employing the quantum states, device operation at elevated temperatures becomes easier and may further increase the chance to realize quantum computation. Admittedly, there are many hills to climb (e.g., thermal fluctuation, energy perturbation, and quantum decoherence, etc.); nonetheless, the ability to manipulate distinguishable quantum states at room temperature may serve as a basis. For this, charge stability at elevated temperatures is imperative. In other words, one © 2013 American Chemical Society

Received: August 27, 2013 Revised: November 25, 2013 Published: November 29, 2013 71

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level spacings (Δε > 75 meV) than the thermal energy (Eth ≈ 26 meV) at room temperature. Furthermore, the GAA stack renders a large gate capacitance (CG), while the self-assembled tunnel barriers create the relatively small source and drain capacitances (i.e., CS and CD). Thus, the CG would be greater than both the CD and the CS and result in a gate modulation factor (aG = CG/Cdot, where Cdot = CG + CD + CS) greater than unity (i.e., aG > 1).24 The large aG is highly favorable to reduce any thermally activated conduction mechanisms, which reduces charge stability in a single-electron tunneling device. First, we show the room-temperature Coulomb-blockade characteristics of the device. The SET clearly reveals multiple Coulomb-blockade oscillation (CBO) peaks at room-temperature in the drain current vs gate voltage (ID−VG) characteristic curves (Figure 2a). The CB1, CB2, CB3, and CB4 denoted at

Figure 1. (a) Schematic configuration of the fabricated Si SET. (b) Scanning electron microscopy image of the Si nanowire after chemical wet-etching. (c) Cross-sectional transmission electron microscopy image of the Si nanowire after fabricating the GAA structure. (d) Expected potential profile in the conduction band along the Si nanowire.

substrate (p ∼1015 cm−3) by using electron-beam lithography and helicon dry-etching. Through isotropic wet-etching (NH4OH/H2O2/H2O), the size of the Si nanowire is reduced to less than 10 nm (Figure 1b). Next, the buried oxide underneath the nanowire channel is intentionally removed by HF to suspend the nanowire channel from the buried oxide. At this point, the large source and drain are supporting the suspended nanowire−channel beam. Subsequently, the nanowire is thermally oxidized to partially form the gate oxide (i.e., the nanowire channel is still suspended). As a result, the Si nanowire is squeezed from all directions, and the size is further reduced to 140 meV) and quantum

Figure 2. (a) ID−VG characteristic curves of the fabricated SET at 300 K. The blue and red lines correspond to the logarithmic and linear scales, respectively. (b) ID−VG characteristic curves of the fabricated SET at T = 150−300 K.

each valley of CBO represent the dominant Coulomb-blockade states. An important feature is the nonperiodic intervals between CBO peaks. If the CBO intervals are periodic, the transport through the QD is governed by the charging energy. A nonperiodic interval, however, indicates that the electron transport is mediated through the discrete quantum states of a Si QD because the Coulomb gap in a semiconductor QD SET accompanies not only a constant charging energy but also an inconstant quantum level spacing of the QD. This is only true if the system is a single dot and not a multidot. 72

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Figure 3. Characteristics of IValley for CB1 and CB2 states at various temperatures: (a) T = 300 K, (b) T = 250 K, (c) T = 200 K, and (d) T = 150 K.

Figure 4. (a) Contour plot of ID as functions of VG and VD at 300 K. (b) Contour plot of ID as functions of VG and VD at 200 K. (c) Contour plot of dID/dVD as functions of VG and VD at 300 K. (d) Contour plot of dID/dVD as functions of VG and VD at 200 K.

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Figure 5. ID−VD characteristic curves at 300 K near Coulomb blockade points indicated in Figure 3a: (a) VG1 ∼ 0.68 V, (b) VG2 ∼ 0.88 V, (c) VG3 ∼ 1.48 V, (d) VG4 ∼ 1.52 V, (e) VG5 ∼ 2.08 V, (e) VG6 ∼ 2.12 V. The inset in each graph shows the dID/dVD−VD curve at 300 K.

The existence of a single dot can be confirmed by measuring the temperature dependence of the CBO characteristics. If the SET is composed of a single dot system, no additional satellite peaks would appear unless the Γ-valley state splits from the 2fold and/or 4-fold degeneracy and contributes to the carrier transport near cryogenic temperatures.18 Conversely, in a multidot system, a peak separation would occur at decreased temperatures because the stochastic tunneling conditions would eventually be broken.25 In Figure 2b, the temperaturedependent CBO characteristics are shown. As the temperature cools down to 150 K, the CBO peaks clearly remain singular. Only the peak width becomes sharper from the reduction of the thermal broadening in the carrier distribution function and the peak position shifts in parallel toward the negative VG direction due to a reduction in the Fermi potential. This corroborates that our device consists of a single dot. Therefore, each CB

state can be assigned to a charge state (i.e., electron occupancy N) of a single QD. Next, we characterize the stability of each charge state by measuring the valley current (IValley) at each Coulomb-blockade state. The external electric field of the source−drain bias provides excess energy through cotunneling events, which is manifested in the valley current.21,26,27 As shown in Figure 3a− d, the valley current (IValley) at CB1 and CB2 states increases with the drain voltage (VD). The relationship between the drain voltage and the valley current can be derived by IValley = AGSGD[(eVDS)2 + (2πkBTeff)2]VDS,21,27 where A is the proportional factor, GS and GD are the source and drain conductance, kB is the Boltzmann constant, and Teff is the effective electron temperature relevant to excess energies. By fitting IValley with the above equation, the effective electron temperature Teff at each Coulomb-blockade state is nearly identical to the environ74

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Figure 6. (a) Contour plot of ID as functions of VG and VD at 100 K. (b) Contour plot of dID/dVD as functions of VG and VD at 100 K. (c) VGdependent channel conductance G at 100 K. (d) Contour plot of dID/dVD as functions of VG and VD at 50 K.

condition28−34 that appears as an elongated Coulomb-blockade diagram.22,23 In other words, when the dot is coupled with two different capacitors (e.g., CG ≠ CD (≈ CS)), the electrostatic energy conditions for Coulomb blockade changes from the original Coulomb-blockade region toward the elongated blockade region. This is because the energy difference from VD (or VG) can be compensated by changing VG (or VD). As shown in the contour plot of the differential drain conductance dID/dVD (Figure 4c), all of the Coulomb-blockade regions are extended toward higher ±VD regions. Furthermore, at 200 K (Figure 4d), the extension of the Coulomb-blockade regimes becomes clearer because of reduced thermal-broadening effects at low temperature. The extremely long and parallel extensions of multiple CB regions (A and −A) make it easier to observe carrier transport through discrete quantum states. Since the change of VD accomplishes both on- and off-resonance statuses for the Nth quantum levels,8,35 the gradual conversion from the Nth to the N + 1th (or N − 1th → Nth) charge states can be traced from the ID−VD (or dID/dVD−VD) curves at specific VG points (see Supporting Information). For example, the magnitude of dID/ dVD repeatedly varies upon increasing VD at fixed VG points (Figure 4c and d). In other words, as |VD| increases, the contrast of dID/dVD changes from “blue (low) → red (high) → blue/green (low) → red (high)”. To trace the variations of VD-dependent ID and dID/dVD, we measured ID−VD and dID/dVD−VD curves at various VG points. When VG is fixed at specific bias points (e.g., VG1, VG2, VG3, VG4, VG5, and VG6 in Figure 4c), the device exhibits the Coulombstaircase phenomena (Figure 5a−f). The trajectories in the IDretarded regions can be clearly distinguished from the dID/

mental temperature Tenv. The small discrepancy between Teff and Tenv ( CD) facilitates the independent control of either the Fermi potential by VD or the dot potential by VG.22,23 This eventually allows the extension of the Coulomb-blockade regime toward high ±VD regions. In this case, the gate voltage and drain bias induce an imbalance in the Coulomb energies and renormalizes the Coulomb blockade 75

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dVD−VD curves, which display oscillation features near the Coulomb-staircase regions (see each inset of Figure 5a−f). The inflection point (i.e., peak or hump) corresponds to the resonance state where the Fermi level of the source (or drain) aligns with the discrete quantum state (see the Supporting Information). Therefore, we can quantitatively analyze the charge states and the quantum structures of the dot. The oneelectron-addition energy Ea (= EC + Δε) is given by Ea = (CG/ CDot)ΔVG,20−23 where ΔVG is the Coulomb gap. Using the intervals of CBO peaks and the capacitance ratio calculated above, we extracted the values of Ea for CB1, CB2, and CB3 states to be 253 meV, 214 meV, and 222 meV, respectively (see also Figure 7a). Similarly, the magnitude of quantum level spacing can be determined from the relationship of Δε = (CD/ CDot)ΔVD,20−23 where ΔVD is the source−drain gap. From the values of ΔVD in dID/dVD−VD curves, the quantum level spacing of Δε1,0, Δε2,1, and Δε3,2 are estimated to be ∼115, ∼76, and ∼81 meV, respectively (see also Figure 7a). The appearance of such a feature at room temperature can only be observable when both EC and Δε are much greater than the thermal energy Eth at 300 K (≈ 25.9 meV). To verify this, by using EC = Ea − Δε,20−23 we estimated EC for the QD in our device. The average value of EC is ∼140 meV. Therefore, the observation of multiple quantum level spacings at room temperature is attributed for both large EC (i.e., 5.4 times greater than 25.9 meV) and Δε (i.e., 3−4 times greater than 25.9 meV). One may think the magnitude of the quantum level spacing is too large. This is true if we consider the QD to be spherical (i.e., Δε < 50 meV for spherical Si QDs).36−38 However, the physical dot in our SET is part of a [110] Si nanowire (i.e., ellipsoidal QD) formed by volumetric undulation. In an ultranarrow [110] Si nanowire (dNW < 5 nm), the magnitudes of Δε can become as large as 60−200 meV.39,40 As the crosssectional size decreases, the effective mass at the 2-fold Γ valley becomes lighter (i.e., mmin ∼ 0.11m0).39 Since the lighter effective mass creates the greater magnitudes of discrete quantum level spacings, a large value of Δε (>75 meV) is achievable. Consequentially, we can ascribe the appearance of multiple large Δε at 300 K to the formation of an ellipsoidal [110] Si QD. To further eliminate any other dubious possibilities of the origin (e.g., charge-trap and pinch-off, etc.), we examined the Coulomb-blockade characteristics at even lower temperatures. At 100 K, the Coulomb diamonds (Figure 6a) and their extended blockade regions (Figure 6b) come to be clearer than those at 200−300 K (Figure 4c and d). Furthermore, it is apparent that, regardless of VD, the dot is completely emptied out of electrons at the subthreshold and blockade regions, where the source and drain are far from pinch off (Figure 6c). When the temperature is further cooled down to 50 K, the split bands and fine structures start to appear (Figure 6d). All in all, the evidence strongly suggests that the multiple CBO features arise from the discrete quantum states of the Si QD. Upon the results, we conjecture that the multiple CBO peaks at room temperature originate from the physical nature of multiple large-quantum-level spacings in a small [110]-oriented ellipsoidal Si single QD (Figure 7a). From the perspective of device engineering, however, high gate-controllability should be also accompanied to effectively attain charge stability for the Coulomb-blockade states. To further ratify this assertion, we simulate the Coulomb-blockade characteristics of an SET by using the extracted experimental parameters. For the

Figure 7. (a) Calculated energy levels of the Nth electron states for the Si QD in the fabricated SET. (b) Simulated Coulomb diagram for the SET consisting of an ultrasmall Si QD (ddot ∼ 5.3 nm) with three quantum states (Δε1,0 = 115 meV, Δε2,1 = 76 meV, and Δε3,2 = 81 meV). The tunnel barrier is fixed at 1500 meV, and CG, CD, and CS are assumed to be 0.55, 0.24, and 0.32 aF, respectively.

simulation, we adopt a theoretical SET model, where both the capacitive charge-control and the energetic dynamics of single-electron tunneling had been formulated on the basis of the steady-state master equation and the orthodox theory (see Supporting Information for calculation details).41,42 The result clearly depicts three Coulomb-blockade regions (Figure 7b) that resembles the observed Coulomb-blockade characteristics of our device (i.e., Coulomb diagram of the fabricated device in Figure 4a). Consequently, the theoretical simulation validates the aforementioned hypothesis that the multiple CBO characteristics at room temperature are ascribed to the multiple large quantum-level spacings of an ultrasmall ellipsoidal Si single QD with large gate coupling. In conclusion, the Si SET comprising an ultrasmall ellipsoidal [110] Si single QD reveals multiple CBO peaks at room temperature. The GAA gate stack (i.e., large voltage gain, CG/ CD = 2.26) generates an elongated CB region that provides an easy method to trace the single electron transport from Nth to N + 1th (or from N − 1th to Nth). Furthermore, both experimental and theoretical results showed single electron 76

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transport via the quantum states of the QD, whose energy spacings are at least 3 times greater than the thermal energy (i.e., Δε ≫ 26 meV). This may be beneficial when in search of a feasible solution to extend Si electronics beyond sub 10 nm node.

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ASSOCIATED CONTENT

S Supporting Information *

Statistical data for various SETs showing multiple Coulomb blockade regions at room temperature, mechanisms for VDSdependent electron transport through multiple quantum states, and description on the numerical model of a single electron transistor. This material is available free of charge via the Internet at http://pubs.acs.org.

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Tel.: +82-2-2260-3946. Fax: +82-2-2260-3945. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This research was supported by the National Research Foundation of Korea through the Basic Science Research Program (NRF-2010-0023085, FY: 2010-2012), the Leading Foreign Research Institute Recruitment Program (NRF-2013044975), and the Brain Korea 21+ Program (22A20130000037) funded by the Korean government of Ministry of Education (MoE).

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