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Oxide-based Synaptic Transistors Gated by Sol−Gel Silica Electrolytes Feng Shao, Yi Yang, Li Qiang Zhu, Ping Feng, and Qing Wan* School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China ABSTRACT: Low-temperature sol−gel processed silica electrolyte films showed a high specific capacitance of 3.0 μF/cm2 due to the electric-double-layer (EDL) effect. Oxide-based transistors gated by such silica electrolyte films show a high on/off ratio (>107) and a very low operation voltage (1.0 μF/cm2) that can induce very high charge carrier density (>1014 cm−2) in the channel layer.18,19 The ion-related electrostatic and electrochemical modulation processes is similar to the ionic regulation processes in the nervous system, © 2016 American Chemical Society
making EDL transistors ideal candidates for synapse emulation. In addition, the long-range coupling ability of electrolyte film also enabled the application of multiple in-plane gate configuration for EDL transistors.20,21 Sol−gel processed silica films have found a wide range of applications,22,23 but for metal-oxide-semiconductor field effect transistor (MOSFET) fabrication, the gate dielectric films were mainly dominated by thermally grown SiO2 and high-k dielectrics.24,25 For traditional field-effect transistor application, ions in the gate dielectrics are regarded as the cause for hysteresis and instability.26−30 For example, in order to eliminate the influence of water absorption and electricdouble-layer effect, organic field-effect transistors gated by sol−gel silica films were fabricated and measured in vacuum.26 For new-concept EDL transistors gated by proton conducting electrolytes,31,32 charge modulation is accredited to the protons dissociated from surface hydroxyl groups by the applied electric field. Under a positive gate bias, protons will migrate to the electrolyte/channel interface through hopping between the surface oxygen and adsorbed water molecules, where they induce the accumulation of electrons in the semiconducting oxide channel layer.31−33 Yakuphanoglu28 also demonstrated that the low voltage operation of pentacene TFTs with sol−gel silica gate dielectric films was likely due to the moisture in the air ambient. But to the best of our knowledge, there is no report on the oxide-based EDL transistors gated by sol−gel processed silica electrolyte films for artificial synapse application. Received: October 24, 2015 Accepted: January 18, 2016 Published: January 18, 2016 3050
DOI: 10.1021/acsami.5b10195 ACS Appl. Mater. Interfaces 2016, 8, 3050−3055
Research Article
ACS Applied Materials & Interfaces
thickness.34 Smooth surface of the dielectric film is critical to obtain high carrier mobility by reducing the scattering of carriers at the channel/dielectric interface. The root-meansquare (rms) roughness of the sol−gel processed silica electrolyte film was estimated to be 0.27 nm by AFM measurement (Figure 2a). Leakage current measurements of
In this work, low-voltage indium−gallium-zinc-oxide (IGZO)-based EDL transistors gated by sol−gel processed silica electrolyte films were fabricated at low temperature on glass substrates. The silica electrolyte films showed a high specific capacitance of up to ∼3.0 μF/cm2. Short-term synaptic plasticity, such as paired pulse facilitation, was emulated. Spatial summation of neuron signals from two presynapse neurons was also emulated using two in-plane gates as the presynaptic inputs. At last, spiking and logic operation was successfully demonstrated because of the superlinearity spatial summation behavior of the synaptic transistor.
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EXPERIMENTAL SECTION
To prepare silica sol, we mixed TEOS (tetraethyl orthosilicate), ethanol, water and phosphoric acid (85 wt %) with a molar ratio of 1:18:4:0.02. The mixture was stirred in a sealed bottle at room temperature for 1.0 h and then placed in an oven at 60 °C for 2.0 h to accelerate the polymerization of Si−O−Si chains. ITO glass and silicon substrates were cleaned successively in DI water, acetone and ethanol by ultrasonication. The silica sol was deposited onto the ITO glass substrates by spin coating process at 3000 rpm for 30 s, followed by heating at 120 or 300 °C for 30 min to form the silica film. The coating and heating steps were repeated for a second layer. A schematic image of above process is shown in Figure 1. To fabricate Figure 2. (a) AFM image of the sol−gel processed silica film annealed at 120 °C. (b) Leakage current curves of the sol−gel silica films annealed at 120 and 300 °C and (inset) schematic image of measured IZO/silica/ITO structure. (c) Frequency dependent specific capacitance curves of the silica films annealed at 120 and 300 °C, respectively. (d) FTIR spectrum of the silica films annealed at 120 and 300 °C.
the silica films were performed by the IZO/silica/ITO sandwich structure, as shown in Figure 2b. Silica film annealed at 120 °C shows a relatively higher leakage current than that annealed at 300 °C. In the electric field range from −50 kV/cm to 50 kV/cm, the maximal leakage current of the silica film annealed at 120 °C is 4.0 μA/cm2, which can guarantee our device operated in a field-effect mode. Figure 2c shows the frequency dependent specific capacitance of the sol−gel silica films. For the silica film annealed at 120 °C, a high specific capacitance of ∼3.0 μF/cm2 is measured at 1.0 Hz. This value is comparable to the room temperature CVD deposited porous silica or alumina dielectrics,35,36 and is about 2 orders of magnitude larger than conventional thermal grown SiO2 film with a same thickness. The frequency-dependent capacitance curve is similar to that of electrolyte-based gate insulators, suggesting a strong contribution of mobile ions with slow polarization process.37−39 When the annealing temperature is 300 °C, the specific gate capacitance value of the silica electrolyte film at 1.0 Hz is estimated to be 0.88 μF/cm2, which is still much higher than the capacitance value of the thermal grown SiO2 film with a same thickness. The above results indicate that silica film annealed at 300 °C still provides sufficient mobile protons for EDL formation, and silica film processed at 300 °C should not be regarded as traditional SiO2 gate dielectric with a dielectric constant = 3.9. To shed some light on this issue, FTIR measurements were performed, and the absorbance curves are shown in Figure 2d. The main peak (1080 cm−1) with a shoulder centered around 1200 cm−1 and the peak at 800 cm−1 are belong to different vibration modes of the Si−O bonds.34 The broad peaks in the range of 2600−3700 cm−1 are generally known for the O−H bonds of hydroxyl
Figure 1. Schematic images of the sol−gel processes for silica electrolyte film preparation. IGZO-based EDL transistors with bottom gate and two in-plane gates, we deposited 30 nm thick IGZO channel layer (target In/Ga/Zn = 1:1:1, atomic ratio) on silica electrolyte films by radio frequency (RF) magnetron sputtering method at the pressure of 0.5 Pa with a RF power of 100 W. A shadow mask was used to pattern the area of IGZO channel layer. Conducting IZO source/drain (S/D) and in-plane gate electrodes (G1/G2) were deposited by RF sputtering method with a second metal mask. As shown in Figure 3a, the obtained IGZO channel layer has a width (W) of 1000 μm and a length (L) of 80 μm (W/L = 12.5). The distance between the S/D electrodes and the nearby in-plane gate electrode is 1000 μm. The thickness of the silica films were measured by profilometry and scanning electron microscope (Zeiss Auriga). Surface roughness of the silica films were examined by atomic force microscope (AFM, NT-MDT, NTEGRA). Fourier transform infrared spectroscopy (FTIR) was measured with Bruker VERTEX 80v in the transmission mode. Dielectric properties of the silica films were characterized by an impedance analyzer (Solartron 1260) with the IZO/silica/ITO sandwich structure. Electrical measurements were performed on a probe station connected to SMUs (Keithley 2612B and 2636B).
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RESULTS For both heating temperatures (120 or 300 °C), the thickness of the silica electrolyte films was estimated to be 400 ± 40 nm, which is in agreement with the result that the applied heating temperature do not cause significant difference in film 3051
DOI: 10.1021/acsami.5b10195 ACS Appl. Mater. Interfaces 2016, 8, 3050−3055
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Figure 3. (a) Schematic image of the IGZO-based EDL transistor gated by sol−gel processed silica film with one bottom gate electrode and two inplane gate electrodes. (b) Output curves of IGZO-based EDL transistor gated by the silica electrolyte film annealed at 120 °C. (c) Transfer curve of IGZO-based EDL transistor gated by silica electrolyte film annealed at 120 °C. (d) Transfer curve of IGZO-based EDL transistor gated by the silica electrolyte film annealed at 300 °C.
silica film showed a good stability. Figure 4a shows the repeated switch on and off operation of the IGZO-based EDL transistor gated by the silica electrolyte film annealed at 120 °C. A highcurrent on/off ratio of 107 and stable on and off currents can be maintained during the repeated switch on and off operation.
group and physically adsorbed water.40 When the annealing temperature is increased to 300 °C, this broad peak dropped significantly along with the H−O−H bending mode41 at 1650 cm−1 and the Si−OH peak at 950 cm−1. This is consistent with the above discussion that some degree of water and hydroxyl group are still presented after annealed at 300 °C. The electrical performance the IGZO-based EDL transistors gated by sol−gel processed silica electrolyte film was measured by applying gate voltage on the bottom ITO gate electrode. Figure 3b shows the output curve of the IGZO-based EDL transistor gated by the silica film annealed at 120 °C. It exhibit a well-defined linear relation at low VDS region and clear saturation at high VDS region, confirming the formation of Ohmic contacts between the IGZO channel layer and the IZO source/drain electrodes and field-effect electrostatic modulation operation. Figure 3c shows the transfer curve (VDS = 2.0 V) of the IGZO-based EDL transistors gated by the silica films annealed at 120 °C. A high on/off ratios of more than 107 was obtained in a small VG range. A counterclockwise hysteresis was also observed, which is mainly due to the slow relaxation of mobile protons in the silica electrolyte film. The saturation field-effect mobility μFE of the device gated by the silica films annealed at 120 °C was estimated to be 5.9 cm2/(V s). The subthreshold swing (SS) was estimated to be as low as 90 mV/ dec according to SS = ∂VG/∂(log IDS). As shown in Figure 3d, IGZO-based EDL transistors gated by the silica films annealed at 300 °C shows similar transfer curve (VDS = 2.0 V), which indicate that the amount of mobile protons in the 300 °C heated films is sufficient to induce a high charge carrier density in the channel. Silica electrolyte films deposited by sol−gel process have a nanoporous structure when they were annealed at temperature below 400 °C. Relatively large EDL capacitance can be observed when they were measured in the air ambient with a given humidity. Thermal treatment has some influence to the capacitance value of the silica film and the electrical performance of the transistor. Furthermore, our results also demonstrated that oxide-based EDL transistors gated by such
Figure 4. (a) Repeated switch on and off operation of the IGZO-based EDL transistor gated by silica electrolyte film annealed at 120 °C. (b) Ten times repeated measurement of the transfer curve of the IGZObased EDL transistor gated by silica electrolyte film annealed at 120 °C. 3052
DOI: 10.1021/acsami.5b10195 ACS Appl. Mater. Interfaces 2016, 8, 3050−3055
Research Article
ACS Applied Materials & Interfaces During the 10 day aging experiment in air ambient, the transfer curve of the device gated by the silica electrolyte film annealed at 120 °C was measured every day, as shown Figure 4b. Highly repeatable electrical performance was obtained, indicating the device is quite stable with low voltage cycling in air ambient. In neuroscience, synapse is the junction between the vastly interconnected networks of neurons. It allows the presynaptic neuron to transmit signals (action potential in the form of spikes) to a postsynaptic neuron with the ability of long-term or short-term change of its efficacy (synaptic weight). The change by the history of its activity could be either enhancement or depression. It is believed that such activity-dependent synaptic plasticity is in charge of memory and learning of our brain.42 A typical short-term synaptic plasticity that prevails in the time scale of tens to hundreds of milliseconds is paired pulse facilitation (PPF). It is a phenomenon when there are two successive presynaptic spikes, the postsynaptic potential (or current) triggered by the second spike is larger than the first one and the increment drops with longer spike time interval. Its origin is considered presynaptic and can be simply viewed as the accumulation of presynaptic Ca2+ concentration by the first spike leads to a greater release of neurotransmitter during the second one.43 IGZO-based EDL transistor gated by the silica electrolyte film annealed at 120 °C was used to emulate the synapse functions. For PPF emulation, bottom gate (G) is regarded as the presynaptic terminal, and IGZO channel is regarded as the postsynaptic terminal. Channel current IDS is used as the synaptic weight. As shown in Figure 5a, the first presynapse spike (VG = 1.0 V, 30 ms) triggers a peak of excitatory postsynaptic current (EPSC). Before it returns to the resting current completely, the second presynapse spike arrives with a time interval (Δt) of 40 ms, and the second EPSC peak is obviously larger than the first one. The ratio of EPSC amplitudes between the second spike A2 and the first spike A1 is defined as the PPF ratio. Figure 5b shows the PPF ratio as a function of spike interval Δt. The highest value obtained at Δt = 20 ms is estimated to be 2.5. It decreases gradually with increasing Δt and becomes only 1.05 at Δt = 500 ms. In some biological synapses, the facilitation can be further subdivided into a rapid phase and a slower phase. Accordingly, the obtained data can be fitted by the double exponential decay function: F = 1 + C1exp(− Δt/τ1) + C2exp(− Δt/τ2), where Δt is the pulse interval, C1 and C2 are the initial facilitation magnitudes of the respective phases, and τ1 and τ2 are the characteristic relaxation times of the respective phases. We obtain τ1 = 25 ms, τ2 = 177 ms. Such results are similar to those observed in biological synapses.43 The operation mechanism of PPF emulated in the IGZO-based EDL transistor is similar to the Ca2+/neurotransmitter quantity build-up in biology synapse. The protons that regulate the concentration of charge carriers in the IGZO channel will be in a relaxation process after the first spike. If the second stimulus arrives before all protons diffuse to their equilibrium state, more protons will aggregate at the silica electrolyte/IGZO channel interface. A shorter Δt means that more mobile protons will be accumulated. Spatial summation can also be emulated in the IGZO-based EDL transistor with two in-plane gates acting as presynapse 1 (G1) and presynapse 2 (G2). Figure 6a shows a schematic image of the spatial summation of two presynaptic inputs in biological neuron. By using a bottom ITO conductive layer, signals applied on the multiple in-plane gate electrodes can be
Figure 5. (a, top) A pair of temporally correlated presynaptic spikes (by the VG inputs); (bottom) the triggered IDS as EPSCs, A1 and A2 represent the amplitudes of the first and second EPSC, respectively. (a, inset) Schematic image of the biological synapse for PPF behavior demonstration. (b) Paired pulse facilitation (PPF) ratio (A2/A1) plotted against interspike interval Δt. It is fitted with the double exponential decay function: F = 1 + C1exp(− Δt/τ1) + C2exp(− Δt/ τ2), as given in the text.
coupled to the channel layer, and a model of two capacitors in series connection was proposed to address the gating mechanism.44,45 As shown in Figure 6b, the EPSC triggered by G1 or G2 separately with a gate pulse of 2.0 V for 20 ms is less than 3 nA due to the relative weak modulation of the inplane gates. When the G1 and G2 were triggered simultaneously, a much larger EPSC of 86 nA is measured. The spatial summation at this activation condition is therefore much larger than the arithmetic sum, exhibiting the superlinear summation character of the synaptic signals that is typically found in biology systems.46 Such superlinear summation results in a spiking and logic operation in one IGZO-based EDL transistor.
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CONCLUSIONS Silica electrolyte films prepared by low-temperature sol−gel process were found to possess a very high specific gate capacitance of ∼3.0 μF/cm2 due to the mobile proton-related EDL effect. IGZO-based EDL transistors with silica electrolyte films as the gate dielectrics were favorable for synaptic behavior emulation. Paired pulse facilitation and spiking and logic operation were successfully emulated. Low-temperature processed oxide-based EDL transistors gated by silica electrolyte films provide an interesting approach for synaptic behavior emulation, which may be interesting for brain-inspired neuromorphic systems. 3053
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Figure 6. (a) Schematic image of the spatial summation of two presynaptic inputs in a biological neuron. (b) EPSCs triggered by the presynaptic spikes of 2.0 V and 20 ms applied on two in-plane gate of G1 and G2. ESPCs were measured at VDS = 0.5 V.
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS This work was supported in part by the National Science Foundation for Distinguished Young Scholars of China (Grant No. 61425020), in part by the National Natural Science Foundation of China (11174300, 11474293), and in part by the Zhejiang Provincial Natural Science Fund (LR13F040001).
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