pân Crossed Nanojunctions from Electroless-Etched Si Nanowires

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p–n Crossed Nanojunctions from Electroless-Etched Si Nanowires Ming-Yen Lu, Sheng-Chieh Huang, Yen-Min Ruan, Yu-Ting Kuo, Hsiang-Chen Wang, and Ming-Pei Lu J. Phys. Chem. C, Just Accepted Manuscript • DOI: 10.1021/acs.jpcc.6b07729 • Publication Date (Web): 12 Sep 2016 Downloaded from http://pubs.acs.org on September 17, 2016

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The Journal of Physical Chemistry

p–n

Crossed

Nanojunctions

from

Electroless-Etched Si Nanowires Ming-Yen Lu†,*, Sheng-Chieh Huang‡, Yen-Min Ruan‡, Yu-Ting Kuo§, Hsiang-Chen Wang‡, and Ming-Pei Lu∥ †

Department of Materials Science and Engineering, National Tsing Hua University,

Hsinchu 300, Taiwan ‡

Graduate Institute of Opto-Mechatronics and §Department of Physics, National

Chung Cheng University, Min-Hsiung, Chia-Yi 62102, Taiwan ∥

National Nano Device Laboratories, National Applied Research Laboratories,

Hsinchu 300, Taiwan

*corresponding

author:

e-mail:

[email protected];

tel:

+886-3-5715131 # 33818

Abstract In this study electroless etching was used to prepare p- and n-Si nanowire (NW) arrays from Si wafers, with the lengths of the Si NW arrays varied by controlling the etching time. The etching rate was approximately 150 nm/min up to 300 min, but decreased notably, to 32 nm/min, thereafter. Transmission electron microscopy confirmed that the Si NWs were single-crystalline and aligned along the [001] direction. The dumbbell separation of 0.13 nm, observed using high-resolution high-angle

annular-dark

field

scanning

transmission

electron

microscopy,

corresponded to Si atom arrangements projected along the [1-10] zone axis. A statistical study revealed that the average carrier concentrations of the p- and n-Si NW

ACS Paragon Plus Environment


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devices were 1.15 × 1018 and 2.61 × 1017 cm–3, respectively, while the average carrier mobilities were 6.66 × 10–3 and 5.41 × 10–3 cm2 V–1 s–1, respectively. A subsequently prepared p–n Si NW crossed nanojunction exhibited rectifying behavior typical of a p–n junction. Thus, the preparation of Si NW arrays from Si wafers through electroless etching appears to be an inexpensive, low-temperature technique for the mass-production of various device architectures and applications.

Introduction The behavior and applications of nanomaterials have drawn much attention for decades, with their unique properties arising from quantum confinement effects on the nanoscale and large surface-to-volume ratios. While nanotechnology is a flourishing field, semiconductor manufacturing remains reliant mostly on silicon (Si)—one of the most promising materials for the preparation of nanomaterials. Indeed, Si nanostructures have potential applications in a diverse range of devices, including field-effect transistors,1-2 logic gates,3-4 solar cells,5-6 photodetectors,7-8 and biosensors9-11. Several growth strategies have been demonstrated for the synthesis of Si nanostructures.12-13 Morales et al. used laser ablation to prepare Si nanowires (NWs) through vapor–liquid–solid (VLS) growth,14 the most common mechanism for growing NWs at high temperature.8, 15-17 Moreover, supercritical fluid–liquid–solid (SFLS) growth has also been used to form Si NWs in solution.18-19 These synthetic methods require high-temperature, high-pressure environments and precise parametric control, potentially limiting the applicability of the Si NWs. Consequently, inexpensive, low-temperature, mass-production techniques will be needed for the large-scale preparation of Si NWs for device applications. Ping et al. suggested that electroless etching might be a suitable method; this top-down approach has provided


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large-scale Si NW arrays with the ability to control the dimensions and properties of the Si NWs.20-23 More importantly, all the fabrication steps can be performed in beakers in the lab under ambient atmosphere. Nevertheless, a systematic study of the electrical characteristics of the various types of Si NWs obtained using electroless etching has yet to appear. Herein, we report the preparation of p- and n-Si NW arrays using electroless etching, where the lengths of the NW arrays increased upon increasing the etching time. The carrier concentrations and mobilities extracted from the electrical characteristics of both p- and n-Si NW devices revealed that their performances were distributed within a narrow range. Moreover, we have also demonstrated the ability to prepare p–n crossed nanojunctions composed of p- and n-Si NWs.

Experimental Details Single-crystalline p- and n-Si NWs were obtained from p- and n-Si wafers using electroless etching, as described previously.11, 24 The doping concentrations of the n-type (P-doped) and p-type (B-doped) Si wafers used in this study were in ranges 4.4 × 1013–4.5 × 1015 Ω-cm and 1.3 × 1014–1.3 × 1016 Ω-cm, respectively. Prior to etching, 1 × 1 cm2 Si (100) samples were ultrasonicated in acetone and rinsed with DI water. The Si samples were then immersed into the etching solution (5 M HF and 20 mM AgNO3, 20 mL) for various periods of time at room temperature. The resulting Ag film formed on the Si NW arrays was etched away in an etchant of NH4OH and H2O2 (3:1); the samples were then rinsed with DI water and dried with N2 gas. The morphologies and crystal structures of the samples were characterized using scanning electron microscopy (SEM, Hitachi S4800-I) and scanning transmission electron microscopy (STEM, JEOL JEM ARM200F). Si NW field-effect transistors (FETs) were fabricated using e-beam lithography



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(EBL). First, the Si NWs were transferred onto a patterned 300-nm SiO2/p+-Si substrate; the SiO2 layer served as an insulating gate oxide layer on the p+-Si substrate. After defining the electrode patterns through EBL, the samples were rinsed in dilute HF solution (HF/H2O, 1:10) for 30 s to etch away the native oxide on the Si NW surface. Metal electrodes were then deposited using an e-beam evaporator;25 200-nm Ni and 200-nm Al were used to ensure ohmic contacts with the p- and n-Si NWs, respectively. The p-Si NW FETs were annealed at 500 °C in Ar for 2 min to improve the Ni–Si contacts. Electrical transport measurements of the Si NW devices were conducted at room temperature using a Keithley 2636B system. After fabrication of the p-Si NW device, the n-Si NWs were placed, using manipulators, onto the p-Si NW device; subsequent electrode deposition and lift-off processes resulted in the p- and n-Si crossed-junction device.

Results and discussion Single-crystalline Si NW arrays displaying various semiconductor characteristics have been obtained previously from corresponding Si wafers using electroless etching.26-27 The formation of Si NW arrays can be tuned using many factors, including the concentrations of the components of the etching solution, the reaction temperature, the sample size, and the etching time.27 In this present study we varied only the etching time, while maintaining fixed the concentrations of the components of the etching solution (5 M HF and 20 mM AgNO3), the reaction temperature (room temperature), and the substrate size (1 × 1 cm2). Figs. 1a–d and 1e–h present SEM images of the Si NW arrays etched from p- and n-Si (001) substrates, respectively, for 100, 200, 300, and 400 min; the lengths of the p-Si NW arrays were 22.5, 31.5, 45.5, and 48.7 µm, respectively, while those of n-Si NW arrays were 19.8, 32.4, 45.2, and 48.6 µm, respectively. The n- and p-Si substrates were commercial products having


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moderate P and B doping. Thus, regardless of the semiconductor characteristics of the Si sample, the lengths of the Si NW arrays increased upon increasing the reaction time, with similar etching rates for n- and p-Si. The effects of the doping type and doping level of the Si substrate on the etching rate of the Si substrate remain uncertain. Zhang et al. found that the p-type Si substrate had a lower etching rate than the n-type Si substrate,26 whereas Hwang et al. observed that the etching rates of the n- and p-Si substrate were almost identical in the same etching solution.28 To shed light on the formation of Si NW arrays, the galvanic displacement between Si and Ag+ ions must be taken into account. The etching process occurring near the precipitated Ag particles and the Si interface involves several cathode and anode reactions: At the cathode: Ag + e → Ag At the anode: Si + 2H O + 4h → SiO + 4H SiO + 6HF → H SiF + 2H O The overall reaction: Si + 4Ag + 6HF → 4 Ag + H SiF + 4H

The reduction of Ag particles (cathodic reaction) and oxidation of Si (anodic reaction) comprised the electrochemical reaction. Initially, the formation of Ag particles and SiO2 occurred at the Si surface; in the meantime, the SiO2 was etched away by HF and Si emerged into the solution; this reaction occurred repetitively. The etching of Si proceeded along the vertical direction of the Si substrate—in this case, its [100] direction. Fig. 1i displays plots of the lengths of both types of Si NW arrays with respect to the etching time; as mentioned above, the n- and p-Si substrates had similar etching rates: approximately 150 nm/min up to 300 min, but decreasing notably, to 32



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nm/min, thereafter. These decreases in etching rates arose mainly from the consumption of Ag+ ions and HF in the solution as the etching time increased. The crystal structure of the as-formed p-Si NWs was analyzed using TEM. Fig. 2a displays a low-magnification TEM image of a Si NW etched from a Si substrate; it has a uniform diameter of 140 nm. The selective area electron diffraction (SAED) pattern from the [1-10] zone axis of Si in Fig. 2b indicates that the Si NW was single-crystalline with its axis along the [100] direction, consistent with our discussion above. Fig. 2c presents a high-resolution (HR) TEM image of the Si NW, revealing lattice spacings of 0.27 and 0.31 nm corresponding to the (002) and (111) planes, respectively, of Si. Structural analysis using aberration-corrected STEM (Cs-STEM) has become a novel technique for visualizing the atomic arrangements of materials.29-30 Fig. 2d presents the high-angle-annular dark field (HAADF) STEM HR image of a Si NW projecting along the [1-10] zone axis. Typical Si dumbbell arrays are evident in this image. The inset to Fig. 2d displays the intensity profile of the Si dumbbell structure; as the red arrow in Fig. 2d indicates, the separation was approximately 0.13 nm, corresponding to a Si dumbbell structure.31 Both n- and p-Si single-NW field-effect transistors (FETs) were fabricated on a 300-nm SiO2/p+-Si substrate using e-beam lithography and lift-off processes; Al and Ni were deposited as metal electrodes, using an e-beam evaporator, for the n- and p-Si NW FETs, respectively. Fig. 3a displays a schematic representation of the structure of the Si NW FETs; the 300-nm SiO2/ p+-Si substrate was used as the back-gate for electrical characterization. The inset to Fig. 3a presents an SEM image of a typical Si NW FET. We compared the electrical characteristics of the p-Si NW FET before and after annealing. The drain current–drain voltage (Id–Vd) curves in Fig. 3b reveal that the conductivity of the device increased substantially, by approximately two orders of magnitude, after annealing. It is known that Ni can diffuse into Si to form Ni silicide


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after annealing at temperatures above 400 °C; Ni silicide is a metallic material that can decrease the contact resistance between Ni and Si.23, 32 In this study, annealing of the Ni-contacted p-Si NW devices was performed at 500 °C for 2 min in an Ar ambient, suggesting that Ni silicide should have formed at the Ni–Si NW interface and, consequently, the conductivity of the device should have increased. Fig. 3c presents the Id–Vd data measured at various gate voltages (Vg); the currents decreased upon increasing the value of Vg from –5 to +5 V, displaying the well-defined gating effect of a p-type semiconductor. In addition, the sweeping transfer characteristics (Id– Vg curve, Fig. 3d) on the logarithmic scale with the applied value of Vd of 5 V reveals that the p-Si NW FET had an on/off ratio of 104 and a threshold voltage of 2.5 V. A positive threshold voltage for p-Si NW FETs implies that the devices can be regarded as depletion-mode FETs.33 We also characterized the electrical behavior of the devices fabricated from the n-Si NWs. A previous study suggested that the electrical characteristics of Al-contacted Si can be improved after annealing because of the diffusion of Si into Al;34 in this study, however, we found that the electrical properties of the n-Si NW devices changed negligibly after annealing (data not shown). It is possible that contamination or aluminum oxide formed between the Al electrodes and Si NW during the metal deposition and inhibited the diffusion of Si, leading to the electrical characteristics of the devices not improving accordingly after annealing. Therefore, we measured the electrical properties of the as-fabricated n-Si NW devices. Fig. 3e reveals that the Id–Vd curve of the n-Si NW devices features an approximately linear relationship. The Id–Vd curves recorded at different gate voltages (Vg) in Fig. 3f reveal that the current of the device increased upon increasing the value of Vg—typical device characteristics of an n-type semiconductor. In addition, we performed a statistical study of the electrical characteristics of the p- and n-Si NW devices. The mobility (µ) and carrier concentration (n) are crucial



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factors for gauging the performance of devices and the doping levels of the semiconductors. The values of µ and n of devices can be extracted from the transfer characteristics of a number of devices; they are defined as35 μ= n=

ℎ

!"( )

(1) (2)

where the transconductance (gm) is the slope (dId/dVg) of the linear regime in the transfer characteristics of devices; L, Vd, Vth, and Cox are the channel length, applied drain voltage, threshold voltage, and capacitance of the dielectric oxide, respectively. To simplify the calculation, we assumed that the Si NWs had cylindrical structures; therefore, we used the cylinder-on-plate model to calculate the capacitance:36 %&' =

"( () *+,-./(

01 ) 0

(3)

where εox is the relative dielectric constant; ε0 is the dielectric constant in free space (8.85 × 10–14 F cm–1); r is the radius of the NW; and tox is the thickness of the dielectric oxide. The mobilities and carrier concentrations determined from a number of p- and n-Si NW devices are plotted with respect to the NW diameter in Figs. 4a and 4b, respectively. The mobilities and carrier concentrations of the p-Si NW devices ranged from 4 × 10–4 to 1.8 × 10–2 cm2 V–1 s–1 and from 4.5 × 1016 to 5 × 1018 cm–3, respectively; for the n-Si NW devices they were distributed between 4 × 10-4 and 1.5 × 10–2 cm2 V–1 s–1 and 1.2 × 1016 and 1 × 1018 cm–3, respectively. Notably, both the mobilities and carrier concentrations of the p- and n- Si NW devices were independent of the NW diameter. Motayed et al. found that the mobility of a GaN NW device increased upon increasing the NW diameter, due to enhanced surface scattering for small-diameter NWs.37 In contrast, Jie et al. and Choi et al. reported Si NW devices whose mobilities were less dependent on the diameter of the NWs.16, 38 Figs. 4c and 4d plot histograms of the statistical mobilities and carrier concentrations of our


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p- and n- Si NW devices, respectively. Notably, the Si NWs obtained from the Si wafers had uniform doping levels, suggesting that they would have identical device characteristics; in contrast, both the mobilities and carrier concentrations varied over wide ranges, possibly because of a contact issue between the metal and the Si NW. The average carrier concentrations of the p- and n-Si NWs were 1.15 × 1018 and 2.61 × 1017 cm–3, respectively; the average carrier mobilities were 6.66 × 10–3 and 5.41 × 10–3 cm2 V–1 s–1, respectively. We also prepared a p–n junction formed by crossed p–n Si NWs. Fig. 5a presents an SEM image of the p–n Si NW nanojunction. Using a manipulator, the p-Si NW was positioned onto the n-Si NW to form the point contact; a corresponding illustration is displayed in the inset to Fig. 5a. Ni and Al were deposited as contact electrodes for the p- and n-Si NW devices, respectively. To realize the electrical configurations of p-n Si NW crossed junctions, simulations were run using finite element method (FEM) software. Fig. 5b displays the carrier concentrations and electric field of the junction at equilibrium; the carrier concentrations of p- and n-Si were obtained from the average values calculated in the previous section. We assumed that the holes and electrons were entirely ionized during the simulation. Notably, the carrier concentrations of holes and electrons (hollow squares and hollow circle curves, respectively) from p- and n-Si decreased around the junction and then fully depleted (labeled Wp and Wn in Fig. 5b) toward the other side, leading to the depletion region (Wp + Wn). The curve of solid triangles represents the variation in electric field around the junction; the depletion width was approximately 85 nm. The I–V data of crossed junction are plotted in Fig. 5c; the I–V characteristics measured from the p–n Si nanojunction (electrodes 1 and 4) exhibited rectifying behavior, a typical feature of p– n semiconductor junctions. In contrast, the I–V measurements of the p-Si NW (electrodes 2 and 4) and n-Si NW (electrodes 1 and 3) devices displayed symmetric



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ohmic-like characteristics (inset to Fig. 5c). Notably, the p-n Si crossed nanojunction was formed without any treatment; if further annealing treatments were applied, the performance of the device might improve.

Conclusions We have used electroless etching to prepare p- and n-Si NW arrays from Si wafers. The lengths of these Si NW arrays were varied by controlling the etching time. The etching rate was approximately 150 nm min–1 for etching times up to 300 min, but decreased notably, to 32 nm min–1, thereafter as a result of consumption of Ag+ ions and HF from the solution. TEM analysis confirmed that the Si NWs were single-crystalline and that the NWs had formed along the [001] direction. The dumbbell separation of 0.13 nm observed in HAADF STEM HR images corresponds to Si atom arrangements projecting along the [1-10] zone axis. The p- and n-Si NW devices had average carrier concentrations of 1.15 × 1018 and 2.61 × 1017 cm–3, respectively, and average carrier mobilities of 6.66 × 10–3 and 5.41 × 10–3 cm2 V–1 s–1, respectively. Moreover, a p–n Si NW crossed nanojunction prepared from these NWs exhibited rectifying behavior typical of p–n junctions; its depletion width, determined from simulation data, was 85 nm. Thus, the preparation of Si NW arrays from Si wafers through electroless etching has potential as an inexpensive technique for the mass-production of various device architectures and applications.

Acknowledgment This study was supported by the Ministry of Science and Technology in Taiwan (MOST 103-2221-E-194 -050 -MY2 and 105-2221-E-194 -017).

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Zheng, G. F.; Lu, W.; Jin, S.; Lieber, C. M., Synthesis and Fabrication of


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High-Performance N-Type Silicon Nanowire Transistors. Adv. Mater. 2004, 16, 1890-1893. 2. Schmidt, V.; Riel, H.; Senz, S.; Karg, S.; Riess, W.; Gosele, U., Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor. Small 2006, 2, 85-88. 3. Huang, Y.; Duan, X. F.; Cui, Y.; Lauhon, L. J.; Kim, K. H.; Lieber, C. M., Logic Gates and Computation from Assembled Nanowire Building Blocks. Science 2001, 294, 1313-1317. 4. Zhong, Z. H.; Wang, D. L.; Cui, Y.; Bockrath, M. W.; Lieber, C. M., Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems. Science 2003, 302, 1377-1379. 5. Lieber, C. M.; Tian, B. Z.; Zheng, X. L.; Kempa, T. J.; Fang, Y.; Yu, N. F.; Yu, G. H.; Huang, J. L., Coaxial Silicon Nanowires as Solar Cells and Nanoelectronic Power Sources. Nature 2007, 449, 885-890. 6. Garnett, E.; Yang, P. D., Light Trapping in Silicon Nanowire Solar Cells. Nano Lett. 2010, 10, 1082-1087. 7. Das, K.; Mukherjee, S.; Manna, S.; Ray, S. K.; Raychaudhuri, A. K., Single Si Nanowire (Diameter

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