Letter www.acsami.org
Cite This: ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Parylene-Based Double-Layer Gate Dielectrics for Organic FieldEffect Transistors Hyunjin Park,† Hyungju Ahn,‡ Jimin Kwon,§ Seongju Kim,⊥ and Sungjune Jung*,†,§ †
Department of Electrical Engineering, §Department of Creative IT Engineering, and ⊥Department of Mechanical Engineering, Pohang University of Science and Technology (POSTECH), 77 Cheongam-Ro, Nam-Gu, Pohang 37673, Republic of Korea ‡ Pohang Accelerator Laboratory, 77 Cheongam-Ro, Nam-Gu, Pohang 37673, Republic of Korea
Downloaded via KAOHSIUNG MEDICAL UNIV on October 27, 2018 at 06:18:07 (UTC). See https://pubs.acs.org/sharingguidelines for options on how to legitimately share published articles.
S Supporting Information *
ABSTRACT: We demonstrate high-performance and stable organic field-effect transistors (OFETs) using parylene-based double-layer gate dielectrics (DLGDs). DLGDs, consisting of parylene C as the upper layer and F as the lower layer, are designed to simultaneously provide good interface and bulk gate dielectric properties by exploiting the advantages of each gate dielectric. The structural effects of DLGDs are systematically investigated by evaluating the electrical characteristics and dielectric properties while varying the thickness ratio of each gate dielectric. The OFET with the optimized DLGD exhibits high performance and operational stability. This systematic approach will be useful for realizing practical electronic applications. KEYWORDS: parylene, double-layer gate dielectrics, stability, organic field-effect transistors, bias stress rganic field-effect transistors (OFETs) have received significant attention in research and industry for their potential to provide flexible, low-cost, and large-area electronics such as displays,1 sensors,2 and memories.3 Although recent efforts have remarkably improved device performance, stability issues must be resolved before OFETs see commercially viable electronics. The gate dielectric is one of the most important components that determine the device performance because it affects the ordering and crystallinity of organic semiconductors (OSCs).4,5 For a high-performance OFET, an insulating polymer should meet essential requirements, including a high dielectric constant to induce more charges in the channel, high dielectric strength to allow lowvoltage operation and high dielectric quality to reduce leakage current (Ileak). In addition, the gate dielectric-induced operational instability attributed to the polarization effect,6 ion migration,7 charge injection into the gate dielectric bulk,8 and charge trapping at the interface should be suppressed for highly stable OFETs.9 However, most single-layer gate dielectrics (SLGDs) do not simultaneously fulfill these requirements. Double-layer gate dielectrics (DLGDs) consisting of two different insulating polymers have been suggested to overcome the SLGD-induced operational instability by exploiting the advantages of each gate dielectric. DLGDs have been utilized to adjust the surface energy,10 reduce the gate-source current (IGS),11 tune the threshold voltage (VTH),12 and provide a smooth surface.13 Moreover, they have been used to compensate for two different SLGD-induced operational instability mechanisms by varying the thickness ratio of each gate dielectric.12−14 As a result, the operational stability of OFETs has been considerably improved, but the structural
O
© XXXX American Chemical Society
effects of DLGDs on the device performance has not been discussed in detail yet.15−17 An appropriate insulating polymer should be carefully selected because the gate dielectric has a significant impact on the device performance. Among the various insulating polymers, poly(para-xylylene) (parylene) is widely used as a gate dielectric because it has many attractive properties such as a good conformal shape, pinhole-free surface, excellent mechanical flexibility, and remarkable chemical resistance. Among the parylene families, C, F, N, and SR have been used to fabricate OFETs.18−22 Despite the good insulating properties, OFETs with parylene-based SLGDs exhibit a threshold voltage shift (ΔVTH) attributed to the polarization effect and interface charge trapping.22,23 Fukuda et al. reported that the polarization effect due to the crystallinity of the parylene C containing a chlorine atom or dipole in a single repeating unit leads to positive ΔVTH of OFETs.23 To suppress the ΔVTH, they used DLGDs to compensate for the polarization effect of parylene C by the interface charge trapping of amorphous fluoropolymer.12 However, the operational stability of OFETs with DLGDs have not been fairly investigated because the same gate-source voltage (VGS) was applied despite the difference in gate dielectric thickness (td). Here, we have systematically investigated the structure effects of parylene-based DLGDs on the electrical characteristics and operational stability of OFETs. To evaluate the gate dielectric properties of parylene C and F SLGD, respectively, we fabricated bottom-gate top-contact (BGTC) OFETs based Received: July 26, 2018 Accepted: October 25, 2018 Published: October 25, 2018 A
DOI: 10.1021/acsami.8b12663 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Letter
ACS Applied Materials & Interfaces
Figure 1. (a) Chemical structures of parylene C and F and schematic diagram of BGTC OFET with parylene SLGD. (b) Typical transfer curves for OFETs with parylene SLGDs. The solid line and dashed line represent IDS and IGS, respectively. (c) εr of MIM capacitors with parylene SLGDs as a function of frequency. (d) Ileak of MIM capacitors with parylene SLGDs as a function of Efield. (e) Normalized IDS of OFETs with parylene SLGDs as a function of t.
One of the obvious differences in transfer curves is the direction of the ΔVTH. The OFET with parylene C shows a positive ΔVTH, whereas a negative ΔVTH is observed in the OFET with parylene F. MIM capacitors were fabricated to investigate the effects of parylene types on the dielectric properties that significantly affect the device performance. It is noted that parylene C induces a positive ΔVTH due to switching dipoles of the chlorine atoms in the gate dielectric bulk, namely the polarization effect.12,23 The polarization effect of parylene C was confirmed by extracting the dielectric constant (εr) of the MIM capacitor as a function of frequency (f) (Figure 1c). The εr of parylene C considerably increases from 2.75 to 3.74 as frequency decreases from 1 MHz to 10 Hz. In contrast, the parylene F exhibits a similar εr of 2.2 regardless of frequency. The results imply that ΔVTH in the transfer curves are mainly due to the polarization effect for an OFET with parylene C and the interface charge trapping for an OFET with parylene F. Furthermore, the Ileak of MIM capacitors as a function of electric field (Efield) is in good agreement with the IGS of OFETs (Figure 1d). Long-term operational stability was evaluated by investigating the bias stress effect of the corresponding OFETs under continuous DC bias on the gate and drain electrodes (EGS = 1 MV cm−1, VGS = VDS) (Figure 1e). The normalized IDS as a function of bias stress time (= IDS(t)IDS(0)−1, where t is the bias stress time and IDS(0) is the initial IDS before bias stress) strongly depends on the parylene types. The normalized IDS of the OFET with parylene C increases at the beginning of bias stress due to the polarization effect and exhibits a slower decay
on 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) and metal−insulator−metal (MIM) capacitors. Then, DLGDs consisting of parylene C and F were designed to exploit the advantages of each gate dielectric and the electrical characteristics of OFETs using DLGDs were investigated by varying the thickness ratio of each gate dielectric. To observe the structural effects of DLGDs on the device performance, we evaluated gate dielectric properties by dividing into bulk and interfacial components. The OFET with the optimized parylene DLGD exhibits highly stable operation under the bias stress while maintaining high performance. We fabricated BGTC OFETs based on TIPS-pentacene with parylene C and F SLGD, respectively, to investigate the effects of parylene types on the electrical characteristics and operational stability (Figure 1a). The OFET with parylene C exhibits a higher drain-source current (IDS) and a steeper subthreshold swing (SS) than that with parylene F (Figure 1b). In terms of IGS, the OFET with parylene F is an order magnitude lower than that with parylene C. For quantitative comparison, electrical parameters of OFETs such as the VTH, field-effect mobility (μFET), on/off current ratio (Ion/Ioff), and SS were extracted and summarized in table S1. The OFET with parylene C shows lower threshold electric-field (ETH = VTHtd−1) of −0.08 MV cm−1, higher μFET of 0.12 cm2 V−1 s−1, larger Ion/Ioff of 1.02 × 107, and smaller SS of 0.26 V decade−1 than that with parylene F, whose ETH, μFET, Ion/Ioff, and SS are −0.15 MV cm−1, 0.09 cm2 V−1 s−1, 3.39 × 106, and 1.42 V decade−1, respectively. B
DOI: 10.1021/acsami.8b12663 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Letter
ACS Applied Materials & Interfaces
Figure 2. (a) Schematic diagram of BGTC OFET with parylene DLGD. (b) Typical transfer curves for OFETs using parylene DLGDs with varying X. The solid line and dashed line represent IDS and IGS, respectively. Plot of (c) μFET and ETH and (d) Ion/Ioff and SS as a function of X. (e) Normalized IDS of OFETs with parylene DLGDs as a function of t. (f) Plot of τ and β as a function of X.
than that with parylene F. The degree of bias stress-induced IDS decay is quantitatively estimated using a stretched exponential function: ÅÄÅ ÑÉ ÅÅ ij t yz β ÑÑÑ Å IDS(t ) = IDS(0)expÅÅ−jj zz ÑÑÑ ÅÅ k τ { ÑÑ (1) ÅÇ ÑÖ
study, the electrical parameters were extracted and summarized in Table S1. As can be seen in Figure 2c, d, OFETs show three discriminable regions according to the X: a region I (1 > X ≥ 0.63); a region II (0.63 > X > 0.33); and a region III (0.33 ≥ X > 0). In region I, OFETs with parylene DLGDs exhibit similar transfer characteristics to that with parylene C SLGD in terms of ETH, μFET, Ion/Ioff, and SS, which are roughly −0.08 MV cm−1, 0.13 cm2 V−1 s−1, 6 × 106, and 0.6 V decade−1, respectively. Particularly, a relatively high IGS is observed with OFETs using X of 0.71 and 0.78 of parylene DLGDs even though parylene F is inserted between the parylene C and the gate electrode. In contrast, OFETs with parylene DLGDs in the region III exhibit device performance, including low IGS, similar to that with parylene F SLGD even though it does not directly contact the OSC. As the X decreases in the region II, ETH increases from −0.09 to −0.14 MV cm−1, μFET decreases from 0.15 to 0.07 cm2 V−1 s−1, Ion/Ioff decreases from 7.16 × 106 to 3.34 × 106 and SS increases from 0.93 to 1.72 V decade−1. We investigated the structural effects of parylene DLGDs on the operational stability of OFETs by evaluating the bias stress effect. The normalized IDS of OFETs with various X of parylene DLGDs as a function of t is shown in Figure 2e. OFETs using DLGDs with X higher than 0.63 exhibit slow IDS decay similar to that with parylene SLGD. However, a small increase in IDS at the beginning of bias stress is observed with OFETs using 0.71 and 0.78 thickness ratios of DLGDs (the
where τ is the characteristic trapping time constant and β is the dispersion parameter.7,24 Although the τ of OFETs are higher than 104 s regardless of parylene types, the OFET with parylene C exhibits a higher βC of 0.63 than that with parylene F (βF = 0.37). The results clearly show that parylene C provides better gate dielectric interface properties, resulting in higher μFET, smaller SS and higher β, whereas better gate dielectric bulk properties, such as higher breakdown Efield, lower IGS and negligible polarization effects, can be obtained by using parylene F. Next, a parylene-based DLGD consisting of parylene C as the upper layer and parylene F as the lower layer was designed to fully exploit the advantages of each gate dielectric to simultaneously provide better interface and bulk dielectric properties (Figure 2a). To investigate the structural effects of parylene DLGDs on the electrical characteristics of OFETs, we fabricated BGTC OFETs with varying thickness ratio of each gate dielectric (X = tC(tC + tF)−1, where tC and tF are the thicknesses of parylene C and F, respectively). The transfer characteristics of OFETs, such as IDS and IGS, are dependent on parylene DLGD conditions (Figure 2b). For comparative C
DOI: 10.1021/acsami.8b12663 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Letter
ACS Applied Materials & Interfaces
Figure 3. (a−d) AFM images and (e−h) DI water CA measurement images of four different parylene-based gate dielectric conditions. The X of (a, e) 1, (b, f) 0.63, (c, g) 0.33, and (d, h) 0 represents parylene C, parylene DLGD in region I, parylene DLGD in region III, and parylene F, respectively.
Figure 4. (a−d) POM images and (e−h) 2D GIXRD patterns of TIPS-pentacene thin films on four different parylene-based gate dielectric conditions. (i) Out-of-plane XRD patterns of TIPS-pentacene thin films on parylene-based gate dielectrics. The X of (a, e) 1, (b, f) 0.63, (c, g) 0.33, and (d, h) 0 represents parylene C, parylene DLGD in region I, parylene DLGD in region III, and parylene F, respectively.
in the electrical characteristics were mainly attributed to different orientation between the source/drain electrodes and crystalline of TIPS-pentacene thin films in the channel area. The insulating properties of gate dielectrics were characterized by dividing them into bulk and interface components to investigate the structural effects of DLGDs on device performance. Dielectric constants of MIM capacitors with parylene DLGDs were extracted to evaluate the bulk properties. Naturally, the dielectric constant of parylene DLGDs was only proportional to the X and shows a severe frequency dependence with a higher X (Figure S1). Furthermore, surface roughness and deionized (DI) water contact angle (CA) of parylene-based gate dielectrics were measured to investigate the interface properties (Figure 3). It is noted that the surface roughness of the gate dielectric is one of the most important factors in charge carrier transport at the
inset of Figure 2e). In contrast, OFETs with higher parylene F thickness ratio does not exhibit IDS increase at the beginning of bias stress because they suppressed the polarization effect of gate dielectric bulk. For quantitative comparison, τ and β were extracted using eq 1 and summarized in Table S1. The τ is about 105 s regardless of the X of DLGD, but, like the electrical parameters, the β shows three discriminable regions according to the X (Figure 2f). In the region I, β is always higher than 0.54 and increases to 0.63 with a higher X. In contrast, β of 0.37 is obtained in the region III. The results clarify that the lower layer of DLGDs, parylene F, considerably affects device performance, including electrical characteristics and operational stability of OFETs, by inducing charge trapping near the interface even though it does not directly contact to the OSC. This result is consistent with the previous results reported by Fukuda et al.12 and Zhao et al.13 We speculate that variations D
DOI: 10.1021/acsami.8b12663 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Letter
ACS Applied Materials & Interfaces interface, but it has not been carefully addressed during OFET fabrication and electrical measurement.25,26 Previous studies have reported that the smooth surface resulting of the optimized DLGD condition improves device performance including operational stability.13,14 The parylene-based gate dielectrics show a root-mean-square (Rq) of surface roughness of less than 3 nm regardless of the X (Figure 3a−d and Figure S2). Moreover, the DI water CAs were estimated to be approximately 90° regardless of gate dielectric conditions (Figures 3e−h and Figure S3). The interfacial properties of parylene-based gate dielectrics were also investigated by recording polarized optical microscope (POM) images and measuring two-dimensional grazing incidence X-ray diffraction (2D GIXRD) patterns to observe the crystallinity of TIPS-pentacene thin films. POM images of TIPS-pentacene thin films on parylene-based gate dielectrics exhibit millimeter-scale domain size regardless of gate dielectric conditions because of the identical surface condition (Figures 4a−d and Figure S4). 2D GIXRD patterns of TIPSpentacene thin films are preferentially oriented along the (00l) crystallographic direction, namely “edge-on” orientation (Figure 4e−h and Figure S5). In addition, the crystalline structure of TIPS-pentacene thin films along the out-of-plane exhibit similar diffractogram peaks (Figure 4i and Figure S6). With (001) reflection, the interlayer distance (d-spacing) was calculated to be 17.6 Å using d = 2π·qr,z−1 and this value is comparable to previously reported data for well-aligned TIPSpentacene thin films.27,28 Despite the different thickness ratios, the parylene-based gate dielectrics exhibit identical surface conditions confirmed by surface roughness, DI water CA, and crystallinity of TIPSpentacene thin films. On the other hand, the dielectric constant are considerably dependent on the X. In addition, the electrical characteristics indirectly imply that the lower layer of parylene DLGDs, parylene F, obviously affects charge transport of OFETs by inducing charge trap sites near the interface even though it does not directly contact the OSC. Thus, it is reasonable to conclude that the bulk of parylene DLGDs are predominantly leading to the difference in device performance. In conclusion, we have systematically investigated the structural effects of parylene DLGDs on the electrical characteristics and operational stability of OFETs while varying the thickness ratio. Parylene DLGD was designed to exploit the advantages of each gate dielectric and thus resulted in better interface and bulk properties at the same time. The results reveal that parylene F, the lower layer of DLGD, affects charge transport by inducing more charge trap sites near the interface even though it does not directly contact the OSC. The OFET with the optimized parylene DLGD, the X of 0.63, exhibits high performance and stability, such as high μFET, small SS, low IGS, and suppressed bias stress. This systematic approach to design DLGDs will be useful for manufacturing electronic applications.
■
■
TIPS-pentacene thin films; 2D GIXRD patterns of TIPS-pentacene thin films; and XRD patterns of TIPSpentacene thin films (PDF)
AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. ORCID
Hyunjin Park: 0000-0003-1838-8149 Sungjune Jung: 0000-0001-9258-0572 Notes
The authors declare no competing financial interest.
■
ACKNOWLEDGMENTS This work was supported by a grant (Code 2015M3A6A5072945) from the Center for Advanced Soft Electronics under the Global Frontier Research Program of the Ministry of Science and ICT (MSIT) of South Korea, and by the MSIT, Korea, under the “ICT Consilience Creative program” (IITP-2018-2011-1-00783) supervised by the IITP (Institute for Information & communications Technology Promotion).
■
REFERENCES
(1) Rogers, J. A.; Bao, Z.; Baldwin, K.; Dodabalapur, A.; Crone, B.; Raju, V. R.; Kuck, V.; Katz, H.; Amundson, K.; Ewing, J.; Drzaic, P. Paper-like Electronic Displays: Large-Area Rubber-Stamped Plastic Sheets of Electronics and Microencapsulated Electrophoretic Inks. Proc. Natl. Acad. Sci. U. S. A. 2001, 98 (9), 4835−4840. (2) Someya, T.; Kato, Y.; Sekitani, T.; Iba, S.; Noguchi, Y.; Murase, Y.; Kawaguchi, H.; Sakurai, T. Conformable, Flexible, Large-Area Networks of Pressure and Thermal Sensors with Organic Transistor Active Matrixes. Proc. Natl. Acad. Sci. U. S. A. 2005, 102 (35), 12321− 12325. (3) Myny, K.; Smout, S.; Rockelé, M.; Bhoolokam, A.; Ke, T. H.; Steudel, S.; Cobb, B.; Gulati, A.; Rodriguez, F. G.; Obata, K.; et al. A Thin-Film Microprocessor with Inkjet Print-Programmable Memory. Sci. Rep. 2015, 4 (1), 7398. (4) Kim, C.; Facchetti, A.; Marks, T. J. Gate Dielectric Microstructural Control of Pentacene Film Growth Mode and Field-Effect Transistor Performance. Adv. Mater. 2007, 19 (18), 2561−2566. (5) Effertz, C.; Lahme, S.; Schulz, P.; Segger, I.; Wuttig, M.; Classen, A.; Bolm, C. Design of Novel Dielectric Surface Modifications for Perylene Thin-Film Transistors. Adv. Funct. Mater. 2012, 22 (2), 415−420. (6) Larsson, O.; Said, E.; Berggren, M.; Crispin, X. Insulator Polarization Mechanisms in Polyelectrolyte-Gated Organic FieldEffect Transistors. Adv. Funct. Mater. 2009, 19 (20), 3334−3341. (7) Mathijssen, S. G. J.; Cölle, M.; Gomes, H.; Smits, E. C. P.; de Boer, B.; McCulloch, I.; Bobbert, P. A.; de Leeuw, D. M. Dynamics of Threshold Voltage Shifts in Organic and Amorphous Silicon FieldEffect Transistors. Adv. Mater. 2007, 19 (19), 2785−2789. (8) Lee, C. A.; Park, D.-W.; Jung, K.-D.; Kim, B.; Kim, Y. C.; Lee, J. D.; Park, B.-G. Hysteresis Mechanism in Pentacene Thin-Film Transistors with Poly(4-Vinyl Phenol) Gate Insulator. Appl. Phys. Lett. 2006, 89 (26), 262120. (9) Choi, H. H.; Lee, W. H.; Cho, K. Bias-Stress-Induced Charge Trapping at Polymer Chain Ends of Polymer Gate-Dielectrics in Organic Transistors. Adv. Funct. Mater. 2012, 22 (22), 4833−4839. (10) Park, S. Y.; Park, M.; Lee, H. H. Cooperative Polymer Gate Dielectrics in Organic Thin-Film Transistors. Appl. Phys. Lett. 2004, 85 (12), 2283−2285. (11) Shin, E.-Y.; Choi, E.-Y.; Noh, Y.-Y. Parylene Based Bilayer Flexible Gate Dielectric Layer for Top-Gated Organic Field-Effect Transistors. Org. Electron. 2017, 46, 14−21.
ASSOCIATED CONTENT
S Supporting Information *
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.8b12663. Experimental details; parameters of OFETs with parylene-based gate dielectrics; dielectric constants of parylene DLGDs; AFM images of parylene DLGDs; contact angles of parylene DLGDs; POM images of E
DOI: 10.1021/acsami.8b12663 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Letter
ACS Applied Materials & Interfaces (12) Fukuda, K.; Suzuki, T.; Kobayashi, T.; Kumaki, D.; Tokito, S. Suppression of Threshold Voltage Shifts in Organic Thin-Film Transistors with Bilayer Gate Dielectrics. Phys. Status Solidi A 2013, 210 (5), 839−844. (13) Zhao, J.; Tang, W.; Li, Q.; Liu, W.; Guo, X. Fully Solution Processed Bottom-Gate Organic Field-Effect Transistor With Steep Subthreshold Swing Approaching the Theoretical Limit. IEEE Electron Device Lett. 2017, 38 (10), 1465−1468. (14) Kim, M. S.; Lee, D.-H.; Cho, H. J.; Oh, J.; Lee, S. Y.; Kim, J. M.; Park, K.; Kim, Y.-S. The Effect of Indirect UV/Ozone Treatment on Pentacene Thin Film Transistors with Double-Stacked Organic Gate Insulators. Org. Electron. 2018, 52, 295−300. (15) Ng, T. N.; Daniel, J. H.; Sambandan, S.; Arias, A.-C.; Chabinyc, M. L.; Street, R. A. Gate Bias Stress Effects Due to Polymer Gate Dielectrics in Organic Thin-Film Transistors. J. Appl. Phys. 2008, 103 (4), 044506. (16) Tang, W.; Zhao, J.; Huang, Y.; Ding, L.; Li, Q.; Li, J.; You, P.; Yan, F.; Guo, X. Bias Stress Stability Improvement in SolutionProcessed Low-Voltage Organic Field-Effect Transistors Using Relaxor Ferroelectric Polymer Gate Dielectric. IEEE Electron Device Lett. 2017, 38 (6), 748−751. (17) Ruzgar, S.; Caglar, M. Use of Bilayer Gate Insulator to Increase the Electrical Performance of Pentacene Based Transistor. Synth. Met. 2017, 232, 46−51. (18) Fukuda, K.; Minamiki, T.; Minami, T.; Watanabe, M.; Fukuda, T.; Kumaki, D.; Tokito, S. Printed Organic Transistors with Uniform Electrical Performance and Their Application to Amplifiers in Biosensors. Adv. Electron. Mater. 2015, 1 (7), 1400052. (19) Kubozono, Y.; Haas, S.; Kalb, W. L.; Joris, P.; Meng, F.; Fujiwara, A.; Batlogg, B. High-Performance C60 Thin-Film FieldEffect Transistors with Parylene Gate Insulator. Appl. Phys. Lett. 2008, 93 (3), 033316. (20) Kwon, J.; Takeda, Y.; Fukuda, K.; Cho, K.; Tokito, S.; Jung, S. Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability. ACS Nano 2016, 10 (11), 10324−10330. (21) Erouel, M.; Tardy, J.; André, E.; Garden, J.-L. Poly(Tetrafluorop -Xylylene): A Low Dielectric Constant Polymer Gate Insulator for Organic Transistors. Sens. Lett. 2011, 9 (6), 2275−2278. (22) Ryu, K. K.; Nausieda, I.; He, D. Da; Akinwande, A. I.; Bulovic, V.; Sodini, C. G. Bias-Stress Effect in Pentacene Organic Thin-Film Transistors. IEEE Trans. Electron Devices 2010, 57 (5), 1003−1008. (23) Fukuda, K.; Suzuki, T.; Kumaki, D.; Tokito, S. Reverse DC Bias Stress Shifts in Organic Thin-Film Transistors with Gate Dielectrics Using Parylene-C. Phys. Status Solidi A 2012, 209 (10), 2073−2077. (24) Miyadera, T.; Wang, S. D.; Minari, T.; Tsukagoshi, K.; Aoyagi, Y. Charge Trapping Induced Current Instability in Pentacene Thin Film Transistors: Trapping Barrier and Effect of Surface Treatment. Appl. Phys. Lett. 2008, 93 (3), 033304. (25) Virkar, A. A.; Mannsfeld, S.; Bao, Z.; Stingelin, N. Organic Semiconductor Growth and Morphology Considerations for Organic Thin-Film Transistors. Adv. Mater. 2010, 22 (34), 3857−3875. (26) Lim, J. A.; Lee, H. S.; Lee, W. H.; Cho, K. Control of the Morphology and Structural Development of Solution-Processed Functionalized Acenes for High-Performance Organic Transistors. Adv. Funct. Mater. 2009, 19 (10), 1515−1525. (27) Anthony, J. E.; Brooks, J. S.; Eaton, D. L.; Parkin, S. R. Functionalized Pentacene: Improved Electronic Properties from Control of Solid-State Order. J. Am. Chem. Soc. 2001, 123 (38), 9482−9483. (28) Yu, X.; Zhou, N.; Han, S.; Lin, H.; Buchholz, D. B.; Yu, J.; Chang, R. P. H.; Marks, T. J.; Facchetti, A. Flexible Spray-Coated TIPS-Pentacene Organic Thin-Film Transistors as Ammonia Gas Sensors. J. Mater. Chem. C 2013, 1 (40), 6532.
F
DOI: 10.1021/acsami.8b12663 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
