Polymer Electrolyte Blend Gate Dielectrics for High-Performance

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Polymer Electrolyte Blend Gate Dielectrics for HighPerformance Ultrathin Organic Transistors: Toward Favorable Polymer Blend Miscibility and Reliability Benjamin Nketia-Yawson, Grace Dansoa Tabi, and Yong-Young Noh ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.9b03999 • Publication Date (Web): 25 Apr 2019 Downloaded from http://pubs.acs.org on April 25, 2019

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ACS Applied Materials & Interfaces

Polymer Electrolyte Blend Gate Dielectrics for High-Performance Ultrathin Organic Transistors: Toward Favorable Polymer Blend Miscibility and Reliability Benjamin Nketia-Yawson,*,† Grace Dansoa Tabi†, and Yong-Young Noh*,‡ ‡Department

of Chemical Engineering, Pohang University of Science and Technology (POSTECH), 77 Cheongam-Ro, Nam-Gu, Pohang 37673, Republic of Korea. †Department

of Energy and Materials Engineering, Dongguk University, 30 Pildong-ro, 1-gil, Jung-gu, Seoul 04620, Republic of Korea.

Keywords: electrolyte-gated transistors, solid-state electrolytes, polymer blends, charge carrier mobility, semiconductor thickness

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ABSTRACT We report on systematic mobility enhancements in electrolyte-gated organic field-effect transistors (OFETs) by thinning down the active layer and exploiting polymer solid-state electrolyte gate insulators (SEGIs). The SEGI is composed of homogeneous poly(vinylidene fluoride-cohexafluoropropylene) [P(VDF-HFP)] polymer solution-ion gel blends of high areal capacitance >10 µFcm-2 at 1 Hz. By scaling up the poly(3-hexylthiophene) (P3HT) semiconducting layer by one order of magnitude (5–50 nm), an ultraviolet photoelectron spectroscopy examination reveals a downward vacuum level shift generating a substantial hole injection barrier that originates from different interfacial dipole layer formations. The ultrathin (5.1 nm) P3HT FETs outperformed the other devices, exhibiting stable device characteristics with a highest field-effect mobility >2 cm2V1s-1 (effective

mobility of 0.83±0.05 cm2V-1s-1), on/off ratio ~106, low threshold voltage 2 cm2V-1s-1, on/off ratio ~106, and low threshold voltage 1 μFcm-2), demonstrating excellent FET performance with known conjugated


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polymers.22,23 Accordingly, we exploit SEGI-1 in this study. Figure S3 in the Supporting Information shows the electrical characteristics of P3HT/SEGI-2 FETs. Figure 3a,b show the electrical characteristics of P3HT/SEGI-1 FETs for various P3HT thicknesses. Field-effect mobilities of 0.85 ± 0.15, 2.88 ± 0.13, and 3.25 ± 0.40 cm2V-1s-1 were measured in the 50.5, 24.6, and 5.1 nm P3HT devices, respectively (Figure 3c), in the saturation regime (VG = +0.5 to -1.5 V, VD = -1.5 V) at a sweep rate of ~85 mVs-1. The mobilities were estimated in the high |VG| region of 1.0–1.5 V from the linear fit of |ID|0.5 as a function of VG. A positive threshold voltage shift was measured in the P3HT FETs with decreasing active layer thickness (50.5 nm > 24.6 nm > 5.1 nm) in the order of -0.92 ± 0.05 V < -0.68 ± 0.08 V < -0.55 ± 0.05 V, respectively. We will comment again on this VT shift and mobility increase. Figure 3d shows the transfer characteristics of the P3HT (5.1, 24.6, and 50.5 nm)/SEGI-1 FETs at sweep rates of 45, 85, and 181 mVs-1. We observed hysteresis-free transfer curves in the 5.1-nm P3HT devices at different sweep rates, recording a negligible mobility difference. Figure 3e shows the P3HT thickness dependence mobility of various transistor sweep rates. The 50.5-nm P3HT transfer curves exhibited hysteresis behavior, which further enlarges at a faster sweep rate of 181 mVs-1 compared with those of the 24.6-nm P3HT devices. The gradual increasing hysteresis behavior in the P3HT FETs with an active

layer

thickness

is attributed to

P3HT surface roughness and the

interdiffusion

of ions, causing interfacial charge trapping at the SEGI/P3HT interface.18,22 It is noteworthy that downscaling the semiconductor thickness of the FET devices increases the on/off current to 106 while exhibiting low gate-leakage current levels (IG) ~105 below the on-current levels.



Figure 3. SEGI-gated FETs. a) Transfer and b) output curves of P3HT/SEGI-1 FETs with different active layer thicknesses (50.5, 24.6, and 5.1 nm). VG is swept at rate of 85 mVs-1. c) Mobility as function of gate voltage of P3HT/SEGI-1 FETs. d) Transfer characteristics of P3HT/SEGI-1 FETs with P3HT thicknesses of 5.1, 24.6, and 50.5 nm at sweep rates of 45, 85, and 181 mVs-1. e) Corresponding P3HT thickness dependence mobility of various transistor sweep rates.


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Figure 4. a) UPS spectra near cutoff for secondary electron emission (left) and near HOMO edge (right) for P3HT films of 5.1-, 24.6-, and 50.5-nm thickness on Au film, with bare Au thin film as reference. b) Interfacial energy diagrams of P3HT/Au interface acquired by UPS. c) On-state contact resistance of P3HT/SEGI-1 FETs at various VG-VT extrapolated using transfer-line method with various channel lengths.



Interfacial Energy Effects. To investigate the interfacial energy level alignment at the P3HT/Au interface, we examined the highest occupied molecular orbital (HOMO) edge of the P3HT thin films: P3HT (50.5 nm)/Au, P3HT (24.6 nm)/Au, and P3HT (5.1 nm)/Au, and reference Au (40 nm) films, using ultraviolet photoelectron spectroscopy (UPS). As shown in Figure 4a, both the onset of secondary electron emission (Figure 4a, left) and the edge of the HOMO band (Figure 4a, right) revealed an increasing shift with a P3HT thickness relative to that of Au. Figure 4b shows interfacial energy diagrams of the P3HT/Au interface obtained from UPS measurements. The secondary emission cutoff, showing a reduction in the vacuum level (VL) with increasing P3HT thickness, pinpoints the inaccuracy of the traditional assumption of a common VL.27,28 This downward vacuum-level shift generates a substantial hole injection barrier (the Fermi level of Au relative to the position of the HOMO level of P3HT) that originates from different interfacial dipole layer formations.27,28 The relative position of the HOMO band rationalizes the VT shift and strong VG dependence of the field-effect mobilities of the high-capacitance SEGI devices. This developed from the Fermi-level shift through the exponential density of the states near the band edge and depletion-region modulation by VG.29–31 This accounts for the superior performance of the ultrathin 5.1-nm P3HT FET devices owing to a better insulator/semiconductor interface, boost charge carrier density in the transistor channel, and efficient hole injection from the Au electrode owing to its low injection barrier. This resulted in a lowest contact resistance (Rc) of 0.19 ± 0.06 kΩ.cm extracted from individual transistors using the Y-function method (YFM).32,33 The 24.6and 50.5-nm P3HT FETs had a measured Rc of 0.53 ± 0.21 and 2.97 ± 1.63 kΩ·cm, respectively. We further examined the contact resistance of the P3HT FETs by exploring the transfer-line method (TLM) at various channel lengths (Figure 4c and Figure S4, Supporting Information). As presented in Figure 4c, the extrapolated on-state contact resistance from the TLM follows an


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increasing Rc with semiconductor thickness consistent with those extracted using the YFM. From the Figure 4c, on-state Rc of 0.50-0.11, 1.10-0.25 and 2.16-0.36 kΩ·cm were recorded for the 5.1-, 24.6-, and 50.5-nm FET devices, respectively.

Figure 5. Reliability and stability of FET devices. a) Transfer characteristics and b) mobility as function of gate voltage of P(VDF-HFP) gated FETs with P3HT active layer thickness of 50.5, 24.6, and 5.1 nm. c) Reliability factor and threshold voltage dependence on semiconductor thickness of P3HT FETs with SEGI-1 (top) and P(VDF-HFP) gate insulator (bottom). d) Cycling voltage test of P3HT/SEGI-1 FETs at VD = -1.5 V and VG = {0 V, -1.5 V} with P3HT active layer of thickness 5.1 nm (top), 24.6 nm (middle), and 50.5 nm (bottom). W/L = 1 mm/10 µm.



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Table 1. Electrical characteristics of SEGI and P(VDF-HFP) FETs with various P3HT thicknesses. dP3HT

Ca)

μFET

rsat

μeff

VT

SS

(µFcm-2)

(cm V s )

(%)

(cm V s )

(V)

(V per decade)

P(VDF-HFP)

0.0498

0.17 ± 0.04

67.3 ± 3.1

0.12 ± 0.02

-3.30 ± 0.21

-8.71 ± 0.89

~102

SEGI-1

13.26

2.25 ± 0.20

36.9 ± 2.6

0.83 ± 0.05

-0.55 ± 0.05

-0.20 ± 0.03

~106

P(VDF-HFP)

0.0498

0.16 ± 0.04

85.7 ± 8.9

0.14 ± 0.02

-1.04 ± 0.66

-9.19 ± 1.12

~102

SEGI-1

13.26

1.83 ± 0.16

29.1 ± 5.6

0.53 ± 0.06

-0.68 ± 0.08

-0.21 ± 0.03

>105

P(VDF-HFP)

0.0498

0.16 ± 0.03

102.0 ± 7.6

0.15 ± 0.02

0.12 ± 0.46

-10.76 ± 1.13

~102

Insulator

(nm) 5.1

24.6

50.5

2

-1 -1

2

-1 -1

on/off

1.67 ± 0.26 15.6 ± 2.4 0.27 ± 0.08 -0.92 ± 0.05 -0.23 ± 0.03 >10 SEGI-1 13.26 C is average capacitance measured from C-F plots at 1 Hz. Parameters of SEGI FETs are reported from sweep rate of 85 mVs-1. FET device dimensions are W/L = 1 mm/10 μm. 4

a)

Reliability and Stability of FET Devices. For comparison purposes, we also fabricated neat P(VDF-HFP) FETs with various P3HT thicknesses. Figure 5a,b display the transfer curves (Figure 5a) and mobility as a function of a gate voltage (Figure 5b) of 50.5-, 24.6-, and 5.1-nmdeposited P3HT/P(VDF-HFP) FETs at an operation voltage of -15 V. An average mobility of ~0.16 cm2V-1s-1 and near-zero threshold voltages were measured in the P(VDF-HFP) devices, which exhibited less mobility dependence on the P3HT film thickness (Figure 5b). Comparatively, the SEGI-1 FETs showed higher mobilities of more than one order of magnitude greater than those of the P(VDF-HFP) FETs based on the same device dimensions (W/L = 1 mm/10 μm). This was owing to high charge-carrier densities induced by a high-capacitance SEGI and low contact resistance. We measured a higher Rc of 11–27 kΩ·cm in the P(VDF-HFP) FETs. Table 1 summarizes the basic transistor parameters of the P3HT FETs with the SEGI-1 and neat P(VDFHFP) gate dielectric. Larger-channel P3HT/SEGI-1 FETs (W/L = 1 mm/50 μm) exhibited higher mobilities (VT) of 6.70 ± 0.49 cm2V-1s-1 (-0.64 ± 0.08 V), 6.63 ± 0.47 cm2V-1s-1 (-0.87 ± 0.04 V), and 2.10 ± 0.11 cm2V-1s-1 (-1.01 ± 0.01 V) in the SEGI-1 FETs with P3HT thicknesses of 50.5, 14 ACS Paragon Plus Environment

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24.6, and 5.1 nm, respectively, owing to a reduction in the contact resistance effect compared with the shorter-channel devices (W/L = 1 mm/10 μm).32,33 The aforementioned mobility corresponds to an effective carrier mobility (µeff) of 2.01 ± 0.21 cm2V-1s-1, 1.22 ± 0.18 cm2V-1s-1, and 0.23 ± 0.02 cm2V-1s-1 for the 5.1-, 24.6-, and 50.5-nm FET devices, respectively, based on a reliability factor (r) proposed by Choi et al. (see equation in the Experimental Section).7 We calculated an average r in the saturation regime (rsat) (Equation 1, Experimental Section) of 32.2 ± 6.2%, 18.2 ± 2.0%, and 10.7 ± 1.0% in the 5.1-, 24.6-, and 50.5nm P3HT/SEGI-1 FETs, respectively, in larger-channel devices (W/L = 1 mm/50 µm). rsat and μeff of 10 μm L devices are displayed in Table 1. Figure S5 displays the estimated rsat in the P3HT FETs with SEGI-1 and P(VDD-HFP) gate insulators. Figure 5c illustrates the rsat and VT dependence on the P3HT thickness of SEGI-1 and P(VDF-HFP) FET devices based on the same device dimensions (W/L = 1 mm/10 µm). rsat decreases when VT approaches higher values relative to zero VT. This points out the presumed ideal zero VT.7 Figure 5d examines the operational stability of the P3HT/SEGI-1 FETs. The devices were continuously cycled between the on-state (at VG = -1.5 V) and the off-state (at VG = 0 V) at V D = -1.5 V for more than 1000 cycling scans in a nitrogen-filled glove box. Devices with 50-nm P3HT film exhibited a steady on/off ratio decay over 500 cycles (Figure 5d, top). This is attributed to charge trapping at the SEGI/P3HT interface as influenced by the surface roughness of the P3HT thin film and the interdiffusion of ions. However, a high on/off ratio was maintained in the SEGI devices compared with those of the neat P(VDF-HFP) devices (Figure S6, Supporting Information). The 24.6-nm P3HT device (Figure 5d, middle) showed relatively less on-current decay. Sequentially, the 5.1-nm P3HT/SEGI-1 device (Figure 5d, bottom) exhibited no detectable on-current or on/off ratio degradation above 1000 cycles, indicating an ideal interfacial EDL formation and relaxation.



CONCLUSIONS We demonstrated high-performance ultrathin polymer FETs with uniform P(VDF-HFP)EMIM][TFSI] SEGIs thanks to high capacitance values of >10 µFcm-2 and robust device interfacial properties. A significant enhancement in the field-effect mobility was realized in the SEGI devices compared with the neat P(VDF-HFP) devices at higher driving voltages. By thinning down the semiconductor thickness of the FET devices, increasing field-effect mobility was achieved owing to better hole injection properties that resulted in a lower contact resistance and increased charge-carrier densities in the transistor channel. The ultrathin (5.1-nm) P3HT devices exhibited excellent performance with an effective field-effect mobility of 0.83±0.05cm2V-1s-1, low VT ~ -0.55 V, SS ~ -0.20 V/decade, and on/off ratio ~106 during 1.5-V operation in the 10 µm L devices. The 50 µm L devices showed highest mobility of 6.70±0.49 cm2V-1s-1, which correspond to effective field-effect mobility exceeding 2 cm2V-1s-1. This work demonstrated an excellent approach for reliable charge-carrier mobility enhancement and useful insight toward achieving high-performance and stable organic transistors with solid electrolyte gate dielectrics.

EXPERIMENTAL SECTION Device Fabrication. The FET devices were fabricated using top gate bottom contact OFET geometry on conventional lift-off photolithography patterned Corning Eagle 2000 glass substrates (interdigitated source and drain electrodes of Au/Ni = 13/3 nm). FET devices with channel lengths (L) of 10, 20, 30, and 50 μm and a channel width of 1 mm were examined. The clean and ovendried substrates were UV-ozone treated for 20 min. The P3HT (purchased from Rieke Metals, Inc.) 16 ACS Paragon Plus Environment

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solutions (10, 5, and 1 mgmL-1 in chlorobenzene) were spun at 2000 rpm for 60 s, followed by thermal annealing at 150 ºC for 30 min in a nitrogen-filled glove box. The P(VDF-HFP)[EMIM][TFSI] gel solutions was prepared by codissolving P(VDF-HFP) and [EMIM][TFSI] in acetone at a weight ratio of 1:4:7 and then heating at 70 ºC for 24 h in a N2-filled glove box, as in our previous publication. These were then used for the SEGI fabrication.22,23 The SEGIs—VDFHFP solution (30 mgmL-1 in 2-butanone) and P(VDF-HFP)-[EMIM][TFSI] gel solutions—were prepared as in our previous publications.22,23 The SEGI-1 and SEGI-2 contained 1 and 2 v% of P(VDF-HFP)-[EMIM][TFSI] gel solution, respectively. The heated (80 ºC) SEGIs were then spin coated (2000 rpm for 60 s) on the P3HT layer and thermally annealed at 80 ºC for 2 h. The devices were completed by thermal evaporation (~0.5 Å/s) of 40-nm gold as a gate electrode using a metal shadow mask. Device Characterization. The atomic force microscopy (AFM) and field-emission scanning electron microscopy (FE-SEM) images of the SEGI films were measured using a noncontact-mode AFM (Nanoscope, Veeco Instruments, Inc.) and FE-SEM microscope (JSM-7100F), respectively. XPS and UPS analyses were measured using a PHI 5000 VersaProbe II (ULVAC-PHI, Inc.). The P3HT film was crystallinity investigated using a Rigaku RINT 2000 X-ray diffractometer (XRD) with Cu Ka radiation. The absorption spectra of the P3HT thin films were measured with an ultraviolet-visible near-infrared spectrophotometer. The capacitance characteristics were measured with a ZM2376 LCR meter and an LCR meter (HP4284A, Agilent) connected to a semiconductor parameter analyzer (Keithley 4200-SCS). The effective surface area of the MIM structures was 0.01 cm2, and that of the MIS capacitor was 0.0004 cm2. The transistor electrical characteristics were measured with a semiconductor parameter analyzer (Keithley 4200-SCS). The mobility (μ) and VT were calculated in the saturation regime using the standard equation (1): ID =



(W/2L) μsatC(VG - VT)2, where ID is the drain current, VG is the gate voltage, and C is the dielectric capacitance per unit area. The effective carrier mobility (µeff) was estimated using the equation µeff = µsat × rsat, where rsat is the reliability factor in the saturation regime. rsat is defined by the following  equation: r   sat  

ID

max



VG

I D0

max

max

    

2

  ID   VG 

2

   claimed

where |ID|max is the drain current at the maximum gate voltage |VG|max, and I D0 is the drain current at VG = 0.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publication website at DOI: Characterization for SEGIs and P3HT thin films. Additional figures: XPS spectra, UVvisible absorption spectra, GIXD data, and AFM images. Additional figures FET device characteristics with SEGI and neat P(VDF-HFP) gate dielectric.

AUTHOR INFORMATION Corresponding Authors *E-mail: [email protected] (Y.-Y.N.). *E-mail: [email protected] (B.N.-Y.).

Notes The authors declare no competing financial interest.

ACKNOWLEDGEMENTS 18 ACS Paragon Plus Environment

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This work was supported by the Center for Advanced Soft-Electronics (2013M3A6A5073183) funded by the National Research Foundation of Korea through the Ministry of Science & ICT.

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ToC figure


Polymer Electrolyte Blend Gate Dielectrics for High-Performance

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