Rapid, Wet Chemical Fabrication of Radial Junction

20 Sep 2018 - A wet chemical process involving two electrodeposition steps followed by a solution casting step, the EESC process, is described for the...
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Functional Inorganic Materials and Devices

Rapid, Wet Chemical Fabrication of Radial Junction Electroluminescent Wires Shaopeng Qiao, Alana F Ogata, Gaurav Jha, Aurnov Chattopadhyay, and Reginald M. Penner ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b10855 • Publication Date (Web): 20 Sep 2018 Downloaded from http://pubs.acs.org on September 20, 2018

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Rapid, Wet Chemical Fabrication of Radial Junction Electroluminescent Wires Shaopeng Qiao,† Alana F. Ogata,‡ Gaurav Jha,‡ Aurnov Chattopadhyay,¶ and Reginald M. Penner∗,‡ †Department of Physics, University of California, Irvine, California 92697 ‡Department of Chemistry, University of California, Irvine, California 92697 ¶University High School, 4771 Campus Dr, Irvine, California 92612 E-mail: [email protected]

Abstract A wet chemical process involving two electrodeposition steps followed by a solution casting step, the EESC process, is described for the fabrication of electroluminescent, radial junction wires. EESC is demonstrated by assembling three well-studied nanocrystalline (or amorphous) materials: Au,CdSe, and PEDOT:PSS. The tri-layered device architecture produced by EESC minimizes the influence of an electrically resistive CdSe emitter layer by using a highly conductive gold nanowire that serves both as a current collector and a negative electrode. Hole injection, at a high barrier CdSe-PEDOT:PSS interface (φh ≈ 1.1 V), is facilitated by a contact area that is 1.9 - 4.7 fold larger than the complimentary gold-CdSe electron-injecting contact (φe ≈ 0.6 V) contributing to low voltage thresholds (1.4 - 1.7 V) for EL emission. Au@CdSe@PEDOT:PSS wire EL emitters are 25 µm in length, amongst the longest so far demonstrated to our knowledge, but the EESC process is scalable to nanowires of any length, limited only by the length of the central gold nanowire that serves as a

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template for the fabrication process. Radial carrier transport within these multi-shell wires conforms to the back-to-back diode model.

KEYWORDS: Electrodeposition, solution processing, light emitting, EL, Schottky, LED, cadmium selenide.

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Introduction As first demonstrated by Lieber et al. in 2002, 1 radial multi-layer, multi-junction wires that are optimized for efficient EL can be obtained using epitaxial growth processes, starting with vapor-liquid-solid (VLS) growth of III-V vertical nanowire forests. 1–6 These processes yield very low defect materials with excellent control of layer thicknesses, composition and lattice match, resulting in efficient and bright EL light emitters. But these exquisite architectures are obtained at the high cost of the required vacuum and thermal processing and the requirement for significant and nontrivial post-synthesis processing to position wire emitters within circuits, attach electrical contacts, etc. A second issue is the fact that long wires, beyond 5 µm in length, are not generally accessible using this approach. 1–6 At the other end of the spectrum are solution processing methods that facilitate the high-throughput assembly of materials that can be nanocrystalline or even amorphous into devices consisting of layers, often five or more, that are stacked along the direction of charge transport. A layer of semiconductor nanocrystals is usually the EL emissive element in these devices. 7–11 Again, a diversity of efficient and bright EL light emitting systems have been demonstrated for a range of semiconductor emitters. The catch is that solution processing methods have been limited to the preparation of two-dimensional films with millimeter-scale or larger lateral dimensions. 7–15 Adapting these methods to nonplanar geometries such as cylinders or wires is not easily accomplished, nor is miniaturization of these devices. Radial junction EL-emitting wires analogous to those obtained by epitaxial deposition, have not be achieved using solution processing to our knowledge, although recent work in this direction has been published. 16 Can a wet chemical fabrication route to electroluminescent wires be realized, and what level of performance can be achieved for EL emitters prepared by such a process? The EESC process described here is a high throughput, wet-chemical process for assembling a radial junction EL wire emitter consisting of concentric layers of three well-studied nanocrystalline materials: Au, CdSe, and the polystyrene sulfonate (PSS) salt of poly(3,4-ethylenedioxythiophene

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Figure 1: EESC fabrication of a Au@CdSe@PEDOT:PSS EL-emitting wire. a) Schematic threestep EESC process flow for fabrication of Au@CdSe@PEDOT:PSS wires. b) Cross-sectional view of this wire showing gold center electrode, red CdSe emitter layer, and blue PEDOT:PSS hole injecting layer. Electrons (dark blue), injected at the gold-CdSe interface radiatively recombine with holes (white) injected at the CdSe-PEDOT:PSS interface to produce EL emission at the CdSe bandgap. Hole injection is facilitated by a PEDOT:PSS/CdSe interface that is 2 - 5 fold larger than the complimentary gold-CdSe interface, depending upon the diameter of the CdSe shell. c) Energy level diagram showing the relative energies of relevant band edges for Au, PEDOT:PSS and Au as well as the conduction band edge of CdSe. d,e) Schematic band diagrams illustrating energetic relationships for the three layers at equilibrium (d) and in “forward bias” corresponding to Au (-) with Eapp ≈1.6 V (e). φB1 ≈ φB2 = 0.64 eV. Eg = 1.70 eV.

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(PEDOT:PSS). In the first step of the EESC process, ultra-long (mm scale) gold nanowires are fabricated using the lithographically patterned nanowire electrodeposition (LPNE) process. 17,18 Then, 25 µm sections of this gold nanowire are used as electrodes to electrochemically synthesize a conformal and hemicylindrical CdSe shell with a uniform and controlled thickness that, in this study, is varied from 300 - 1200 nm. Finally, a PEDOT:PSS over-coating is applied by spin-coating to complete the device structure (Figure 1a). Since the first electrodeposition step that patterns a gold nanowire is accomplished using LPNE which involves photolithography, EESC is not a “solution processing” scheme in the strictest sense but the LPNE process requires no clean room so it simplifies and accelerates lithographic patterning at the nanometer scale 17,18 while also integrating seamlessly into a process flow that includes wet chemical steps (two in this case). In this proof-of-concept demonstration, the EL wires produced by EESC are 25 µm in length, amongst the longest so far demonstrated to our knowledge, but the EESC process is scalable to nanowires of any length, limited only by the length of the central metal nanowire which can readily be 1.0 cm using LPNE.e.g. 19 These 25 µm wires provide the opportunity to assess the uniformity of light emission along the axis of these structures, as well as other metrics. EL light emission, along the entire length of the wire, is produced by the recombination of injected electrons and holes within the CdSe shell (Figure 1b). In spite of the energetic symmetry of this device (Figure 1c), hole injection, at a high barrier CdSe-PEDOT:PSS interface (φh ≈ 1.1 V), is facilitated by a contact area that is 1.9 - 4.7 fold larger than the complimentary gold-CdSe electron-injecting contact (φe ≈ 0.6 V) contributing to low voltage thresholds (1.4 - 1.7 V) for EL emission. CdSe was selected for this study precisely because we and others have studied it in detail previously, and the differences afforded by the unique EESC devise architecture are directly apparent by making comparisons with our prior work and that of others, as in Table 1. To first order, the EESC architecture, not the composition of the emitter, is the source of these differences.

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Experimental Methods EESC fabrication of Au@CdSe@PEDOT:PSS wires CdSe single nanowire core/shell light emitters were fabricated using EESC using the process flow shown in Figure 2a. Unless otherwise indicated, all solvents and dry chemicals were reagent grade. Here, steps 1-4 are standard LPNE 17,18 processing to produce a gold nanowire. Step 1: a 60 nm thick layer of nickel was thermally evaporated on a precleaned soda lime glass slide (2.5 cm × 2.5 cm × 1 mm). Step 2: A layer of photoresist (PR, Shipley, S1808) was deposited by spin-coating (2500 rpm, 80 s) onto the nickel surface, followed by a soft-bake at (90◦ C) for 30 min. Step 3: The PR-coated nickel was then covered with a contact mask, exposed to UV light (40 mJ/cm2 , 2s), and the exposed PR was developed for 20 s (Microposit, MF-319), rinsed with water (Millipore MilliQ, ρ > 18 MΩ· cm), and air dried. Step 4: The freshly exposed nickel layer was over-etched in 0.80 M nitric acid for 8∼10 min to create a horizontal trench under the PR with a horizontal depth of 1µm at the end of nickel edge. Single gold nanowire was then electrodeposited into this trench potentiostatically at -0.90 V versus saturated calomel electrode (SCE) using a Clean Earth Inc. gold plating solution. Step 5: The photoresist layer was removed with acetone and a second layer of photoresist (Shipley, S1808) was spin-coated and photolithographically patterned to open a 2 mm window exposing the gold nanowire and exposed nickel was removed in nickel etchant (Alfa Aesar Q23A003) for 2 min, resulting an open 2 mm long single gold nanowire. Step 6: The photoresist layer was then removed again with acetone and another thicker layer of photoresist (Shipley, S1827) was deposited by spin-coating. Step 7: A 25µm window was then opened using contact mask within the 2mm long single gold nanowire region. Step 8: The CdSe shell was electrodeposited onto the gold nanowire potentiostatically at -0.60 V versus SCE in an unstirred, room temperature, aqueous plating solution consisting of 0.30 M CdSO4 (CdSO4 ·8H2 O, 98+%, Sigma-Aldrich), 0.70 mM SeO2 (99.999%, Sigma-Aldrich), and 0.25 M H2 SO4 (99.999%, Sigma-Aldrich) at pH 1-2. (Caution: both CdSO4 and SeO2 are highly toxic). Step 9: A PEDOT:PSS layer

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Figure 2: Fabrication of Au@CdSe@PEDOT:PSS wires by EESC. a) Process flow: Step 1 - a 60 nm thick layer of nickel is thermally evaporated on a glass slide. Step 2 - photoresist (PR, Shipley S1808) is spin-coated onto the nickel surface. Step 3 - a horizontal trench 60 nm (h) × 2.5 cm (l) × 1 µm (d) is produced in the PR layer adjacent to the edge of the nickel film. Step 4 - nickel edge is immersed in a Au plating solution and a Au nanowire is electrodeposited using the nickel edge as the working electrode. Step 5 - a 2 mm width trench exposes the gold nanowire. Step 6 - PR layer is removed and a thicker PR layer (Shipley, S1827) is spin-coated. Step 7 - a window of 25 µm width is created. Step 8 - a CdSe shell is electrodeposited on exposed gold nanowire; the thickness of the CdSe shell is controlled by the electrodeposition time. Step 9 - a layer of PEDOT:PSS is applied as a transparent top positive electrode. b,c). Gold electrodeposition cyclic voltammograms (CVs) at 50 mV/s in Clean Earth Inc. gold plating solution, (b) and current vs. time transients (c). d,e). CdSe electrodeposition CVs at 50 mV/s (d) and current vs. time transients and the inset shows CdSe shell thickness vs. electrodeposition time(e).

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(1.0wt.% in water, high-conductivity grade, Sigma-Aldrich) was deposited by spin-coating (2500 rpm, 80 s) onto the whole glass slide two times. All electrodeposition operations were carried out using a Gamry Series G 300 potentiostat in conjunction with a one compartment three-electrode electrochemical cell with saturated calomel reference electrode (SCE) as the reference electrode and platinum foil as the counter electrode. Copper tape was used on the edge of PEDOT:PSS during electrical measurements to protect PEDOT:PSS from metal clip. Structural Characterization. Scanning electron microscopy (SEM) images were acquired using a FEI Magellan 400 XHR system at an accelerating voltage of 8 keV with 2 nm iridium coating. Energy-dispersive X-ray spectroscopy (EDS) images were also acquired using this instrument which is equipped with a 80 mm2 silicon drift X-ray detector (Oxford Instruments, with Aztec software). Samples for cross-sectional SEM were prepared by breaking the sample in half. Electroluminescence and Photoluminescence. EL images as a function of bias were acquired using an inverted microscope (Olympus, IX71) equipped with a 40× objective lens (Olympus, LUCPlanFLN 40 × 0.60) and a CMOS camera (Andor, Neo). Electrical measurements during EL emission were accomplished using a source-meter (Keithley 2400) controlled by LabVIEW software. EQE was calculated using the number of photons out of the single nanowire light emitter divided by the number of electrons flowing through the material per second. CMOS sensitivity and geometry loss was factored into calculation. EL spectra were obtained using a spectrometer (Andor, Shamrock SR-500i-D2) equipped with a 300 l/mm grating blazed at 760nm and a CCD camera (Andor, Newton). All the EL measurements were carried out under room temperature. PL spectra were acquired using a SpectraPro 2300i spectrometer (Princeton Instruments, Acton) excited by a 532nm laser.

Results and Discussion The EESC process. Electroluminescent Au@CdSe@PEDOT:PSS wires were fabri-

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cated using the EESC process flow (Figure 2a) that is also described in greater detail above. In summary, steps 1 - 5 are standard LPNE 17,18 process flow for the fabrication by electrodeposition of a gold nanowire. Steps 6 and 7 are optional, as they provide for masking of the gold nanowire prior to electrodepositing the CdSe shell, in step 8. Electrical contacts are attached in step 9 (Figure 2a). The most critical steps of the EESC process are the two electrodeposition steps: gold in Step 5 and CdSe in Step 8. Gold electrodeposition occurs on a lithographically patterned nickel edge 17,18 under conditions of activation control at -0.90 V vs. SCE, located at the foot of the gold plating wave (Figure 2b), in a commercial gold plating solution (Clean Earth Inc.). 20,21 Approximately 40 min. is required to produce a gold nanowire that is ≈850 nm in width within a 60 nm horizontal trench that defines its height. During this 40 min. the gold plating current increases by a factor of approximately two (Figure 2b) as the solution-wetted gold surface roughens, as clearly seen in the SEM image of Figure 3e, for the gold nanowire (left edge). The CdSe shell, 350 - 1150 nm in radius, is electrodeposited from an aqueous plating solution according to the reaction: Cd2+ + H2 SeO3 + 4H+ + 6e− → CdSe(s) + 3H2 O from a solution containing 0.30 M CdSO4 , 0.70 mM SeO2 , and 0.25 M H2 SO4 at pH 12. 20,21 As previously demonstrated, 20,21 a stoichiometric CdSe layer is obtained by activationcontrolled electrodeposition at a constant potential of -0.60 V vs. SCE (Figure 2d). Using an unstirred, room temperature plating solution, the duration of the CdSe growth is 50 to 250 seconds, depending upon the shell thickness that is desired. 20,21 The deposition current increases during this deposition process in approximate proportion to the increasing area of the hemicylindrical CdSe-surface (Figure 2e). Finally, the PEDOT:PSS layer with a thickness of 100 - 200 nm is deposited by spin-coating (2500 rpm, 80 s) onto the glass slide twice, with air drying of the layer between these two depositions. SEM and AFM characterization. If the PEDOT:PSS layer is omitted, the uniformity of the electrodeposited CdSe layer can be evaluated using SEM. Images for Au@CdSe wires

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Figure 3: Scanning electron microscopy (SEM) and atomic force microscopy (AFM). a) Low magnification SEM image of a 25 µm length Au@CdSe@PEDOT:PSS wire, b) Electron dispersive x-ray (EDX) elemental map showing Cd (green), Se (red) and Au (yellow), c). Cross-sectional SEM image showing (in false color) central gold nanowire (yellow), CdSe shell (red), and PEDOT:PSS top layer (blue). d) EDX elemental map showing Cd (green), Se (red), S (blue) and gold (yellow), e) Bare Au and five Au@CdSe@PEDOT:PSS wires ranging in diameter from 846 nm (left) to 3343 nm (right), f) AFM height traces for the same six GCP wires shown in (e). The excess apparent width seen in these data, relative to the SEM images in (e), is the result of convolution of the AFM tip width with the wire width. The total vertical height is accurate.

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(Figure 3a) shows a smooth CdSe layer with a uniform thickness along the axis of the wire. This uniformity is a direct consequence of kinetically-controlled CdSe electrodeposition that produces a constant current density (A/cm2 ), unaffected by more rapid diffusional transport of Cd2+ and SeO2− 3 expected at the left and right edges of the CdSe layer. EDX elemental maps also show spatially uniform Cd and Se concentrations along the wire axis (Figure 3b) as well as within the CdSe shell (Figure 3d). A Au EDX map (Figure 3b) shows low signal caused by the attenuation of electrons by the intervening CdSe shell, but the EDX signal for this nanowire is seen in the EDX map of the cross-section (Figure 3d). Cross-sectional SEM images of wires (Figure 3c) reveal the gold nanowire at the glass surface, surrounded by the CdSe shell (≈ 1.0 µm in radius), and the PEDOT:PSS overlayer with a thickness varying from 150 nm to 300 nm in this case. The CdSe shell can be grown conformally over a wide range of radii from 300 nm to 1200 nm, as seen in the SEM image and AFM height-distance traces of Figure 3e and 3f, respectively. Transport in Au@CdSe@PEDOT:PSS wires. Au@CdSe@PEDOT:PSS wires are metal-semiconductor-metal (M-S-M) junctions in which both the gold and PEDOT:PSS layers are metallic with approximately the same work function, φ = 5.1 eV (Figure 1c). When contacted by CdSe, both Au and PEDOT:PSS produce a rectifying Schottky barrier (Figure 1d,e). 22–25 For the Au@CdSe@PEDOT:PSS device, the two Schottky barriers are oriented back-to-back: one forward biased (with metal-(+) polarity) and one reverse biased (metal-(−)). For a uniformly n-doped semiconductor (the present case), current is limited by the reverse biased junction and majority electrons dominate charge transport relative to holes. This is because of the disparity between the barrier height for electrons, φn ≈ 0.64 eV and holes, φp ≈ 1.06 eV. If the metal-semiconductor junctions are identical, current versus Eapp (or I-V ) curves show an exponentially increasing current in both directions and are symmetrical about Eapp = 0, conforming to the equation: 23–28

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Figure 4: Transport properties of Au@CdSe@PEDOT:PSS wires (In this figure, (+) bias polarity indicates PEDOT:PSS (+) and Au (-) polarity.) a) Current-voltage (I-V) plots showing the low voltage region (Eapp < 1.0 V) for five CdSe shell thicknesses as indicated. b) Ln(I) versus Ln(Eapp ) from 0 to + 2.5 V for the same five CdSe shell thicknesses showing agreement of these data with the back-to-back Schottky diode model of Eq. 1. The two dashed lines are the predictions of Eq. 1 for back-to-back Schottky barriers, using the parameters of Table 2 for wCdSe = 302 nm (red) and 1164 nm (black). c) Plot of Ln(I/E) versus E 1/2 , and the linear region fitted Poole-Frenkel emission Eq. 3. d) Poole-Frenkel field lowering coefficient, βpf , versus wCdSe showing values an order of magnitude higher than the theoretically predicted value of βpf ≈ 2.5 x 10−5 eV m1/2 V−1/2 .

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I(V ) =

2I1 I2 sinh 

I1 exp −

qV 2n1 KT



qV 2KT



+ I2 exp



qV 2n2 KT



(1)

Where I1 is given by: 22,25–27 −qφB1 I1 = A A1 T exp KT ∗∗

2





(2)

The equation for I2 is analogous. Here A∗∗ is the effective Richardson constant that is assumed to be 15.6 A cm−2 K−1 29 for both Au-CdSe and PEDOT:PSS-CdSe Schottky barriers (Table 2). φB1 is the barrier height for electrons at the Au-CdSe whereas φB2 , used in the analogous expression for I2 , applies to the PEDOT:PSS-CdSe contact (Figure 1d). n1 and n2 are the ideality factors for these two junctions while A1 and A2 are their respective interface areas. 30 But in spite of the symmetry implied by the energy level diagram (Figure 1c), symmetrical I-V curves are not observed (Figure 4a). Instead, significantly more current is seen for Eapp (+) bias, corresponding to Au (-); PEDOT:PSS (+) polarity. Henceforth, we refer to this as “forward bias”. This asymmetry in the I-V curve is attributed to three factors: First, the interfacial area of the CdSe-PEDOT:PSS junction is larger relative to the Au-CdSe junction, a factor that should facilitate hole injection from a (+) PEDOT:PSS contact into CdSe. The ratio of these areas depends upon the radius of the CdSe shell (wCdSe ), and increases from 1.9 (wCdSe = 350 nm) to 4.7 (1140 nm)(Table 2). Second, while both Au and PEDOT:PSS are metallic with similar work functions, they are otherwise very different materials, having radically different electronic structures and densities of states. Just as PEDOT:PSS is superior in terms of hole injection, Au is expected to provide for more efficient electron injection than PEDOT:PSS. Third, the Au-CdSe and PEDOT:PSS-CdSe interfaces are formed using fundamentally different processes - electrodeposition and solution casting, respectively. It is unclear, however, how the fabrication method influences the device properties.

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Ideality factors at both junctions, n1 and n2 , are obtained in the process of fitting experimental I-V curves using Eq. (1) (Table 2). These provide an indication of the degree to which these interfaces are operating in accordance with ideal thermionic emission, characterized by n = 1. 30 Deviations - usually in the positive direction - from n = 1.0 can be caused by image forces acting to reduce the barrier height, to interface states or traps at the interface, and simply by high dopant concentrations in the semiconductor. 30,31 Ideality factor values for the Au-CdSe interface, n1 , are close to unity, ranging from 1.11 to 1.16 (Table 2) suggesting EESC produces a low defect density contact between Au and CdSe, and that the CdSe dopant concentration is not too high to degrade n1 . 32,33 Ideality factors for PEDOT:PSS (n2 ) are higher, ranging from 1.29 to 1.48 (Table 2); larger than measured for Au-CdSe but comparable to, or lower than, n values reported for PEDOT:PSS interfaces with semiconductors, demonstrating that the quality of the PEDOT:PSS-CdSe interace produced by the EECS process is not atypical. 34,35 “Forward bias” (Au (-)) is associated both with higher current (Figure 4a) and stronger EL light emission (vide infra) and within this regime, Eq (1) predicts experimental I-V curves for devices with all five CdSe shell thicknesses and across the entire Eapp range measured here (Figure 4b). The fits to our data using Eq. (1) produce parameters summarized in Table 2 that are physically reasonable including barrier heights in the range from 0.59 to 0.67 eV that are in the range of barriers reported for macroscopic CdSe-Au Schottky barriers 36 and CdSe-PEDOT:PSS Schottky barriers. 37 The tentative conclusion is that in the Au-CdSe-PEDOT:PSS device, the two Schottky junctions are in full control of carrier transport. Control of transport by other processes, operating in the bulk of the CdSe instead of at the junctions, would be revealed by negative deviations of the current from the predictions of Eq. (1). Two common processes invoked to account for such deviations are space charge limited conduction (SCLC) and Poole-Frenkel (P-F) emission. The absence of these two processes is significant because in planar Au-CdSe-Ni EL emitting junctions 20 both SCLC

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and PF emission have been detected at intermediate (0.5 < Eapp < 2 V) and high (Eapp > 3 V) bias conditions, respectively, whereas Schottky control of transport was seen only at low Eapp below 1.0 V. 20 In particular, we looked carefully for evidence of PF emission at high biases because this process releases trapped minority carriers in the CdSe, accentuating EL emission in the bulk of the CdSe, in principle. PF emission is predicted by Eq. 3 which predicts a linear Ln(I/E) versus E 1/2 in the regime of Eapp where PF is occurring: 30,38,39 βpf E 1/2 J = J0 exp kT

!

(3)

where βpf is the PF field-lowering coefficient and E is the magnitude of the electric field (Eapp /wCdSe ). 30,39 Because linear Ln(I/E) versus E 1/2 is also predicted for Schottky emission (Eq. (1)), 30 it is also important to calculate the Poole-Frenkel field lowering coefficient, βP F from the slope of this plot for comparison with the theoretically expected βpf value of 2.55 × 10−5 eV m1/2 V −1/2 40 in order to validate PF emission as a possible contributor to transport. Plots of Ln(I/E) versus E 1/2 (Figure 4c) show linearity over a wide Eapp range consistent with either PF or Schottky emission, but the calculated βP F (Figure 4d) is too high, in the range from 1.5 - 2.8 × 10−4 eV m−1/2 V1/2 which is approximately an order of magnitude higher than the theoretical βpf value. 40 Beyond this, the electric fields generated in the region of linearity (1 × 106 V/m < E < 8 × 106 V/m) are significantly lower than have been required to generate PF emission in similar systems (E ≈ 1 - 7 × 107 V/m). 20 Collectively, the data suggests that the linear Ln(I/E) versus E 1/2 (Figure 4c) is a consequence of Schottky emission, rather than PF emission in these systems. In summary, transport through Au@CdSe@PEDOT:PSS devices, across a wide range of wCdSe and Eapp , conforms to the predictions of Schottky emission at back-to-back Schottky junctions. 25–27,30 EL emission from Au@CdSe@PEDOT:PSS wires. A false color photomicrograph of a Au@CdSe@PEDOT:PSS wire (Figure 5a) shows the CdSe and PEDOT:PSS-coated gold nanowire as a 25 µm wide dark band against the light blue PEDOT-PSS layer, with uncoated 15

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Figure 5: EL emission for Au@CdSe@PEDOT:PSS wires: a) False color photomicrograph of a Au@CdSe@PEDOT:PSS wire showing PR-covered gold nanowire on each side (yellow), and a 25 µm emitter region covered with CdSe (magenta) and PEDOT:PSS (blue). b) EL emission maps for a wCdSe = 1064 nm as a function of Eapp from 1.8 V to 2.8 V. The uniformity of the EL emission intensity along the wire is notable. c,d). EL intensity (c) and external quantum efficiency (EQE) (d) versus Eapp for devices with wCdSe varying from 302 nm to 1064 nmversus Eapp for GCPs with wCdSe varying from 302 nm to 1064 nm. The inset in (c) is a plot of the threshold voltage, Vth , versus wCdSe . Here, Vth is estimated as the lowest voltage at which EL emission is observed above background. e,f). EL intensity (e) and EQE (f) versus electrical field strength, , for Au@CdSe@PEDOT:PSS wires with wCdSe varying from 302 nm to 1064 nm.

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gold nanowire on both sides, protected by photoresist. A copper electrode (not shown), is used to make contact to the PEDOT-PSS layer. The device shown here has the thickest CdSe shell, wCdSe = 1064 nm. The application of a forward bias at the PEDOT:PSS - Au contacts induces EL emission from regions of the wire having all three layers: Au, CdSe, and PEDOT:PSS. Photomicrographs of the device acquired in the dark (Figure 5b) show a voltage threshold for EL, Eth = +1.8 V and an increase in EL intensity with Eapp up to +2.8 V. Light at 1.8 V can not be seen here due to the low light intensity and the contrast settings. Although it is not visible in this figure, for devices with wCdSe = 1064 nm, an onset for EL is actually detected at Eth = +1.7 eV, averaged over several devices. Eth is also inversely correlated with wCdSe (Figure 5a, inset) so thinner shells produce even lower Eth values, down to +1.45 V for wCdSe = 350 nm. All of the data in frames c,d,e and f were acquired in forward bias. Relative to other CdSe-based EL emission systems, this Eth value is amongst the lowest, and in all prior cases of which we are aware, Eth < 2.0 V has required channel lengths below 200 nm (Table 1). For example, gold nanogaps that are 100-200 nm in width and filled with electrodeposited CdSe are characterized by Vth = 1.5 - 1.9 V. 41 Planar M-S-M junctions containing electrodeposited CdSe show Vth = 2.0 V for a CdSe thickness of just 100 nm, but larger values up to 7.0 V for thicker CdSe layers of 450 nm. 20 Electrode spacings of just 30 nm were associated with a Vth = 1.7 V. 42 Relative to the other CdSe-based EL device architectures we have studied, 20,41,43,44 two unique characteristics of the current device is the use of a conformal PEDOT:PSS hole injecting layer and the expansion of the interface area of the PEDOT:PSS with the CdSe emitter layer. Either or both of these factors would be contributing to lower Eth . As already noted above, Au@CdSe@PEDOT:PSS wires are majority carrier devices in terms of transport, but EL requires holes. These holes are commonly injected at the positive contact - PEDOT-PSS in this case - and radiative recombination with electrons produces EL which is localized within one hole diffusion length, Lp , from this contact. In polycrystalline

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II-VI films, typical value for Lp are in the 400-600 nm range. 45,46 The EL intensity is typically minority carrier limited, and this provides an explanation for increasing EL intensity with both Eapp and current (Figures 5c and 5d). Although we are not able to resolve the location of light emission within the CdSe layer in our optical images, the positive correlation with wCdSe (Figure 5c) is evidence that it originates from a layer of thickness Lp from the PEDOT:PSS contact. This is because the volume of EL-producing CdSe and the emitting area of the device both increase with the radius of the CdSe shell in this case. If, on the other hand, EL originates in a layer localized at the Au-CdSe contact, the volume and area of emission will be constant and the opposite dependance on wCdSe should be observed as a thicker CdSe shell self-absorbs the emitted EL. However, this case would not be expected based upon the (-) bias applied to the gold contact in our experiments. It should be noted that the Eapp range explored in the data of Figure 5c,d,e,f corresponds to the range where stable EL was observed. At higher Eapp , the EL intensity was unstable. The maximum external quantum efficiency (EQE) of Au@CdSe@PEDOT:PSS wires increases with Eapp and is in the range from (0.70 - 3.8) × 10−4 (Figure 5d). The correlation of EQE with Eapp has been frequently observed and is attributed to the filling of trap states which mediate nonradiative recombination under high injection conditions. 47–49 Less obvious is the reason for EQE to be inversely correlated with wCdSe (Figure 5d), on average, when EL intensity is directly correlated with wCdSe (Figure 5c). Enhanced EL could be related to E if PF emission were operating (we have already concluded above that it is not) - and thin CdSe shells would exhibit higher efficiency in this case - but neither EQE nor EL intensity are well correlated with E across all five wCdSe values (Figure 5e,f). Self-absorption of emitted EL by the CdSe shell provides one rational higher EQE with decreasing wCdSe . 30 EL spectra. A comparison of photoluminescence (P L) and EL spectra as a function of Eapp (Figure 6a) shows that EL spectra are somewhat broader spectrally for all Eapp , and a slight increase in spectral width is seen with increasing Eapp , visible most clearly in the Gaussian fits of Figure 6b. These EL spectra are far narrowed than those for planar Au-CdSe-Au

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Figure 6: EL spectra for a Au@CdSe@PEDOT:PSS wire. a) Raw EL spectra as a function of Eapp for a Au@CdSe@PEDOT:PSS wire having wCdSe = 788 nm. The P Lspectrum was acquired for this device with excitation at λex = 532 nm. b). Normalized and Gaussian-fitted EL spectra showing red-shifted emission maxima as well as spectral broadening with increased Eapp .

junctions prepared by electrodeposition, 20 where Poole-Frenkel emission was implicated in the transport process. For those devices, EL spectra showed a FWHM approaching 500 nm at Eapp of 8.5 V and 300 nm at 4.5 V 20 whereas in the Au@CdSe@PEDOT:PSS device FWHM are in the 58 - 70 nm range for 2.2 V < Eapp < 2.5 V (Figure 6b). In our prior work, these broad emission envelopes were attributed, in part, to recombination of trapped holes (electrons) with electrons (holes) within the bandgap. 20 With PF emission acting as a major contributor to current transportation, higher electric fields will activate more recombination centers at different energy levels. In the present case, current transport is dominated instead by back-to-back Schottky emission leading to the expectation that band edge emission produced by injected holes and at the (+) contact would be the main radiative recombination mechanism, providing for narrower spectra centered at the CdSe bandgap. 50,51 In addition to broadening, peak EL intensities also red-shift with increasing Eapp . Of course, the current also increases with Eapp and can be expected to drive Joule heating of the device to some extent, thereby decrease in the bandgap in accordance with Varshini’s law. 47–49,52–54 αT 2 Eg (T ) = Eg (0) − β+T

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(4)

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where Eg (0) is the band gap at 0K, α is the T → ∞ limiting value of the band gap shrinkage coefficient dEg (T )/dT and β is a material specific parameter. This heating-induced contraction of the bandgap, caused by a thermally induced increase in the interatomic spacing, has been previously documented for CdSe. 42,55,56

Conclusions EECS is a new, high-throughput process involving two electrodeposition steps and a solution casting step for preparing three-layer, radial junction, electroluminescent wires. A distinguishing feature of EECS is its ability to produce long EL-emitting wires which is enabled by a gold nanowire core prepared using the LPNE process. We demonstrate EECS here by fabricating Au@CdSe@PEDOT:PSS wires 25 µm in length - a record for wire-based EL-emitting devices. The uniformity of the wire structure afforded by EECS is apparent from the uniformity of the EL emission along the wire axis which is excellent. Using the EECS process, EL emitting Au@CdSe@PEDOT:PSS wires of millimeter-scale length should be accessible using exactly the same processing conditions described here. In Au@CdSe@PEDOT:PSS wires, the efficiency of EL emission is significantly improved, by an order of magnitude in EQE, relative to planar Au-CdSe-Au emitters described just two years ago. 20 But further improvements are needed to bring EQE to 1.0 % and above, enabling brightness and efficiency that competes with state-of-the-art quantum dot-based EL devices.

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Table 1: Performance of CdSe Nanostructure-Based Electroluminescent Junctions. Junction Descriptiona

Electrode Spacing (nm)

Vth b (V)

Spectral Range (nm)

EQEmax c

1000 70-120 40

4 5-7 3

480-650 615-650 540-590

1-10×10−5 5×10−6 5.2×10−3

57

--

4

600-630

4-8×10−3

60

---

1.5 15.5

600-635 400-750

0.12-0.18 1.4×10−6

61

122-144

2.25

530-600

0.05

63

125

2.5-3

500-600

0.0131-0.0165

64

175

3

600-700

0.061

65

150

1.7

580-670

0.182

66

130-135

2.5

470-550

0.06

67

--

2.2

560-700

0.051

68

176-228

9

--

0.05

69

30 2000-6000

1.7(±0.1) 4

650-820 620-850

10−5 (1-5)×10−6

42

nc-CdSe in a nanogap

200

1.5(±0.2)

650-890

1.8(±0.7)×10−6

41

nc-CdSe NW arrays

600

6.2(±0.5)

610-890

4(±1)×10−6

44

CdSe tn-ELJ

448

6.9(±0.3)

560-960+

4.9(±0.2)×10−5

20

302 595 788 953 1164

1.44(±0.02) 1.50(±0.00) 1.53(±0.03) 1.60(±0.04) 1.70(±0.04)

650-800 650-800 650-800 650-800 650-800

3.8(±0.6)×10−4 9(±2)×10−5 1.9(±0.6)×10−4 1.5(±0.6)×10−4 7.1(±0.2)×10−5

nc films CdSe QD CdSe QD-PVK CdSe QD-TPD CdSe-CdS core-shell QD CdSe-CdS core-shell QD CdSe QD TPD CdSe-CdS nanoplates CdSe-ZnS core-shell QD CdSe-CdS dot-in-rod QD CdSe-CdZnS QDs core-shell QD CdSe-CdZnS QDs core-shell QD CdSe-CdS dot-in-rod QD CdSe-CdS-ZnS core-shellQD single nanostructures CdSe NR CdSe NW

EESC Au@CdSe@PEDOT:PSS

a Abbreviations:

Ref

58 59

62

70

this work “ “ “ “

NR = nanorod, NW = nanowire, nc = nanocrystals or nanocrystalline, PVK = 21 - bis(3-methylphenyl) - (1,1’-biphenyl) poly(vinylcarbazole), TPD = N,N’ - diphenyl-N,N’ ACS Paragon Plus Environment b 4,4’-diamine. Vth = Eapp at the EL emission threshold. c EQEmax = The maximum EQE.

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Table 2: Fitting Parameters For The Calculation of I-V Curves Using the Back-to-Back Diode Model (Eq. (1)) WCdSe (nm)

A∗∗a (A cm−2 K−1 )

φB1 b (eV)

φB2 c (eV)

n1 d

n2 e

A2 /A1

15.6 15.6 15.6 15.6 15.6

0.628 0.615 0.643 0.653 0.649

0.586 0.638 0.643 0.642 0.672

1.11 1.15 1.14 1.11 1.16

1.48 1.33 1.38 1.38 1.29

1.9 2.8 3.4 4.0 4.7

302 595 788 953 1164 a A∗∗

= effective Richardson constant for CdSe. 29 B1 = Schottky barrier height for Au-CdSe contact. = Schottky barrier height for PEDOT:PSS-CdSe contact. d n = ideality factor for Au-CdSe contact 1 e n = ideality factor for PEDOT:PSS-CdSe contact 2 A1 = interface area for Au-CdSe contact A2 = interface area for PEDOT:PSS-CdSe contact

bφ cφ

B2

Author Information Corresponding Author: E-mail: [email protected]. Notes: The authors declare no competing financial interest.

Acknowledgement The authors gratefully acknowledge the financial support of this work by the National Science Foundation, Division of Materials Research through contract DMR-1206867. FE-SEM data were acquired using instrumentation of the LEXI facility (lexi.eng.uci.edu/) at UCI. P Lspectra were acquired at the Laser Spectroscopy Facility (LSF) at the Department of Chemistry at UCI. The authors thank Dr. Dmitry Fishman, Director of the UCI Chemistry Laser Spectroscopy Facility, for his expert assistance and Professor Rob Corn and his students for providing access to the microscope and CMOS camera used here for EL measurements.

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