NANO LETTERS
Rational Fabrication of Graphene Nanoribbons Using a Nanowire Etch Mask
2009 Vol. 9, No. 5 2083-2087
Jingwei Bai,† Xiangfeng Duan,*,‡,§ and Yu Huang*,†,§ Department of Materials Science and Engineering, Department of Chemistry and Biochemistry, and California Nanosystems Institute, UniVersity of California, Los Angeles, California 90095 Received February 19, 2009
ABSTRACT We report a rational approach to fabricate graphene nanoribbons (GNRs) with sub-10 nm width by employing chemically synthesized nanowires as the physical protection mask in oxygen plasma etch. Atomic force microscopy study shows that the patterns of the resulted nanoribbons replicate exactly those of mask nanowires so that ribbons or branched or crossed graphene nanostructures can be produced. Our study shows a linear scaling relation between the resulted GNR widths and mask nanowire diameters with variable slopes for different etching times. GNRs with controllable widths down to 6 nm have been demonstrated. We have fabricated GNR field effect transistors (FETs) with nanoribbons directly connected to bulk graphene electrodes. Electrical measurements on an 8 nm GNR-FET show room temperature transistor behavior with an on/off ratio around 160, indicating appreciable band gaps arise due to lateral confinement. We find the on/off ratio in the log scale inversely scales with ribbon width. This approach opens a new avenue to graphene nanoribbons and other graphene nanostructures in the deep nanometer regime without sophisticated lithography. It thus opens exciting new opportunities for graphene nanodevice engineering.
Graphene is a two-dimensional crystalline form of carbon: a single layer of carbon atoms arranged in hexagons, like a honeycomb. Ever since it was first reported in 2004, graphene is quickly rising to be one of the hottest material systems for fundamental physics and potential applications in electronics due to its exceptionally high electronic quality.1-5 The room temperature carrier mobilities of graphene devices can reach as high as 10000 cm2/V·s,5 making it an attractive candidate for next generation electronic materials. However, a two-dimensional graphene sheet is a semimetal with a zero bandgap and remains highly conductive even at the charge neutrality point,6,7 which prevents it from being used for an effective field effect transistor at room temperature. It has been suggested that a band gap can open up by fabricating graphene nanostructures of confined geometry such as nanoribbons.8-13 These graphene nanoribbons (GNRs) are predicted to be semiconducting due to edge effects and quantum confinement of the electron wave function in the transverse direction. Theoretical calculations suggest the band gap of GNRs scales inversely with their width, and a width in the sub-10 nanometer regime is required to achieve a * To whom correspondence should be addressed. E-mail: xduan@chem. ucla.edu and
[email protected]. † Department of Materials Science and Engineering, University of California, Los Angeles. ‡ Department of Chemistry and Biochemistry, University of California, Los Angeles. § California Nanosystems Institute, University of California, Los Angeles. 10.1021/nl900531n CCC: $40.75 Published on Web 04/03/2009
2009 American Chemical Society
sufficiently large band gap for room temperature operation. For example, a band gap of 0.67 eV (like that for Ge) requires a width of 2-3 nm.12 However, it is nontrivial to obtain GNRs in the sub-10 nm regime experimentally. Using electron beam (e-beam) lithography and atomic force microscopy (AFM) lithography, GNRs of variable widths have been achieved.14-17 Studies on these GNRs have also confirmed the theoretical calculation that the band gap of the GNRs inversely scales with the width.14 However, the smallest width that can be produced using these lithography approaches is only 15-20 nm, which prevents us from obtaining GNRs with a sufficiently large band gap for room temperature field effect transistors (FETs). Additionally, GNRs obtained from the e-beam lithography approach usually have a line edge roughness of 1-3 nm, which can adversely impact their electronic properties and makes it practically impossible to obtain GNRs in the sub-5 nm regime using conventional lithography. Interestingly, it has recently been reported that chemical exfoliation and sonication can be used to produce GNRs with ultranarrow width down to 2-3 nm with smooth edges. Significantly, room temperature FETs have been demonstrated from these ultranarrow GNRs.18,19 These studies represent important advances in graphene based electronics. However, there is yet no approach to produce GNRs in the sub-10 nm regime in a predictable and controllable
Figure 1. (a-f) Schematic fabrication process to obtain GNRs by oxygen plasma etch with a nanowire etch mask; (g, h) AFM images of a nanowire etch mask lying on top of a graphene flake before (g) and after (h) oxygen plasma etch (The arrows highlight the edge of the graphene sheet.); (i) AFM image of the resulting GNR after sonication removing the mask nanowire; (j, k) branched and crossed graphene nanostructures from merged and crossed nanowire masks. The scale bars in (g-i) are 300 nm, and those in (j, k) are 100 nm.
manner. Herein, we report a rational approach to fabricate sub-10 nm GNRs using chemically synthesized nanowires as etch mask. In contrast to conventional lithography, nanowires can be obtained using various chemical approaches with controllable sizes down to 1-2 nm with a nearly atomically smooth line edge.20-25 Such nanowires can be aligned on top of graphene as a physical mask to protect the underlying graphene layer from oxygen plasma etch. In this way, GNRs in the sub-10 nm regime can be readily produced in a highly controllable manner. We found the width of the resulted GNRs scales well with the nanowire diameter and etch time. GNRs with widths from 6 to 30 nm have been obtained, and room temperature GNR-FETs have also been demonstrated from sub-10 nm GNRs. Figure 1 illustrates our approach to fabricate GNRs with controllable widths. For an initial demonstration, we use mechanically peeled graphene flakes, although the approach described here can be readily extended to graphene sheets or films obtained through chemical approaches.4,26-28 Graphene layers are first mechanically peeled onto a highly doped silicon wafer with 300 nm thermal oxide (Figure 1a).3 The substrate is then calcined at 300 °C to remove organic residue. In general, we focus on graphene flakes with height in the 1-2 nm regime, typically consisting of double layers or few-layer graphene. Silicon nanowires of variable diameters are then aligned onto the graphene to function as 2084
physical etch mask (Figure 1b). The silicon nanowires used here are grown by the Au nanocluster mediated vapor-liquidsolid growth approach. To ensure close contact between the nanowire and graphene sheet, capillary force is introduced by briefly dipping the substrate into isopropyl alcohol (IPA) and blowing dry with nitrogen. After locating the nanowires on top of graphene with an atomic force microscope (AFM, Veeco Dimension 5000), we use oxygen plasma (Diener Electronic) to selectively etch away the unprotected graphene region, leaving GNRs underneath the nanowire mask protection (Figure 1c). The etch time varies from 20 to 60 s at a power level of 40 W. The initial etch is predominantly a vertical etch and can result in GNRs with width comparable to the nanowire diameter. The width of GNRs can be further scaled down with an additional etch that undercuts the graphene underneath the nanowire through a lateral etch (Figure 1e). When the etch process is completed, the nanowire mask can be easily removed by brief sonication to obtain the exposed GNRs on a silicon substrate (Figure 1d,f). AFM is then used to determine GNR width using a procedure described previously.18 Figure 1g shows the AFM image of a nanowire lying on top of a graphene flake. The original graphene flake disappeared after oxygen plasma etching for 20 s (Figure 1h). The GNR underneath the nanowire can then be exposed and observed with AFM when the nanowire is removed by brief sonication (Figure 1i). In this way, GNRs can be obtained in a highly controllable manner. The pattern of the resulting graphene nanostructures follows exactly the same as that of the nanowire mask. Therefore, it is possible to obtain various graphene nanostructures such as bifurcated or crossed structures from nanowire bundles or crossed nanowires (Figure 1j,k). It is important to note these bifurcated or crossed graphene nanostructures are single crystals with a continuous lattice, unlike previous work on carbon nanotube or semiconductor nanowire crossed junctions where a tunneling barrier usually exists.29,30 The ability to replicate these nanowire mask patterns and obtain variable graphene nanostructures is of interest for many potential device applications. The widths of the resulting GNRs are mainly determined by mask width (nanowire diameter) so that GNRs with variable widths down to the sub-10 nm regime can be readily obtained using different diameter nanowire etch masks (Figure 2a-e). To further understand the scaling relation between the diameter of the mask nanowires and the width of the resulting GNRs, we plot GNR width versus nanowire diameter with two different etching durations of 20 and 60 s, respectively (Figure 2f). For a shorter time etch (20 s), most GNRs have similar sizes to those of original nanowires. The slope of the linear fitting for the 20-s etch is about 0.74, indicating a slight undercut effect occurs already for the 20-s etch. Increasing the etch time to 60 s leads to a further undercut with the linear slope dropping to 0.46. Based on the scaling relation observed in Figure 2f, we can rationally predict the width of GNRs from mask nanowire diameter and etch time. In this way, GNRs of controllable widths can be readily obtained in a highly predictable manner. Although Nano Lett., Vol. 9, No. 5, 2009
Figure 2. AFM images of selected GNRs with widths of about (a) 31 nm (height ∼1.5 nm), (b) 23 nm (height ∼1.6 nm), (c) 14 nm (height ∼1.3 nm), (d) 9 nm (height ∼1.2 nm), and (e) 6 nm (height ∼1.0 nm). All scale bars indicate 100 nm. (f) Scaling of the GNR width with mask nanowire diameter for two different oxygen plasma etch times of 20 s (black) and 60 s (red).
our current data do not include the sub-5 nm regime, we believe this approach is fundamentally scalable and can be readily extended down to the sub-5 nm regime by employing a smaller nanowire mask with carefully controlled etch conditions. Another important advantage of our strategy is the relatively smooth etching edge obtained in the GNRs owing to the uniformity and smoothness of the mask nanowires. In contrast, GNRs produced by e-beam lithography usually exhibit much rougher edges due to beam blur and the development process.31 A smooth edge is very important to control the electrical properties of GNRs because the charge carrier confinement is very sensitive to edge configuration and edge disorder could result in an additional state in the energy band structure and an adverse effect on device performance.8,13,32 The ability to fabricate GNRs with controlled width readily allows us to make GNR-FETs with controllable transistor characteristics. To fabricate a GNR-FET, we first align mask nanowire on top of graphene and then use e-beam lithography to pattern source-drain electrodes according to the nanowire location. After development, source-drain electrodes are formed by e-beam evaporation under high vacuum followed by a lift-off process. The device is then subjected to oxygen plasma etch to remove unprotected graphene and obtain a GNR underneath the nanowire connected to two large graphene blocks underneath the source and drain electrodes (Figure 3a). To simplify the device fabrication process, we choose to use oxidized nanowire so that it would not provide a parasitic conductive path even if we do not remove the Nano Lett., Vol. 9, No. 5, 2009
Figure 3. (a) Schematic illustration of the GNR-FET fabrication process. The GNR-FET device is fabricated on a heavily doped silicon substrate with 300 nm SiO2 as gate dielectrics. The GNR connects two large graphene blocks, which are in turn in contact with metal electrodes. Silicon oxide nanowires were used as the etching mask. Electrical measurement was done without removing the nanowire mask, with negligible leakage current through the oxide nanowires. (b) Drain current (Id) versus source-drain voltage (Vd) recorded at different gate voltages for W ∼ 8 nm and channel length ∼ 400 nm (thickness ∼ 1.5nm). (c) Transfer characteristics for the device in (b) at Vd ) -10 mV, -100 mV, and -500 mV.
nanowire in the final device. The oxide nanowires used here are obtained by oxidizing silicon nanowire in air for 5-10 min at 900 °C.33 Separate electrical measurement on oxidized nanowire itself indicates that the parasitic conductance is
