Scalable Preparation of High-Density Semiconducting Carbon

Jan 5, 2018 - Although chemical vapor deposition (CVD)-grown carbon nanotube (CNT) arrays are considered ideal materials for constructing high-perform...
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Scalable Preparation of High-Density Semiconducting Carbon Nanotube Arrays for High Performance Field-Effect Transistors Jia Si, Donglai Zhong, Haitao Xu, Meng-Meng Xiao, Chenxi Yu, Zhiyong Zhang, and Lianmao Peng ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.7b07665 • Publication Date (Web): 05 Jan 2018 Downloaded from http://pubs.acs.org on January 5, 2018

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Scalable Preparation of High-Density Semiconducting Carbon Nanotube Arrays for High Performance Field-Effect Transistors

Jia Si,† Donglai Zhong,† Haitao Xu,† Mengmeng Xiao, Chenxi Yu, Zhiyong Zhang,* and Lian-Mao Peng* Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China *

To whom correspondence should be addressed. [email protected]; (L.M.P.) [email protected].

E-mail:

(Z.Y.Z.)

†These authors contributed equally to this work

ABSTRACT: Although chemical vapor deposition (CVD)-grown carbon nanotube (CNT) arrays are considered ideal materials for constructing high-performance field-effect transistors (FETs) and integrated circuits (ICs), a significant gap remains between the required and achieved densities and purities of CNT arrays. Here, we develop a directional shrinking transfer method to realize up to 10-fold density amplification of CNT array films without introducing detectable damage or defects. In addition, the method improves the film uniformity while retaining the perfect alignment and high carrier mobility of 1,600 cm2V-1s-1 of CVD-grown CNT arrays. By combining the density amplification method with the thermocapillary flow method developed by Rogers et al., semiconducting CNT arrays with high densities and high qualities are obtained. High-performance FETs with a channel length of 200 nm are demonstrated using these high-density semiconducting CNT arrays, yielding a record-high on-state current density of 150 µA/µm, a peak transconductance of 80 µS/µm, and a current on/off ratio of more than 104 among the CVD-grown CNT-based FETs.

KEYWORDS: carbon nanotubes, field-effect transistor, chemical vapor deposition, well-aligned CNT array, shrinking transfer method

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Semiconducting single-walled carbon nanotubes (s-SWCNTs) have been widely used as potential building blocks for various applications in electronics,1-8 optoelectronics,9,10 sensors and others.11-13 However, the large-scale fabrication of high-performance carbon nanotube (CNT)-based devices remains difficult, largely due to the lack of high-quality CNT materials suitable for high-performance devices and integrated circuits (ICs).7 Well-aligned semiconducting CNT arrays with high densities are generally considered the ideal material system for CNT electronics, especially for high-speed and low-power ICs.7, 14 While impressive progress has been made in achieving CNT arrays with a high density or a high semiconducting purity, the simultaneous realization of both properties remains challenging.15-25 Two kinds of CNTs have been widely used in the fabrication of high-performance CNT field-effect transistors (FETs) and ICs, i.e., solution-processed CNTs15-17 and carbon vapor deposition (CVD)-grown CNT arrays.18-25 Recently, significant progress has been made toward the development of purification techniques for CNT materials, and CNT solutions with up to 99.99% high-purity semiconducting CNTs have been realized.15, 26-30

Although various methods have been developed to form aligned arrays based on

solution-processed CNTs, the resulting arrays are chemically modified and have a short length (typical mean length of 1 µm) and a poor large-scale uniformity and alignment.15-17, 31 Compared with solution-processed CNTs, CVD-grown CNTs can provide ultra-long, chemically clean and perfectly aligned CNT arrays with a high carrier mobility. In principle, this form of CNTs is highly desirable for the construction of large-scale ICs.4-7, 32-35 Impressive progress has also been made toward achieving high-density aligned CNT arrays through the CVD method, and in some favorable cases, the chirality-specific growth of CNT arrays has been realized.21-25 However, obtaining pure semiconducting CNT arrays remains a challenge, and post-processing is necessary to remove the residual metallic CNTs (m-CNTs). Rogers et al. developed a promising approach for removing m-CNTs from aligned arrays grown on quartz substrates by using nanoscale thermocapillary flows in thin-film organic coatings followed by reactive ion etching to obtain pure semiconducting CNT arrays (99.9925%) without substantially damaging the CNTs in the arrays.36-39 ACS Paragon Plus Environment

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However, the density of the CNT arrays processed by this approach is limited to less than 3 CNTs/µm by the trench width (~350 nm) formed on the organic coating above the m-CNTs, and this density is far below the ultimate density (100-200 tubes/µm) of semiconducting CNT arrays required for high-performance IC applications.36-38 In addition, the removal of m-CNTs decreases the density uniformity of the CNT array. Therefore, the method must be improved before it can be practically used. A multiple transfer method has been developed to achieve CNT arrays with a high density; however, the complicated process leads to excessive costs, large variations and, ultimately, low device performance.40, 41 In this work, we demonstrate a promising method for achieving high-density and semiconducting CNT arrays of high quality. Specifically, we developed a directional shrinking transfer method to realize density amplification in CNT array films without introducing detectable damage or defects. Furthermore, we combined the density amplification method with the method for removing m-CNTs based on thermocapillary flows to amplify the density of the pure semiconducting CNT arrays after removing the m-CNTs, providing an ideal material for high-performance CNT-based nanoelectronics.

RESULTS AND DISCUSSION The schematic diagram shown in Figure 1a demonstrates the main processes in the density amplification method for CNT arrays. The key steps of the method are the transfer of a CNT array film to a stretched elastic film, shrinkage of the elastic film, and transfer of the array to another substrate. The elastic film can be made of rubber, polyester, shape memory alloy, or organic or inorganic stretchable materials. Here, we adopt a factory-made polydimethylsiloxane (PDMS) film that can be stretched by up to 10 times its original length. First, a CNT array film, which can be either an original CVD-grown CNT array film or a pure semiconducting CNT array film with the m-CNTs removed,23-25 is prepared and peeled off of the original substrate by using a polymethylmethacrylate (PMMA) film as the carrier. Second, a PDMS film is stretched by a custom-made machine (see Supporting Information, Figure S1), and the ACS Paragon Plus Environment

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peeled CNT/PMMA film is adhered to the stretched PDMS film while keeping the CNT array perpendicular to the stretched direction of the PDMS film. The stretching ratio N of the PDMS film directly determines the density magnification of the CNT arrays. Third, the stretched PDMS film supporting the CNTs/PMMA is released, leading to a reduction in the inter-CNT spacing and an increase in the CNT array density. Finally, the shrunken CNT array is transferred from the stretchable film to a target substrate using a chemical or mechanical method. Density amplification of the CNT array is thus realized. The carrying film for transferring the CNT array is a crucial element in this method, as it is used not only as a medium for transferring the CNTs from the substrate to the PDMS film but also to synchronously condense the CNT array with the PDMS film during the shrinking process. Here, we use PMMA as the carrying film for the following reasons: (1) PMMA can form a uniform ultra-thin layer through spin coating to attach to every CNT in the array. (2) PMMA can liquefy during the shrinking process at temperatures above its glass transition temperature (105°C), and the liquid PMMA can fill the ripples on the PDMS film and support the synchronous movement of the CNTs with the contraction of the retractable film, helping to maintain the orientation of the CNTs. (3) PMMA can protect the CNTs from contamination by the impurities released by PDMS and be easily removed. To quickly demonstrate the density amplification method, we first use as-grown CNT arrays without eliminating the m-CNTs from the arrays. Figures 1b and 1c show scanning electron microscopy (SEM) images of the CNT array before and after density amplification with N=10, i.e., the PDMS film is stretched by a ratio of 10. After the density amplification process, the CNT array film exhibits a higher density of 60-80 tubes/µm, which is nearly 10 times the original density of 6-8 tubes/µm. Furthermore, the CNT array maintains perfect alignment on a large scale of 2.4×20 mm. Although multiple transfer methods could also achieve a density increase in CNT arrays,40, 41 N completed transfer processes are required to realize an N-fold density amplification of the CNT arrays. Thus, compared with the multiple transfer method, our density amplification method exhibits a much higher efficiency. The main ACS Paragon Plus Environment

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drawback of our method is that the effective active area decreases by N times, and the sample size also decreases by N times. However, we can prepare CNT arrays on a larger substrate by utilizing a larger CVD furnace. The density magnification of CNT arrays is tunable via control of the stretching ratio, N, of the PDMS film, as shown in Figures 2a-2d. Based on the original CNT array with a density of 4-5 tubes/µm, we subjected CNT array films with similar original densities to shrinking processes with N=2, 3, and 4. Figure 2e demonstrates a perfect relationship between the CNT array density and the amplification ratio N (right axis). To further quantify the electrical properties of the CNT arrays, we fabricated 40 back-gate FETs on each type of CNT array and found that the average on-state current (Ion) is directly proportional to N (Figure 2e, left axis), implying no noticeable CNT loss or introduction of impurities. In addition, the Raman spectra of the processed CNT arrays in Figure 2f show only a very weak defect peak, suggesting that this approach causes no obvious damage to the CNTs. In addition to a high density, a large-scale uniformity of the density is also important for high-performance IC applications. Variations in the CNT array density in the channels of FETs can lead to variations in Ion, resulting in reduced yields, increased delay variations, and degraded noise margins in large-scale ICs. Figures 3a and 3b compare SEM images of four random positions in the same CNT array sample before and after density amplification with N=5. The CNT arrays after density amplification appear to have smaller density variations than the original CVD-grown CNT arrays. To quantify the uniformity of the CNT array prepared by this approach, we calculated the normalized standard deviation (σ) of the CNT array density (tubes per unit length) distribution. A MATLAB program was designed to automatically recognize and count the CNTs in the SEM images (see Supporting Information, Figure S2). Figure 3c illustrates the σ values of the CNT array density, showing that the density decreases with increasing density amplification ratio, suggesting a significant improvement in the density uniformity of the array after density amplification. The on-state conductance (Gon, Ids/Vds under low Vds) of the FETs based on the CNT arrays was evaluated to further quantify the variations in the CNT FETs. ACS Paragon Plus Environment

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Figures 3d and 3e show the statistical distributions of Gon for back-gate FETs fabricated on the as-grown CNT array and the five-fold shrunken CNT array, respectively. After density amplification, the Gon distribution improved from 4.19±1.19 mS to 22.46±0.73 mS, indicating that both the density and uniformity are significantly improved through the density amplification method. We conclude that the density amplification method can effectively improve the density uniformity of CNT arrays, which is beneficial for the fabrication of highly uniform FETs and thus ICs. A polar plot of the Raman G-peak intensities of the shrunken CNT arrays is given in Figure 3f, showing that the shrunken CNT arrays maintain excellent directionality. In fact, according to the simulation results, we found that the shrinking process can maintain the alignment of the CNT array on the stretched PDMS in the central region (Figure 3g). The deformation of the five-times-stretched PDMS was simulated with COMSOL software (using the St Venant-Kirchhoff model and silicone as the material). Although the grids at the edges are disordered, those in the central region retain their original shape. If we use only the central portion of a large PDMS film, as demonstrated in our experiments, it is possible to maintain the perfect alignment of the CVD-grown CNT arrays. One very important advantage of our density amplification method is that the method is compatible with the methods generally used to remove m-CNTs. High-density and pure semiconducting CNT arrays can thus be obtained by combining one m-CNT removal method with our density amplification method. Here, we removed the m-CNTs from CVD-grown CNT arrays through the thermocapillary flow method.36-39 After the purification process, a pure semiconducting CNT array with a device current on/off ratio (Ion/Ioff) of up to 104 was obtained, but this as-grown CVD CNT array had a very low array density of approximately 1 CNT/µm (see Supporting Information, Figure S3). The purified CNT array sample was further processed by the shrinking method to realize density amplification. The overall process is shown in Figure S4 in the Supporting Information. Self-aligned top-gate FETs (Figures 4a and 4b) were fabricated on semiconducting CNT arrays ACS Paragon Plus Environment

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with/without density amplification (N=5, 10) to assess the electrical properties of these two types of CNT arrays.35 To assess the quality of the CNT arrays after undergoing all the processes, the carrier mobility of the shrunken CNT arrays with an average diameter of ~1.31 nm (see Supporting Information, Figure S5) was extracted based on the FETs, as shown in Figure 4c. The extracted carrier mobility distribution is approximately 1591.8±133.6 cm2/vs, which is comparable to that of the as-grown CNTs with a similar diameter.19,42 The increased density plus the largely maintained high quality (mobility) of the semiconducting CNT arrays lead to a significant improvement in the device performance. Figure 4d statistically compares the peak transconductance (Gm) values of top-gate FETs based on as-prepared semiconducting CNT arrays and on CNT arrays after density amplification with N=5, showing a significant performance improvement for the latter devices, with a 4.9-fold improvement in Gm after amplifying the density of the CNT arrays. We then used pure semiconducting CNT arrays with a density of 10 tubes/µm after 10-fold amplification to fabricate FETs. As the transfer and output curves of a typical device show (Figures 4e and 4f), the FETs based on the high-density CNT arrays exhibit a nearly 10-fold performance improvement over those based on the original CNT array without density amplification (see Supporting Information, Figure S6). As a result, Ion and Gm reach maximum values of 150 µA/µm and 80 µS/um, respectively, which are the highest values obtained for CVD-derived semiconducting CNT arrays (Figure 4g).19,24-25,37,41,43-45 Meanwhile, the Ion of each CNT is as high as 15 µA/tube, indicating that the quality of the CNTs is very high.19, 21-25 The shrunken CNT arrays maintained a high semiconducting purity, as indicated by the large Ion/Ioff of up to 104. We thus demonstrated that high-quality aligned CNT arrays with pure semiconducting CNTs and high density can be obtained by the method discussed in this work, and this method will in turn promote the development of high-performance CNT-based electronics.

CONCLUSIONS In summary, we developed a directional shrinking transfer technique for realizing ACS Paragon Plus Environment

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density amplification in CNT array films without introducing detectable damage or defects in the CNTs. The density amplification method is compatible with the methods for removing m-CNTs, e.g., those based on thermocapillary flows, and can thus be used to amplify the CNT array purity after removing m-CNTs. By combining the density amplification method with the thermocapillary flow method, pure semiconducting CNT arrays with a high density and high quality are obtained, which further promotes the fabrication of high-performance CNT FETs. The FETs based on the obtained high-density and pure semiconducting CNT arrays exhibit the highest performance among CVD-grown CNT-based FETs reported to date, including an Ion of 150 µA/µm, a Gm of 80 µS/µm, and a Ion/Ioff of up to 104.

METHODS Growth of CNT arrays. Well-aligned CNT arrays were grown on quartz substrates. ST-cut (Hoffman Inc.) quartz wafers were annealed at 900°C for 9 hours to improve the crystallinity. Standard UV photolithography was performed to pattern catalyst stripes with a width of 5 µm and a spacing of 250 µm. The catalyst stripes were patterned perpendicular to the X axis of the quartz surface according to the requirement described in the previous report.32 Then, an iron film with a thickness of approximately 0.1 nm was deposited as a catalyst for CNT growth using an electron beam evaporator, followed by a lift-off process. CNT growth was performed in a horizontal CVD furnace. The prepared substrate with patterned catalyst was annealed at 800°C for 1 h to remove the polymer residue remaining from the photolithography process. After cooling to room temperature, the furnace was again heated to 800°C in 30 min under the protection of Ar (500 sccm) before CNT growth. In a typical CVD growth process of CNTs, H2/Ar (50 sccm/50 sccm) was used to reduce the catalyst for 10 min at 800°C. Subsequently, an Ar flow of ∼50 sccm through an ethanol bubbler and a hydrogen flow of ∼50 sccm were introduced into the CVD furnace for 23 min for CNT growth. Then, the system was cooled to room temperature in an Ar atmosphere to finish the growth process. Purification of CNT arrays by the thermocapillary method. CNT arrays were ACS Paragon Plus Environment

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transferred to a SiO2/Si substrate, which exhibits better thermal conductivity than quartz. A Ti/Au (10 nm/50 nm) stacked film was deposited and patterned as electrodes for CNT FETs with a 10 µm channel length. The Ti film can provide a Schottky contact for semiconducting CNTs and an ohmic contact for m-CNTs. Therefore, the current in a semiconducting CNT is much smaller than that in an m-CNT when the same voltage is supplied. Then, thermocapillary resist a,a,a’-tris(4-hydroxyphenyl) -1-ethyl-4-isopropylbenzene (TPPA) with a thickness of 25 nm was deposited on the CNT film through thermal evaporation. The sample was heated to 85°C in a probe station under a vacuum of 10 mPa to make TPPA flow easily, and a constant voltage of 13 V was applied to the electrodes for 5 minutes to form trenches on the m-CNTs. Oxygen plasma generated by inductively coupled plasma (ICP) was then used to etch the exposed m-CNTs. Finally, the sample was successively immersed in acetone, gold etchant and HF buffer to remove the TPPA residue, Au film and Ti film. Directional film shrinking technique. The quartz substrate with the CVD-grown CNT array film was spin-coated with a PMMA film and then dipped into an HF buffer solution to etch the SiO2 (see Supporting Information, Figure S1b). After natural separation of the quartz substrate, the PMMA (attached to the CNT film) was further immersed in deionized water for 30 minutes to remove residual HF. Then, the clean PMMA-CNT composite film was attached to a PDMS film, which was stretched in one direction by a homemade machine (see Supporting Information, Figure S1a). Note that the side of the PMMA film without CNTs must be placed on the PDMS film, and the axial direction of the CNTs must be perpendicular to the stretching direction of the PDMS film. Then, the PDMS film was slowly released to its natural length with a slow velocity of 0.1 mm/s at a background temperature of 105°C or higher. The PMMA-PDMS film with the density-amplified CNT array film was stacked tightly on a Si/SiO2 substrate at 170°C on a hotplate with the CNT side toward the substrate, and then, the PDMS film was slowly peeled off of the PMMA film and substrate. Finally, the substrate was immersed in acetone to dissolve the PMMA and dried by nitrogen. Fabrication of CNT array FETs. First, an electron beam lithography (EBL) process followed by oxygen plasma etching defined the channel region. Then, the source and ACS Paragon Plus Environment

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drain contacts were patterned via EBL followed by evaporating a 0.3 nm/80 nm Ti/Pd film and a standard lift-off process. Subsequently, the gate window was patterned via EBL, and a 10-nm-thick HfO2 film was grown via atomic layer deposition (ALD) at 90°C, followed by electron beam evaporation (EBE) deposition of a 15 nm Pd film and a standard lift-off process. Finally, a Ti/Au film with a thickness of 20 nm/100 nm was formed as the pads for the electrical measurements. ASSOCIATED CONTENT The authors declare no competing financial interest. Supporting Information The Supporting Information is available free of charge on the ACS Publications website at DOI: Additional discussions are provided about the (1) Design of shrinking machine, (2) Purification of CNT arrays, (3) CNT image recognition program, (4) Entire process for removing m-CNTs and performing density amplification and (5) Electrical properties of top-gated FETs fabricated on non-amplified CNT arrays. (PDF)

AUTHOR INFORMATION Corresponding Authors *E-mail: (Z.Y.Z.) [email protected] *E-mail: (L.M.P.) [email protected] ORCID Zhiyong Zhang: https://orcid.org/0000-0003-1622-3447 Author Contributions Z.Z. and L.M.P. proposed and supervised the project. J.S. and H.X. performed the density amplification of the CNT films. D.Z. performed the removal of m-CNTs through the thermocapillary flow method. M.X. grew the CVD-based CNTs. C.Y. performed the simulation of the PDMS stretching. J.S., D.Z. and H.X. fabricated and

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measured the FETs. J.S, D.Z., Z.Z. and L.M.P. analyzed the data and co-wrote the manuscript. All authors discussed the results and commented on the manuscript. ACKNOWLEDGMENT This work was supported by the National Key Research & Development Program (Grant Nos. 2016YFA0201901 and 2016YFA0201902), the National Science Foundation of China (Grant Nos. 61376126, 61621061 and 61427901), and the Beijing

Municipal

Science

and

Technology

Commission

D161100002616001-3).

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and

Aligned

Single-Walled

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Nanotubes

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Multiple-Cycle Growth Methods. ACS Nano 2011, 5, 3849–3857. (24) Ding, L.; Tselev, A.; Wang, J.; Yuan, D.; Chu, H.; Mcnicholas, T. P.; Li, Y.; Liu, J. Selective Growth of Well-Aligned Semiconducting Single-Walled Carbon Nanotubes. Nano Lett. 2009, 9, 800–805. (25) Zhang, S.; Kang, L.; Wang, X.; Tong, L.; Yang, L.; Wang, Z.; Qi, K.; Deng, S.; Li, Q.; Bai, X.; Ding, F.; Zhang, J. Arrays of Horizontal Carbon Nanotubes of Controlled Chirality Grown Using Designed Catalysts. Nature 2017, 543, 234– 238 (26) Chen, B.; Zhang, P.; Ding, L.; Han, J.; Qiu, S.; Li, Q.; Zhang, Z.; Peng, L.-M. Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits. Nano Lett. 2016, 16, 5120–5128. (27) Yang, Y.; Ding, L.; Han, J.; Zhang, Z.; Peng, L.-M. High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films. ACS Nano 2017, 11, 4124–4132. (28) Brady, G. J.; Joo, Y.; Wu, M.-Y.; Shea, M. J.; Gopalan, P.; Arnold, M. S. Polyfluorene-Sorted, Carbon Nanotube Array Field-Effect Transistors with Increased Current Density and High On/Off Ratio. ACS Nano 2014, 8, 11614– 11621. (29) Geier, M. L.; McMorrow, J. J.; Xu, W.; Zhu, J.; Kim, C. H.; Marks, T. J.; Hersam,

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Complementary Static Random Access Memory. Nat. Nanotechnol. 2015, 10, 944–948. (30) Kane, A. A.; Ford, A. C.; Nissen, A.; Krafcik, K. L.; Léonard, F. Etching of Surfactant from Solution-Processed, Type-Separated Carbon Nanotubes and Impact on Device Behavior. ACS Nano 2014, 8, 2477–2485. (31) He, X.; Gao, W.; Xie, L.; Li, B.; Zhang, Q.; Lei, S.; Robinson, J. M.; Hároz, E. H.; Doorn, S. K.; Wang, W.; Vajtai, R.; Ajayan, P. M.; Adams, W. W.; Hauge, R. H.; Kono, J. Wafer-Scale Monodomain Films of Spontaneously Aligned Single-Walled Carbon Nanotubes. Nat. Nanotechnol. 2016, 11, 633–638. (32) Xiao, J.; Dunham, S.; Liu, P.; Zhang, Y.; Kocabas, C.; Moh, L.; Huang, Y.; Hwang, K.-C.; Lu, C.; Huang, W.; Rogers, J. A. Alignment Controlled Growth of Single-Walled Carbon Nanotubes on Quartz Substrates. Nano Lett. 2009, 9, 4311–4319. (33) Dürkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39. (34) Zhang, Z.; Liang, X.; Wang, S.; Yao, K.; Hu, Y.; Zhu, Y.; Chen, Q.; Zhou, W.; Li, Y.; Yao, Y.; Zhang, J.; Peng, L.-M. Doping-Free Fabrication of Carbon Nanotube Based Ballistic CMOS Devices and Circuits. Nano Lett. 2007, 7, 3603–3607. (35) Zhang, Z.; Wang, S.; Ding, L.; Liang, X.; Pei, T.; Shen, J.; Xu, H.; Chen, Q.; Cui, R.; Li, Y.; Peng, L.-M. Self-Aligned Ballistic n-Type Single-Walled Carbon Nanotube Field-Effect Transistors with Adjustable Threshold Voltage. Nano Lett. 2008, 8, 3696–3701. (36) Du, F.; Felts, J. R.; Xie, X.; Song, J.; Li, Y.; Rosenberger, M. R.; Islam, A. E.; Jin, S. H.; Dunham, S. N.; Zhang, C.; Wilson, W. L.; Huang, Y.; King, W. P.; Rogers, J. A. Laser-Induced Nanoscale Thermocapillary Flow for Purification of Aligned Arrays of Single-Walled Carbon Nanotubes. ACS Nano 2014, 8, 12641–12649. (37) Jin, S. H.; Dunham, S. N.; Song, J.; Xie, X.; Kim, J.; Lu, C.; Islam, A.; Du, F.; Kim, J.; Felts, J.; Li, Y.; Xiong, F.; Wahab, M. A.; Menon, M.; Cho, E.; Grosse, ACS Paragon Plus Environment

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(45) Franklin, A. D.; Chen, Z. Length Scaling of Carbon Nanotube Transistors. Nat. Nanotechnol. 2010, 5, 858–862.

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Figure 1. Density amplification method for CNT arrays. (a) Flow chart showing the major steps of the density amplification method. First, a CNT array film is prepared and peeled off of the original substrate by using a PMMA film as the carrier. Second, the CNT/PMMA is adhered to a stretched PDMS film. Third, the PDMS film is slowly released to its original length. Finally, the CNT/PMMA/PDMS film is transferred to a target substrate. (b) SEM image of a CVD-grown CNT array before density amplification with a density of 6-8 tubes/µm. (c) SEM images of a CNT array after density amplification with N=10. The entire area is 2.4 mm×20 mm, and the average density increased to 6-8 CNTs/100 nm.

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Figure 4. Top-gate FETs based on semiconducting CNT arrays before and after density amplification. (a) Schematic illustration of a top-gate self-aligned FET and (b) the corresponding SEM image of a typical as-fabricated FET. The scale bar represents 500 nm. (c) Histogram of the field-effect mobility extracted from 15 FETs based on density-amplified CNT arrays. (d) Gm

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statistics of 7 FETs based on semiconducting CNT arrays and 7 FETs based on five-fold density-amplified CNT arrays under Vds=-0.1 V. (e) Transfer characteristics (blue line, left axis and insert) and Gm (red dots, right axis) measured from an FET based on density-amplified CNT arrays with a density of 10 tubes/µm and channel length L=200 nm. Ion/Ioff is 104. (f) Output characteristics of the same device as in (e) under Vgs from 0 V to -3 V with a 0.5 V voltage step. Ion and Gm increased by approximately 10-fold through the density amplification method (compared to Figure S6). (g) Gm per width versus Ion/Ioff for some representative CVD-derived CNT array-based FETs.

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