Self-Terminating Confinement Approach for Large-Area Uniform

Self-Terminating Confinement Approach for Large-Area Uniform Monolayer Graphene Directly over Si/SiOx by Chemical Vapor Deposition Jinbo Pang,§ Rafael G. Mendes,†,‡,§ Pawel S. Wrobel,⊥ Michal D. Wlodarski,⊥ Huy Quang Ta,§,⊥ Liang Zhao,†,‡ Lars Giebeler,§ Barbara Trzebicka,⊥ Thomas Gemming,§ Lei Fu,∥ Zhongfan Liu,†,‡,□ Juergen Eckert,#,¶ Alicja Bachmatiuk,*,†,‡,§,⊥ and Mark H. Rümmeli*,†,‡,§,⊥ †

College of Physics, Optoelectronics and Energy & Collaborative Innovation Center of Suzhou Nano Science and Technology, and Key Laboratory of Advanced Carbon Materials and Wearable Energy Technologies of Jiangsu Province, Soochow University, Suzhou, 215006, China § IFW-Dresden, Helmholtz Strasse 20, D-01171 Dresden, Germany ⊥ Centre of Polymer and Carbon Materials, Polish Academy of Sciences, ul. M. Curie-Sklodowskiej 34, Zabrze, PL-41-819 Zabrze, Poland ∥ College of Chemistry and Molecular Science, Wuhan University, Wuhan, 430072, China □ Center for Nanochemistry (CNC), Beijing Science and Engineering Center for Nanocarbons, College of Chemistry and Molecular Engineering, Peking University, Beijing 100871, China # Erich Schmid Institute of Materials Science, Austrian Academy of Sciences, Jahnstraße 12, A-8700 Leoben, Austria ¶ Department Materials Physics, Montanuniversität Leoben, Jahnstraße 12, A-8700 Leoben, Austria ‡

S Supporting Information *

ABSTRACT: To synthesize graphene by chemical vapor deposition (CVD) both in large area and with uniform layer number directly over Si/SiOx has proven challenging. The use of catalytically active metal substrates, in particular Cu, has shown far greater success and therefore is popular. That said, for electronics applications it requires a transfer procedure, which tends to damage and contaminate the graphene. Thus, the direct fabrication of uniform graphene on Si/SiOx remains attractive. Here we show a facile confinement CVD approach in which we simply “sandwich” two Si wafers with their oxide faces in contact to form uniform monolayer graphene. A thorough examination of the material reveals it comprises faceted grains despite initially nucleating as round islands. Upon clustering, they facet to minimize their energy. This behavior leads to faceting in polygons, as the system aims to ideally form hexagons, the lowest energy form, much like the hexagonal cells in a beehive, which requires the minimum wax. This process also leads to a near minimal total grain boundary length per unit area. This fact, along with the high graphene quality, is reflected in its electrical performance, which is highly comparable with graphene formed over other substrates, including Cu. In addition, the graphene growth is self-terminating. Our CVD approach is easily scalable and will make graphene formation directly on Si wafers competitive against that from metal substrates, which suffer from transfer. Moreover, this CVD route should be applicable for the direct synthesis of other 2D materials and their van der Waals heterostructures. KEYWORDS: direct monolayer graphene growth, uniform graphene, chemical vapor deposition, silicon, grain boundaries, optical transmission, carrier mobility

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t is well over a decade now since Andre Geim and Konstantin Novoselov first isolated graphene and began revealing a whole myriad of graphene’s exciting physical properties.1 Those studies and subsequent studies by others continue to demonstrate great promise in numerous fields such © 2017 American Chemical Society

Received: December 2, 2016 Accepted: January 24, 2017 Published: January 24, 2017 1946

DOI: 10.1021/acsnano.6b08069 ACS Nano 2017, 11, 1946−1956

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surprising given that the direct graphene fabrication over Si/ SiOx is highly desirable due to the potential lower cost, compatibility with current Si-based technology, and better process control.49 In this work we revisit the direct fabrication of graphene over Si/SiOx. We borrow ideas originally developed for uniform graphene fabrication over Cu, in which confinement of the substrate is implemented.50,51 We compare the synthesis of graphene directly on Si/SiOx both without and with confinement and demonstrate that large-area uniform monolayer graphene directly over Si/SiOx is feasible. Indeed, our approach is remarkably simple and involves simply sandwiching two Si/ SiOx wafers together (which in essence produces a uniform single-layer graphene film at each surface). The resultant graphene when characterized is shown to have faceted grain boundaries in the form of polygons despite nucleating in the form of disks. This faceting process occurs as the system aims to minimize its energy and moves toward the ideal case of forming hexagonal polygons, much like a beehive forming hexagonal cells to minimize wax use. In this way, the grain boundary periphery is minimized, and as such, the optical and electric performance is highly competitive when compared to monolayer graphene produced over metals and other substrates. The work may be suitable for large-area uniform graphene production directly over Si wafers. Initially, we adopt three Si/SiOx (300 nm oxide) substrate configurations, the schematics of which are presented in Figure 1. The three configurations from left to right are Si/SiOx with

as electronics, coatings, composites, and biomedical applications.2−7 Of core importance to realize graphene’s success commercially is its production. Large films and small sheets of graphene are the two major forms of graphene used for various applications.8−11 In terms of large-area graphene, which holds promise for future electronics,7,12−15 e.g., field effect transistors (FET), touch panels, displays, and photovoltaic devices, there are numerous efforts to achieve uniform monolayer and fewlayer graphene in a controlled manner. In the microelectronics industry there is hope that large-area graphene may offer solutions beyond just complex devices16 and transparent electrodes7 but also as efficient electrical interconnects in large-scale integrated circuits.17 In the pursuit of the above, for large-area graphene fabrication, the vast body of work has been dedicated to the fabrication of large-area graphene over metals using chemical vapor deposition (CVD), mostly using Cu or Ni as catalytic substrates.18−22 Cu, with its low carbon solubility, makes achieving uniform monolayer and bilayer graphene more likely as compared to Ni.18,23 Roll-to-roll fabrication of graphene over Cu has also been achieved.24 However, to use such graphene within microelectronic applications where the devices are built on dielectric substrates (mostly Si/SiOx wafers), the as-produced graphene requires postsynthesis transfer of the graphene onto a dielectric substrate. This procedure leads to undesired damage and processing contamination of the transferred graphene.25−28 To this end, a relatively large body of work has looked at the thermal decomposition of SiC surfaces to yield graphene.29 While the quality of the obtained graphene is good, it is near impossible to achieve this in a large area and with a uniform layer number.30−32 Other dielectric substrates have also been explored, such as quartz, sapphire, SrTiO3, Si3N4, and borosilicate glass.33−37 Indeed, recent developments of direct graphene growth over glass are remarkable.38 Of course, given that Si/SiOx technology is so successful and very well established, it makes sense that graphene be formed on Si wafer material in a more direct manner. There are two approaches to achieve this. The first we term pseudodirect, and this includes techniques in which a metal catalyst upstream helps decompose the carbon feedstock, enabling graphene to form on a Si/SiOx substrate downstream.39−41 Alternatively, one can form a thin metallic film on a Si/SiOx substrate that evaporates away during the synthesis process.42 The use of liquid metal films (which also evaporate away) on Si/SiOx for uniform graphene formation has been particularly successful.43,44 The second approach is to fabricate synthetic graphene directly on Si/SiOx. The team from Yunqi Liu completed a variety of pioneering works showing large graphene grain formation on Si/SiOx.35 They and others went on to develop film coverage over Si/SiOx.45−48 However, homogeneous and uniform graphene layers for large-area coverage directly over Si/SiOx has remained a challenge. Moreover, the challenges facing homogeneous and uniform graphene coverage over Si/SiOx have led to the direct CVD synthesis of graphene over Si wafers being largely ignored in favor of the far easier and more developed approaches, namely, CVD fabrication over Cu and SiC decomposition. This fact is easily seen in Figure S1 in the Supporting Information, in which published articles from the different synthesis approaches are presented in a bar chart. Clearly CVD-grown graphene dominates, and the number of publications on this theme is several orders of magnitude larger than that for the direct fabrication of graphene over Si/SiOx. The difference is

Figure 1. Schematic illustrating the substrate configurations explored for the direct synthesis of graphene over Si/SiOx using thermal CVD. (a) SiOx facing up, (b) SiOx facing down, and (c) a sandwiched Si/SiOx−SiOx/Si configuration. The oxide layer is the desired substrate surface for graphene growth. The substrate is commercially available Si wafer with a polished thermally grown oxide (layer thickness ∼300 nm). The supporting plate is sintered alumina.

the oxide facing up (exposed), Si/SiOx with the oxide facing down on a sintered alumina support, and two Si/SiOx wafers with their oxide faces sandwiched together.

RESULTS After individually subjecting these different configurations to an atmospheric thermal CVD reaction for nominal periods of time, the samples were cooled and then initially examined using scanning electron microscopy (SEM) and Raman spectroscopy. The data show full coverage on the oxide face after 4 to 5 h. This preparation features a short time frame when compared against full film coverage in other works (6−8 h).34,48 Figure 2 presents representative data from the samples after a reaction time of 5 h in which the substrates are fully covered by a graphene film. Clear differences between the different 1947


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Figure 2. Characterization of the synthetic graphene for the three substrate configurations explored for the direct growth of graphene over Si/ SiOx. (a, b, c) SEM micrographs of the postsynthesis sample surfaces. (d, e, f) Raman spectral mapping of the full width at half-maximum of the 2D band. The units for the color scale bar are cm−1. (g, h, i) Raman spectra showing representative G, 2D, and D bands for the graphene samples.

RMS) of 0.18 ± 0.02 nm. In contrast, the alumina has a surface RMS roughness of 101 ± 8 nm, which is more than 500 times that of the polished SiOx surface. This observation means that the confined space in the sandwiched SiOx/SiOx interface is significantly less than that found at the SiOx/alumina interface (Figure S3k,l). In addition we conducted detailed quantitative approximation approaches to further study the space between the substrate interface (see discussion sections relating to Figure S3 in the Supporting Information). The calculations show a gap of ca. 1.4 nm, which is at least 3 times more than that of the predicted gas reaction species (see Table S1). In short, the space between the two polished SiOx faces confines or restricts the diffusion of feedstock species to the SiOx surface, where graphene forms, although it is still large enough for their steady flow through the interface region so as to enable homogeneous monolayer graphene. Previous reports in which synthetic graphene was fabricated by CVD over Cu have also shown that restricting the feedstock supply through space confinement in essence controls the C supply rate and can favor homogeneous single-layer graphene formation.50,54 To some degree this behavior can also be achieved by limiting the CH4/H2 ratio and flow.51,55 In essence, in this work, confining the space or gap between the sandwiched Si/SiOx substrate helps limit the carbon supply and reduces the nucleation density. In the case of the substrate lying face down on the alumina base (Figure 1b) the gap is limited because of the rather large roughness of the alumina surface, while for a Si/ SiOx face down on another polished SiOx surface (Figure 1c) the gap is significantly lower and so the C supply is sufficiently

substrate configurations are observed. For the upward facing oxide surface from the substrate (Figure 1a) one sees full or near full coverage of graphene and numerous randomly located secondary and ternary layers. The secondary layers show up as dark contrast spots in the SEM micrographs, while Raman maps of the full width at half-maximum (fwhm) of the 2D peak, which is used to differentiate between monolayer graphene and few-layer graphene,52,53 confirm the inhomogeneity in layer numbers. Local Raman spectroscopy on the clear patches of the as-produced film indicate monolayer graphene. A similar outcome is observed for the samples in which the oxide layer lies face down on a (polycrystalline) alumina base (Figure 1b). However, both the SEM data and the Raman data indicate fewer secondary layers as opposed to the face-up case. For the samples in which two Si/SiOx substrates have their oxide faces sandwiched together the graphene layer showed homogeneous monolayer large-area graphene (see Figure S2 in the Supporting Information); namely, secondary layer formation is avoided. Moreover, the Raman spectroscopy data showed a 2D/G ratio of 2, indicating that the as-grown film of strictly monolayer graphene directly formed on a Si/SiOx substrate is of high quality. These data are presented in Figure 2. To gain insight into why there is such a large difference between the face-down sample on an alumina base and the sandwich (SiOx/SiOx) samples (Figure 1c), we conducted atomic force microscopy (AFM) topography investigations of the Si/SiOx faces as well as the Al2O3 support base surface (Figure S3a,b). The statistical AFM height data (Figure S3c,d) show the SiOx surface has a roughness (root-mean-square, 1948


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Figure 3. Time-dependent growth evolution of the graphene from individual domains, with adjacent grains merging to form a continuous monolayer graphene for the sandwich configuration. (a, b, c, d) SEM micrographs for the time-dependent graphene formation. (e, f, g, h) AFM height images of the corresponding samples. (i, j, k, l) Representative Raman spectra for the samples with reducing D band as full monolayer coverage is achieved.

(∼2700 cm−1) mode locations, relative intensities, and 2D fwhm (single Lorentzian fit of 34 cm−1).50,59 The D mode (∼1350 cm−1) intensity relative to the G mode decreases with increasing growth time. The D mode is associated with defects. Open graphene edges are also defects that increase the D mode.60 Hence, in this case as the number of free edges reduce as the individual grains grow and merge, so does the D mode, such that once full coverage is obtained only a minute D mode remains present. By forming a plot of individual grain sizes for low growth times and grain sizes of merging flakes for longer growth times we see how the grain size depends on temperature (Figure S4a). One can also determine the growth rate change with respect to the growth time (Figure S4b). The growth rate is seen to be approximately linear initially and then rapidly slows and stops. This is behavior attributed to the merging of the individual flakes and reduction in free edges as the film grows to eventually encompass the entire substrate surface. A comparison of grain size and growth rate in this work as compared with other reports is listed in Table S2. In the table, we can see that the initial growth rate of 375 nm/h found in this work is the highest among similar works for direct graphene synthesis over Si/SiOx substrates. Moreover, here we demonstrate a large-area homogeneous monolayer directly formed over Si/SiO x substrates using thermal CVD and, importantly, a sandwich or confinement technique. We also looked at the diameter of the individual disk-shaped islands during early growth and their temperature dependence (Figure S5). SEM evaluations show the graphene disk diameter increases with increasing temperature for a given reaction time (2 h). In addition, the density of the disks increases with increasing temperature, indicating an increase in nucleation rate with increasing temperature. From the data we prepared

reduced to favor single graphene layer formation and limit secondary layer formation. Hence, here we demonstrate that C species limitation by space confinement for homogeneous highgrade monolayer graphene can also be achieved with nonmetallic Si/SiOx substrates using a simple sandwich technique, which importantly overcomes what has been a challenge for the direct growth of large-area graphene growth over Si/SiOx, namely, homogeneous large-area graphene growth directly on Si/SiOx. Here we produce samples of 2 × 2 cm2 (Figure S2); however this size can easily be scaled up depending on the size of the CVD reactor. To understand the evolution of the graphene growth for the sandwich substrate configuration, we performed the CVD reaction with growth times from 1 to 5 h. Figure 3 shows typical data for time-dependent samples. After 1 h round graphene islands are randomly located on the substrate surface (Figure 3a). The average diameter of the flakes is 375 ± 30 nm. The formation of round islands is in keeping with previous work48 and occurs because the lowest energy atomic configuration at nucleating graphene island edges favors isodirectional (disk-like) growth for nonmetal substrates.56 With increasing growth time (2 h), the islands enlarge (mean diameter 670 ± 45 nm) and start to merge (Figure 3b). After 4 h a near complete film has formed with only a few small open patches remaining (Figure 3c), and after 5 h a full graphene film is obtained that is free of secondary layers. Similar data to those from SEM are found with the AFM studies. In addition, AFM allows us to measure the height of the islands and forming film at open edges. The heights are typically 0.80 ± 0.02 nm, which is concomitant with monolayer graphene over Si/SiO x substrates.57,58 Raman spectroscopy investigations confirm the presence of monolayer graphene through the G (∼1580 cm−1) and 2D 1949


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Figure 4. TEM characterizations of the large-area synthetic monolayer graphene (from sandwich configuration). (a) Low-magnification micrograph of a graphene film transferred onto a holey carbon TEM grid. (b) SAED pattern of the region circled in (a). The inset profile shows the intensity profile of the diffraction spots. (c, d) High-resolution TEM images showing the honeycomb atomic configuration of graphene. (e) False-color composite micrograph image highlighting the different domain (grain) orientations and faceted grain boundaries. Corresponding DF-TEM images showing how the composite image is formed are provided in the Supporting Information in Figure S7.

Figure 5. Faceted graphene film for sandwich substrate configuration with complementary microscopies (from top to bottom): AFM, SEM, and TEM. (a) AFM height image showing the facets of graphene domains, with black arrows indicating grain boundaries. (b) Outlining the grain boundaries. The height profile (c) across the black bar in (b) showing the local curvature with a height of 0.3 nm. (d) SEM graph of the graphene film showing darker contrast of the grain boundaries and (e) its outline and (f) the intensity profile across the black bar. (g) Falsecolor composited TEM image indicating the facets and rotational misorientations between two adjacent grains. (h, i) HRTEM graphs for the grain boundaries of 23° and 28°, respectively. The grain boundaries are stitched with carbon pentagon−heptagon pairs.

comparable with other works for the direct formation of graphene over dielectrics,61 and this value is much higher than found for graphene growth over Cu.63−65 The increasing growth rates of the graphene disks with respect to increasing

Arrhenius plots, from which we can derive the activation energies for the disk diameter and disk density (nucleation density).61,62 They are 7.2 ± 1.5 eV and 4.6 ± 0.6 eV, respectively. The activation for the grain/disk diameter is 1950


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in Figure 5g, in which the faceted grains are presented in false color along with their relative rotation angles. With HRTEM we are able to observe the grain boundaries at high magnification, and at this scale the boundaries do not appear straight but have a degree of curvature and form through pentagon−heptagon pairs, much as with graphene grain boundaries in general, as this arrangement exhibits the lowest energy configuration.76,77 The amplitude of the (in-plane) undulations in the grain boundaries ranges from 0.6 to 1.2 nm (see also Figure S11). A fuller analysis of the grain boundary heights and their relative rotation angles shows a correlation as presented in Figure S12 in the Supporting Information.

temperature are attributed to improved thermal decomposition of the feedstock at higher temperatures. This finding is supported by thermodynamics calculations, which show an increase in mole fraction for C with increasing temperature, as well as an increase for the two most prominent radicals, H* and CH3 (Figure S6). The thermodynamic calculations also confirm that thermal CH4 decomposition occurs at the growth temperatures used in this study; namely, decomposition can occur without a catalyst. We now turn to characterizing the large-area homogeneous single-layer graphene directly formed over Si/SiOx with the sandwich configuration using low-voltage (80 kV) Cs corrected high-resolution transmission electron microscopy (HRTEM), selected area electron diffraction (SAED), and dark-field transmission electron microscopy (DF-TEM). Figure 4a shows a low-magnification micrograph of a typical (transferred) graphene film covering over a holey carbon/Cu TEM grid. A representative SAED pattern from this region (Figure 4b) shows the 3-fold diffraction symmetry of the material, and the reflex spacings are indicative of crystalline graphene. The relative intensities of the reflex spots across the {11−20} and {10−10} directions confirm monolayer graphene.66,67 Highresolution micrographs (Figure 4c,d) present the honeycomblike graphene lattice. In areas where a hole exists (data not presented), layer counting from the edge also confirms the presence of monolayer graphene.68 DF-TEM allows one to determine the domain size, shape, and relative rotation angles of the graphene grains forming the single-layer polycrystalline film.69−72 Examples are provided in Figure 4e and Figures S7, S8, and S9 in the Supporting Information. False color is used to aid the eye to easily see the grain shape and relative grain orientations in Figures 4e and S7. The DF-TEM data consistently show the grains are faceted; that is, the single-layer graphene film comprises stitched polygonal graphene grains, and this observation differs significantly from the grain shapes found in polycrystalline monolayer graphene formed over Cu using common CVD routes.70,72 In order to better understand the grain boundaries, we employ complementary AFM, SEM, and low-voltage HRTEM studies. Figure 5a shows a typical AFM topography image of monolayer graphene film. The tomography images show regions of lines of bright contrast (increased height) concomitant with the faceting of the grains as shown in Figure 5a−c. Phase imaging (Figure S10) makes observation of the facets easier73 and also allows one to determine where grain boundaries with no height change most probably are (using WSXM processing software). Height measurement statistics show boundary heights varying between 0 and 1.4 nm (average 0.3 ± 0.04 nm) and are discussed in detail below. The faceted grain boundaries are mostly visible by SEM and show up as lines of reduced intensity relative to the monolayer graphene on the Si/SiOx substrate (Figure 5e,f). The reduced contrast in SEM occurs because the local curvature of a raised graphene grain boundary provides more shielding for the secondary electron emission (from the Si/SiOx substrate) so that the facets look darker than the overall flat graphene film lying flush with the substrate.74,75 The reduction in contrast is determined to be as much as 22 ± 4% (as extracted by Gwyddion image analysis software). In both the AFM and SEM data the faceted grain boundaries are analogous to those found with DF-TEM mapping, as for example shown

DISCUSSION The collected statistics of the grain boundary heights do not fit a Gaussian profile; indeed the profile seems to have three peaks (Figure S12a). Moreover, a statistical analysis of the relative rotation angles between grains also shows three peaks in the distribution (Figure S12b). These data are in excellent agreement with a theoretical study by Carlsson and others,75 which correlates grain boundary (out-of-plane) heights with relative rotation angles. The theoretical study showed that the most common rotation angle is 28°, in agreement with our experimental data as well as that from others.71,78 The relative height for relative rotations of 28° was predicted to be between 0 and 0.3 nm; experimentally we observe ca. 0.2 nm. The theoretical work also claimed heights between 0.6 to 0.8 nm and 1.0 to 2.0 nm for relative grain rotations of around 10° to 20° and 0° to 10°, respectively. Again, our experimental data are in good agreement with the theoretical study. We now turn to the evolution and merging of the individual disk-like islands that ultimately yield faceted grains in the largearea homogeneous monolayer graphene film. The formation of facets with merging disks occurs as they seek to minimize their perimeter and hence minimize energy. Much like multiple bubbles clustering, their minimal configuration is achieved when the shape of the cluster is faceted.79−81 This process ideally leads to the formation of hexagons. By analogy we can think of the hexagon cells in a beehive, which require the minimum possible amount of wax. The grains in our large-area homogeneous monolayer graphene are for the most part hexagonal, although at times deviations, such as four-, five-, and seven-sided polyhedra, are seen (Figure S13), which is attributed to the nonuniform spatial distribution of the nucleating islands. The faceting process of clustering islands is illustrated in Figure 6. A key advantage of this approximation toward hexagonal faceting of the grain is that the sum length of grain boundaries per unit area [∑LGB/πr2] is less than for most large-area graphene films grown over metal, where complex grain shapes are obtained, and so the sum length of grain boundaries per unit area in these cases is larger. Grain boundaries are scattering sites that can reduce electrical performance,72 and hence, as we show below, because of the faceting and hence minimization of grain boundaries, our large-area homogeneous single-layer graphene competes very favorably with single-crystal graphene grown over nonmetals and large-area graphene grown over Cu. Hence, we now examine the optical and electrical performance of the large-area single-layer graphene film directly fabricated over Si/SiOx. Figure 7a shows the optical transmittance of the graphene films after transfer onto a transparent quartz substrate. Starting from 450 nm, a 97% transmittance is achieved with 97.9 ± 0.5% at 550 nm, which agrees well with 1951


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nm) for 6 h CVD growth. The fact that we obtain similar transmittance results for both 5 and 6 h CVD growth times shows that once a full coverage layer of graphene has formed (5 h), continued CVD for extended periods does not lead to additional graphene layer formation; that is, the growth reaction is self-limiting, probably because there are no available sites for new adatom formation due to depletion of active grain edges via stitching at the grain boundaries.82,83 The self-limiting growth is further supported by Raman spectroscopy studies on samples grown between 6 and 8 h. All samples show homogeneous monolayer graphene (e.g., Figure S14). Figure 7c shows the output drain−source current characteristics of a graphene field effect transistor from our large-area graphene with a back gate for tuning. Figure 7d shows the transfer characteristics (gate voltage manipulated drain current) for a drain source voltage of 0.1 V. The unipolar transfer curve shows p-type doping, which is attributed to adsorbents from the air84,85 and/or chemical residue from the device fabrication process.86−88 The carrier mobility from 20 fabricated transistors using our monolayer graphene grown directly over Si/SiOx ranged from 410 to 760 cm2 V−1 s−1 (extracted from the middle linear region89 of the transfer characteristics). The FET mobility in this work is the best ever measured in a back-gated transistor for direct synthetic graphene monolayer full-coverage films formed over a Si/SiOx substrate. A comparative study with other works can be found in Table S3 and Figure S15a. In addition, this mobility is analogous to that of the transferred graphene over flexible substrates.90 Moreover, the mobility of direct synthetic graphene in this work starts approaching the performance of monolayer graphene full-coverage films grown over Cu.55,91 To highlight the competitiveness of our large-area monolayer graphene grown directly over Si/SiOx, we compare its electrical performance data with published values, including graphene grown over Cu, and present that in a graphical format (Figure S15b) and in tabular form (Table S4).

Figure 6. Growth evolution of a graphene monolayer film in a bubble-like fashion. AFM imaging for different stages: (a) Early formation of graphene nuclei. (b) Two adjacent graphene grains increase in size and both their frontier edges contact initially at a tangential point. (c) The graphene domains continue growing, and their grain boundaries become elongated. (d, e, f) Schematics of merging disk grains. (g, h) Sketch and AFM image for clustering of graphene disks. (i) Outline of the faceted grain boundaries of the monolayer graphene.

CONCLUSIONS In this work we revisit the direct CVD growth of graphene over Si/SiOx, with which it is notoriously difficult to obtain uniform monolayer graphene. Here we show that by implementing a simple confinement approach, in which the Si wafers are simply sandwiched together, one can obtain large-area uniform singlelayer graphene films. Once full coverage of the film is obtained, no further graphene formation is observed, indicating the process is self-terminating. Initially during the formation circular or disk-like graphene islands form. As they grow and merge (cluster), faceted grain boundaries form, and this arrangement is attributed to energy minimization, much like layers of bubbles clustering together. This process leads to a near minimal total length of grain boundaries per unit area, which is reflected in the optical and electrical characteristics of the as-produced material that is as competitive as equivalent large-area graphene fabricated over Cu. This competitiveness and also the ease of the synthetic graphene route developed might hold promise for scaling by simply stacking sandwiched wafers on top of each other (Figure S17) and if successful could reinvigorate efforts for the direct CVD synthesis of uniform graphene fabrication over Si/SiOx, which has the key advantage of not requiring transfer as compared to CVD techniques with metal catalyst supports such as copper. Moreover, it is easy to visualize how the technique

Figure 7. Optical and electrical performance of large-area monolayer graphene (from the sandwich configuration in Figure 1c). (a, b) Optical transmittance of a graphene film (transferred onto a fused quartz substrate) for samples from 5 and 6 h growth, respectively. (c) Output drain current for drain voltage while tuning gate voltage. (d) Transfer characteristics of the graphene transistor at a drain voltage of 0.1 V (heavy p-doping is observed). Insets show an optical picture and sketch of a graphene field effect transistor with a global back gate.

the published data for monolayer graphene.26 This further confirms the large-area full coverage of our film is single-layer graphene. Figure 7b shows a similar result (97.7 ± 0.4% at 550 1952


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ACKNOWLEDGMENTS We thank Andrea Voss for support with the optical measurements. M.H.R. and L.F. thank the Sino-German Center for Research Promotion (Grant GZ 871). J.P. thanks the IFW Dresden, Germany, and CMPW (Centre of Polymer and Carbon Materials, Polish Academy of Sciences), Poland, for support. H.Q.T. and M.H.R. thank Soochow University for its support. A.B. thanks the National Science Center for the financial support within the frames of the Sonata Program (Grant agreement 2014/13/D/ST5/02853). M.H.R. acknowledges the National Science Center Opus Program (Grant agreement 2015/19/B/ST5/03399) and the National Science Foundation China (NSFC, Project 51672181).

might be extended to other two-dimensional materials and van der Waals heterostructure materials in general.

MATERIALS AND METHODS Graphene Growth. A Si/SiOx (300 nm oxide) wafer after sonication in acetone and drying in N2 was used for the synthesis experiments. The graphene grains and films were synthesized in a horizontal corundum tube furnace. CVD synthesis was performed at a temperature of 1185 °C in ambient pressure with a gas mix of Ar/H2/ CH4 with flow rates of 120/30/1.5 sccm, respectively. The growth times varied according to the specific experiment in question. The samples were typically heated in an Ar/H2 flow (120 sccm/30 sccm) to the synthesis temperature. After the temperature stabilized (10 min), the Ar/H2/CH4 gas mix was introduced for a nominal growth time. It was found that a post-treatment under Ar/H2 for ca. 20 min followed by cooling in an Ar atmosphere yielded the cleanest (minimal surface contamination) graphene. Transfer. For TEM and optical transmittance investigations the graphene was transferred using a KOH aqueous solution to detach the graphene sample from the Si/SiOx surface. The protocol steps are spin-coating PMMA, detaching the film in KOH (2 M), fishing onto a TEM grid in 2-propanol medium,92 and then PMMA removal using acetone. Finally, high-vacuum annealing is employed to remove any organic residues. Characterizations. SEM measurements were performed on a Zeiss Ultra Plus and a FEI Quanta 250 (5 kV) with secondary electron detector. AFM was performed using an Asylum Research Cypher in the tapping mode (0.8 Hz for 1024 by 1024 pixels). DF-TEM was performed on a Tecnai F30 (at an acceleration voltage of 80 kV). HRTEM was performed on a Titan 80-300 with Cs corrector for the primary objective lens (at an acceleration voltage of 80 kV). Raman spectra and mapping were performed on a WiTec alpha 300 (514 nm laser excitation). Optical transmittance was performed on a UV/vis spectrophotometer (Analytik Jena Specord 250). The electrical transistor measurements were conducted using a dual-channel source-meter unit (Keithley 2612B). Graphene Transistor Fabrication. First, a graphene strip was prepared using a PMMA photoresist and e-beam lithography90,93−96 and finally oxygen plasma etching. The lithography pattern was prepared on a Hitachi S400 SEM with a Raith writer. Then, pads and tips for the source and drain were fabricated using e-beam lithography in which Au/Ti was deposited with e-beam evaporation plus lift off.97−101

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ASSOCIATED CONTENT S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.6b08069. The supporting information contains additional characterization data as well as comparative studies to graphene produced by other techniques (PDF)

AUTHOR INFORMATION Corresponding Authors

*Phone (A. Bachmatiuk): +48 32 2716077-166. Fax: +48 32 2712969. E-mail: [email protected]. *Phone (M. H. Rümmeli): +86 512 67873347. Fax: +86 512 67873347. E-mail: [email protected]. ORCID

Jinbo Pang: 0000-0001-6965-4166 Lars Giebeler: 0000-0002-6703-8447 Zhongfan Liu: 0000-0003-0065-7988 Mark H. Rümmeli: 0000-0002-4448-1569 Notes

The authors declare no competing financial interest. 1953


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