Article pubs.acs.org/journal/apchd5
Fabrication and Demonstration of III−V/Si Heterocore Microcavity Lasers via Ultrathin Interlayer Bonding and Dual Hard Mask Techniques Chee-Wei Lee, Doris Keh-Ting Ng,* Ai Ling Tan, and Qian Wang Data Storage Institute (DSI), Agency for Science, Technology and Research (A*STAR), 2 Fusionopolis Way, Innovis, #08-01, Singapore 138634
ABSTRACT: Heterogeneously integrated heterocore microcavity III−V semiconductor lasers on silicon-on-insulator (SOI) are fabricated and demonstrated in this paper. The heterocore microcavity is realized via ultrathin silicon dioxide interlayer bonding of III−V on SOI and dual hard mask technique. The dual hard mask technique utilizes flowable oxide and silicon nitride as etch masks for III−V and SOI etchings, respectively, and hence, a single lithography is required in the fabrication. Compact opticalpumped heterocore microdisk lasers are demonstrated and their lasing performances are characterized. KEYWORDS: microcavity lasers, heterogeneous integration, nanofabrication
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with an adjacent SOI bus waveguide as in an ordinary microresonator cavity.9,10 The fabrication of this microcavity with micrometer-scale diameter imposes challenges on the processes, namely, the following: (i) The process should minimize the use of lithography overlay to etch the entire cavity, as the multilayers device requires very high alignment accuracy. The cavity performance will be affected if misalignment occurred. Selfaligned technique is preferred for the fabrication. (ii) The III− V and SOI must be bonded together strongly to refrain the different layers from peeling off throughout the whole process, that is, the bonding mechanism must be able to withstand the harsh environment caused by the etching and the high temperature. (iii) The process must be able to etch through the three layers, and this imposes different requirements on the resist and etch mask for the various etching process. For examples, the resist or etch mask must be able to withstand high temperature during the III−V etching and an etch recipe should only attack the intended material but not the others materials in the cavity. To address these challenges, the heterogeneous III−V/Si integration platform is realized via novel combination of various advanced fabrication techniques
eterogeneous III−V/Si integration technology through wafer-bonding enables passive and active devices integration for realization of photonic subsystem-on-chip. There are a number of demonstrations on heterogeneous III−V/Si integration platforms, and on III−V lasers on silicon as light source is a vital device required for optoelectronic systems.1−7 The demonstrations so far are mainly based on bonding III−V to silicon directly, through BCB interlayer or using silicon dioxide layers. The SOI is preprocessed before bonding in these published works and a light coupling structure8 is normally required to couple light from III−V to the SOI beneath. In this paper, we present fabrication and demonstration of heterogeneously integrated compact heterocore microcavity III−V/Si lasers. Microcavity on-chip laser with a low power consumption and small foot-print is an important device for photonic system on chip and potential optical data inter/ intrachip transmission. The microcavity III−V/Si lasers presented in this paper is an etched through structure with three materials layers that are III−V, SiO2 and SOI, with III−V being the uppermost layer. The microcavity comprises two vertically stacked disks of III−V and SOI materials, both having identical lateral dimension, with the former provides light amplification and the latter provides passive light guiding. Possible light extraction from such hybrid cavity can be made © 2016 American Chemical Society
Received: October 14, 2016 Published: October 26, 2016 2191
DOI: 10.1021/acsphotonics.6b00794 ACS Photonics 2016, 3, 2191−2196
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including ultrathin SiO2 interlayer bonding and dual hard mask single lithography patterning process The ultrathin SiO2 interlayer molecularly bonds the III−V and SOI together. This covalent bonding is much stronger and able to withstand the high temperature as compared to adhesive bonding using benzocyclobutene (BCB),11 which may not able to withstand temperature higher than 200 °C. The dual hard mask single lithography patterning process uses siloxane or flowable oxide resist and Si3N4 as the dual hard mask. The technique allows us to etch down the three materials to form the cavity with only a single lithography step. The etching recipe and the corresponding etch mask combinations are designed such a way that they etch only the intended material, while having minimum effect on the other materials on the sample. Besides, the self-aligned mask from the nitride and the III−V cavity get rid of the tight alignment accuracy in defining the SOI cavity, should an overlay technique is employed. The siloxane resist is used as the etch mask for the Si3N4 and the III−V etching, while the nitride mask is then used to etch the SiO2 through self-alignment. The Si3N4 and the III−V combined subsequently act as the etch masks for the final SOI etching. The designed process not only makes it possible to fabricate such heterocore devices, but also greatly reduces the process difficulty. All these processes will be explained in detail. With such hybrid architecture, we demonstrate optically pumped lasers based on disk geometry, and the lasing performance is characterized, in terms of their L-L curves and spectrum, are presented and discussed. Finally, a summary is drawn.
Figure 1. SEM of the as-grown III−V epitaxy layers lattice-matched on InP substrate. The contrast between InP and InGaAsP layers are seen after the cleaved facet of the sample is subjected to a quick dip in diluted hydrochloric acid.
etch stop layer during the substrate removal in the wafer bonding process. All the layers are undoped and latticematched to InP substrate. The MQW gives a photoluminescence (PL) peak of around 1510 nm. On the other hand, the SOI substrate (Soitec) has a buried oxide (BOX) thickness of 2000 nm, and the SOI layer thickness is 340 nm. The SOI substrate is subjected to dry oxidation to give a high quality and smooth thermal oxide with a thickness of about 100 nm, leaving behind SOI layer with thickness of around 300 nm.
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EXPERIMENTS The fabrication process for the heterocore microcavity mainly consists of A) wafer preparation, B) low temperature SiO2 interlayer bonding; and C) dual hard mask single lithography patterning process and device etching.
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LOW TEMPERATURE SIO2 INTERLAYER BONDING The first step of forming the heterocore cavity is to bond the III−V epitaxial thin film onto SOI substrate. The bonding is done through our SiO2 interlayer bonding process developed in-house,12 which has various advantages over the common direct bonding used in literature.13,14 It eliminates the need for fabricating outgassing structures, such as etched trenches or holes on the Si substrate for byproduct gas diffusion and absorption during the bonding process. This reduces the fabrication process steps. The hydrophilic and porous oxide layer provides a medium for outgassing purpose, besides giving a stronger bonding strength15 than hydrophobic bonding surfaces. The interlayer also allows us to have the flexibility in the choice of host substrate regardless of any lattice matching, as long as a high smoothness oxide interlayer can be deposited. In terms of process, interlayer bonding eliminates the use of hazardous chemicals such as Piranha and hydrofluoric acid (HF) that are required in the direct III−V to Si bonding process.15 One concern with the wafer bonding process is the fidelity of the material quality before and after bonding. This has been studied extensively in our previous publication,12 which shows that the material property is largely preserved after the bonding process. For our demonstration, the oxidized silicon wafer is cleaved into pieces with size of 20 × 20 mm2 and the III−V wafer is cleaved into smaller die size of 10 × 10 mm2. The bonding process starts with cleaning the two material substrates with organic solvents in ultrasonic bath for 5 min in each solvent. The solvents used are acetone, followed by isopropyl alcohol
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III−V MATERIAL AND SOI WAFER PREPARATION The III−V material that we used is InGaAsP-based. The III−V epitaxy film is grown by metal−organic chemical vapor deposition (MOCVD) commercially (IQE, Inc.). The active region consists of six quantum well (1.51Q) and seven quantum well barriers (1.27Q) with thicknesses of 10 and 20 nm, respectively. The layer structure of the as-grown wafer is summarized in Table 1, and the Scanning Electron Micrograph (SEM) of the as-grown layers are shown in Figure 1. The multiple quantum wells (MQW) stack is sandwiched by 5 nm of InGaAsP (1.27Q) layers. The InGaAs layer is a chemical Table 1. Epitaxy Layers of the III−V Material Used in Fabrication of the Hetero-Core Microcavity layer
thickness (nm)
InGaAsP (1.27Q) InGaAsP (1.27Q) InGaAsP (1.51Q) × 6 InGaAsP (1.27Q) × 6 InGaAsP (1.27Q) InP InGaAs InP substrate
5 20 10 20 5 500 100
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(IPA), and then rinsed with deionized (DI) water. The SOI sample then goes through rigorous cleaning with modified RCA solution of NH4OH/H2O2/H2O = 1:2:10 at 85 °C for 20 min. Subsequently, the SOI sample is rinsed thoroughly with flowing DI water. Meanwhile, the InP substrate is cleaned with NH4OH solution for 1 min and rinsed with DI water. It is advisible to always keep the samples in DI water without exposing to air unnecessarily in order to prevent collection of particles onto the cleaned surfaces. After the chemical cleaning, the two prebonding surfaces are blown dried and subjected to O2 plasma surface activation for 1 min. The RF power used is low at 50W so that the surface is not in any way damaged by the plasma. The process pressure used is 250 mT and the O2 flow rate is set at 20 sccm. The two substrates are then brought to close proximity and bonding front is started from one edge to another slowly at room temperature to reduce the air trapped between the substrates. The pair is bonded via van der Waals force at this moment. The bonded pair is then loaded from the top with a pressure of 0.3 MPa and the whole fixture is placed in a vacuum oven to anneal at 220 °C for about 10 h. The two materials are bonded covalently at this point (left photo in Figure 2). The InP
Figure 2. Photographs present the appearance of the sample after bonding (left) and substrate removal (right).
substrate is removed with HCl/H2O = 3:1 solution in a beaker for roughly an hour, leaving behind only the MQW on the SOI substrate (right photo in Figure 2). The bonded pair is then rinsed with DI water and blow dried with nitrogen gun to complete the bonding process.
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DUAL HARD MASK SINGLE LITHOGRAPHY PATTERNING PROCESS For our heterocore cavity fabrication, it is highly challenging to etch the entire cavity. There is no single etch recipe and etch mask that allow us to etch the whole cavity, and hence, proper process design has to be made. As such, dual hard mask technique is used in our cavity etching. The dual hard mask process was reported before using different hard mask materials16 and for different purposes. With our process design utilizing the dual hard mask technique, we avoid multiple overlay lithography and etching cycles, which is extremely difficult. Furthermore, only one lithography step is needed in our final process design. The simplified diagram of the dual hard mask single lithography system is presented in Figure 3. The scanning electron micrographs (SEM) of the structure at various process stages are included as well. In our dual hard mask single lithography process, first a conformal layer of Si3N4 layer with thickness of 300 nm is deposited onto the bonded sample by using inductively coupled plasma chemical vapor deposition (ICP-CVD). FOX-22 (Corning) is subsequently spin-coated on the sample, with a thickness of around 400 nm. The sample
Figure 3. Simplified illustration of the dual hard mask single lithography technique. The SEMs show the appearance of the sample at the various process stages.
is subjected to electron beam lithography (EBL, Elionix) to transfer the cavity design onto the FOX-22 resist. The exposed resist is developed in TMAH 25% solution. The developed FOX-22 features are then used as the etch mask for Si3N4 etching. The etching is done in an advanced dielectrics etch (ADE, SPTS) system by using CHF3 and H2 plasma. Following the Si3N4 etch, the remaining resist is used for the etching of the MQW. The MQW etching is done in an ICP system (Oxford Instruments) employing Cl2 and N2 recipe, with stage heating at 250 °C for effective removal of InClx. FOX-22 resist is able to withstand the high temperature in the chamber, which is not possible if other organic resist is used instead. The etch selectivity of III−V to FOX-22 is around 10:1 for our recipe. The MQW is now etched through and exposing 2193
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the SiO2 interlayer underneath. The SiO2 cannot be etched with FOX-22 as etch mask due to their similar chemical structure, i.e., the etch recipe of SiO2 will etch away FOX-22 as well. Thus, Si3N4 has to be used as etch mask from now onward. In addition, Si3N4 layer is also the self-aligned mask for subsequent etchings. The etching of SiO2 is done in the ADE system with CHF3 and Ar recipe, and the last etching of SOI is done in the ICP system with CHF3 and SF6 recipe at a temperature of −20 °C. The etching on Si3N4 and III−V from this recipe is insignificant due to the low temperature. If we were to etch the entire cavity using a very thick layer of Si3N4, this would require an optimized recipe to deposit lowstress Si3N4 layer,17 which is not a straightforward task. Furthermore, a high selectivity etching recipe would be needed to etch the thick Si3N4 layer by using the FOX-22 as etch mask, and this is challenging. Metal etch mask is out of consideration as the produced rough sidewall will incur high loss to the cavity. Nevertheless, all these are more challenging methods and the dual etch masks process seems to be a more effective option. Also note that only a single lithography without overlay is needed for the fabrication. The completed heterocore microdisks are characterized inside a cryogenic chamber (JANIS), which allows the sample to be cooled down to liquid nitrogen temperature. We characterize our microdisk lasers at 78K. The excitation source is a continuous wave laser with emission wavelength of 1064 nm with maximum laser output power of 100 mW. Considering all the optical loss in the setup, the maximum deliverable power to the sample is around 25 mW. Hence, the actual excitation received by the devices would be less than 25 mW. The scattered laser emission from the devices is collected via the same objective and measured by an optical spectrum analyzer (OSA, Yokogawa AQ6370B) or photodetector.
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FABRICATED DEVICES AND CHARACTERIZATION
The SEMs of the fabricated heterocore are shown in Figure 4. The contrast between the different etched layers is visible under the low secondary electron imaging (LEI). Microcavity with different diameters are fabricated, and the SEMs show the images for microdisk with diameter of 4 and 5 μm in Figure 4a and b, respectively. In Figure 4c, the zoom in view of the sidewall is shown. Some minor corrugation at the sidewall is observed, which is typical for dry-etched sidewall. But, nevertheless, the sidewall is almost vertical (∼90°) throughout, and the SOI is completely etched with no residue seen on the BOX layer. There is no observable overetch or undercut on the structure. The design dimension is also transferred with fidelity onto the materials. The circular trench at the peripheral of the Si3N4 hard mask is likely due to the microtrenching18 occurred during Si3N4 and MQW etchings with FOX-22 as etch mask. The rough surface is caused by the attacks of the various plasma etchings imposed on the sample for MQW, SiO2, and SOI etchings. The L-L curves of the microdisk lasers with diameter of 4 and 5 μm are shown in Figure 5a and b, respectively. In our measurement, we optically pump the lasers with a continuous wave (CW) laser source having wavelength of 1064 nm. The pumping source is delivered through a microscope objective to the top of the devices. The sample is placed in a cryogenic chamber and cooled down to 78 K. The CW lasing is collected from the top of the devices through surface scattering. The laser emission is then analyzed by an optical spectrum analyzer
Figure 4. SEM of the microdisks with diameters of (a) 4 and (b) 5 μm and (c) the zoom in view of the sidewall profile for the etched microdisk.
(OSA, Yokogawa AQ6370B). The power is in nanoWatt range because it is the scattered power. As compared to the microcavity laser demonstrated in ref 19, our lasers exhibit clear lasing threshold. The corresponding thresholds for the two microdisk lasers with diameter of 4 and 5 μm are about 15 and 10 kW/cm2. In general, the lasing threshold increases as the device shrinks, which is understandable because when a microcavity gets smaller, the optical loss due to sidewall scattering increases as the mode is squeezed more to the cavity sidewall. In addition, the well-known fact of deteriorating Q factor with cavity size also contributes to increase of laser threshold. As compared to other similar work,20−22 our laser has threshold density in the same order, but our cavity is much smaller than the DFB laser,22 which is counterintuitive as our threshold density should be higher because of much smaller 2194
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CONCLUSION In summary, we fabricated a heterocore or hybrid microcavity with MQW thin film (∼210 nm) bonded on SOI. The fabrication of such cavity is made possible through our process design utilizing the low temperature SiO2 interlayer bonding and the dual hard mask single lithography patterning process, which is a novel integration of processes that is one of a kind. We demonstrated microdisk lasers with various sizes and the results are presented in terms of pumping efficiency, lasing threshold and detected lasing power. The heterocore cavity does not require dedicated structure for light coupling between III−V and SOI, which makes it even more compact, and the light extraction could be done with just a conventional bus waveguide.
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors would like to express appreciation to Dr. Kim Peng LIM for the help on the SEM for epitaxy layers. REFERENCES
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Figure 5. L-L curves for the microdisk lasers with diameters of (a) 4 μm and (b) 5 μm, all measured at 78 K, and (c) characteristic lasing spectra of the 5 μm size microdisk.
devices. This could be attributed to our device design and process optimization that have played a vital role in reducing the overall cavity loss. Our footprint is also much smaller,20,21 which makes it a more compact option. Nevertheless, the operation of the our heterocore lasers are still at low temperature and optically pumped, and future work will be done to further improve the device. The characteristic spectrum for microdisk with diameter of 5 μm at above threshold operation showing a lasing wavelength of 1545 nm, is shown in Figure 5c. It exhibits a narrow line width below 40 pm. In our measurement, all collected power is in nanowatt level because it is the scattered light from the top and side of the cavity; moreover, there is also light escaping through the bottom substrate. 2195
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