Silicon Cations Intermixed Indium Zinc Oxide Interface for High

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Silicon cations intermixed indium zinc oxide interface for highperformance thin-film transistors using a solution process Jae Won Na, You Seung Rim, Hee Jun Kim, Jin Hyeok Lee, Seonghwan Hong, and Hyun Jae Kim ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b06643 • Publication Date (Web): 16 Aug 2017 Downloaded from http://pubs.acs.org on August 17, 2017

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ACS Applied Materials & Interfaces

Silicon cations intermixed indium zinc oxide interface for high-performance thin-film transistors using a solution process Jae Won Na1†, You Seung Rim2†, Hee Jun Kim1, Jin Hyeok Lee1, Seonghwan Hong1, and Hyun Jae Kim1*

1

School of Electrical and Electronic Engineering, Yonsei University, 50 Yonsei-ro,

Seodaemun-gu, Seoul 120-749, Republic of Korea 2

School of Intelligent Mechatronic Engineering, Sejong University, 209 Neungdong-ro,

Gwangjin-gu, Seoul, 05006, Republic of Korea

KEYWORDS: Interface engineering, metal oxide semiconductor, solution processing, thermal diffusion, thin-film transistor

†

These authors contributed equally to this work

CORESPONDING AUTHOR: [email protected]

ACS Paragon Plus Environment 1


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Abstract Solution-processed amorphous metal-oxide thin-film transistors (TFTs) utilizing an intermixed interface between a metal-oxide semiconductor and a dielectric layer are proposed. In-depth physical characterizations are carried out to verify the existence of the intermixed interface which is inevitably formed by inter-diffusion of cations originated from a thermal process. In particular, when indium zinc oxide (IZO) semiconductor and silicon dioxide (SiO2) dielectric layer are in contact and thermally processed, a Si4+ intermixed IZO (Si:IZO) interface is created. Based on this concept, a high-performance Si:IZO TFT having both a field-effect mobility exceeding 10 cm2 V-1 s-1 and a on/off current ratio over 107, is successfully demonstrated.


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1. Introduction The fabrication of electronic devices using a solution process, with an aim to replace vacuum processes, is a key issue in realizing low-cost electronics.1-3 Amorphous metal-oxide semiconductors are highly promising materials for the low-cost electronics due to their straightforward processability towards solution phases. When amorphous metal-oxide semiconductors are applied to thin-film transistors (TFTs), they show high electrical properties, e.g. high field-effect mobility, low temperature process, high transparency, and good electrical uniformity over a large area. For these reasons, amorphous metal-oxide semiconductors are widely utilized in various applications such as display backplanes, sensors, and logic devices.4-7 Typically, a chemical conversion process is essential for the fabrication of solutionprocessed metal-oxide films with good electrical properties.8-11 A thermal energy induced process is commonly applied as a chemical conversion process and highly related to the formation of metal-oxide network with following several key steps: decomposition of organic solvent and precursor ligands, formation of metal-oxide chemical bondings, and densification of the film.12 This process also accompanies with thermodynamic reactions regarding interdiffusion and Gibbs free energy between the solution materials and adjacent interface layers.13 That is, an intermixed interface between a metal-oxide semiconductor and a dielectric layer can be considered in terms of phase transformation such as alloy or new layer formation. Here, we apply the engineering of intermixed interface formation between a metal-oxide semiconductor and a dielectric layer for the fabrication of high performance metal-oxide TFTs. Solution-processed indium-zinc-oxide (IZO) as a semiconductor layer and silicon dioxide (SiO2) as a dielectric layer are carefully investigated to verify the intermixed interface. The silicon cations of small ionic radii can easily diffuse into the IZO layer as



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either interstitials or SiOx clusters and Si4+ intermixed IZO (Si:IZO) system is highly expected.14 As reported in previous literatures, silicon incorporation in sputter-processed IZO film can effectively modulate the electrical characteristics of IZO TFTs due to strong siliconoxygen bonding in comparison to zinc and indium. 15-17 In this regard, we expect the diffused Si4+ from the SiO2 dielectric layer would behave as a carrier suppressor in the solutionprocessed IZO film. IZO has been widely used as a X:IZO platform to apply the carrier suppressing effects of additional X cations in metal-oxide film, e.g., X = Ga3+, Hf4+, Al3+, Mg2+, La3+, etc.18 Similarly, IZO can provide an appropriate platform to observe the effects of diffused Si4+ in the IZO film. Based on this concept, we confirmed that the device performance of ultrathin Si:IZO semiconductor could be significantly changed by adjusting thermal energy and effective channel thickness via a solution process. The Si:IZO TFTs exhibited an excellent performance with a high field-effect mobility exceeding 10 cm2 V-1 s-1, a large on/off current ratio over 107, and a sub-threshold voltage swing of 0.63 V dec-1.

2. Experimental Section 2.1 Synthesis of Metal-Oxide Precursor Solution The 0.1 M IZO solution was prepared by dissolving 225.6 mg of indium nitrate hydrate (In(NO3)3•xH2O, Aldrich, 99,999%), and 47.3 mg of zinc nitrate hydrate (Zn(NO3)2•xH2O, Aldrich, 98%) into 10 ml of 2-methoxyethanol (2ME, Aldrich, 99%). The 0.1 M IZO solution was stirred vigorously for 1 h under ambient conditions, and aged for 24 h before spincoating. 2.2 Fabrication of IZO TFTs To fabricate bottom-gate structured TFTs, we depotited three layers of IZO films on a heavily doped p-type Si substrate with thermally grown 1200-Å-thick SiO2 layer. For deposition of the first IZO layer, the 0.1 M IZO solution was spin-coated at 3000 rpm for 30 s


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on the substrate. The substrate was pre-annealed at 100°C for 5 min and post-annealed for 30 min. On top of the first IZO layer, spin-coating of the 0.1 M IZO solution, pre-annealing at 100°C for 5 min, and post-annealing for 30 min were repeated. For the third IZO layer, spincoating of the 0.1 M IZO solution, pre-annealing at 100°C for 5 min, and post-annealing for 90 min were conducted. We maintained post-annealing tempeatures at 230, 280, 330, and 380°C, respectively. The entire post-annealing time was 150 min. After the active layer deposition, aluminum source/drain electrodes were deposited by RF magnetron sputter via a shadow mask. The width and length of the channel were 1000 µm and 150 µm, respectively. The fabricated IZO TFTs were immersed in water-distilled 5% acetic acid solution (CH3COOH, Aldrich, 99%) for 1 to 8 min for a selective etching process. The aluminum electrodes would be used as a protection layer from the acetic acid solution and the exposed IZO film would be selectively etched away as shown in Figure 1a. The selectively etched IZO film would be utilized as the active layer of oxide TFT. To ensure stability and repeatability, all etching was done with fresh solutions at room temperature. After etching, the samples were cleaned by DI water, and annealed at 150°C for 5 min to evaporate any remaining water molecules. 2.3 Fabrication of Coplanar Homojunction-structured IZO TFTs The active layer deposition on a heavily doped p-type Si substrate with thermally grown 1200-Å-thick SiO2 layer was conducted using the previously mentioned method. After the active layer deposition, photo resist (AZ1512, AZ Electronic Materials) was spin-coated at 4500 rpm for 25 s. The substrate was pre-annealed at 100°C for 10 min, and exposed to UV light (365 nm, 405 nm, and 436 nm) via a source/drain mask for 15 s. The substrate was hardbaked at 100°C for 3 min and dipped into a developer solution (AZ300MIF, AZ Electronic Materials) for 50 s to ensure that only the source/drain shaped PR coatings remain on the IZO film. The width and length of the channel were 300 µm and 15 µm, respectively. The etching



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process was conducted in 5% acetic acid solution to form coplanar homojunction-structured IZO TFTs as shown in Figure 1b. That is, the PR protected IZO film would be utilized as source/drain electrodes and the selectively etched IZO film would be utilized as the active layer of oxide TFT. Therefore, the IZO film simultaneously work as source/drain electrodes and the active layer of oxide TFT. After etching, the substrate was cleaned by acetone to strip off source/drain shaped PR coatings. The samples were cleaned by DI water and annealed at 150°C for 5 min to evaporate any remaining water molecules. 2.4 Film and Device Characterization The microstructure of the IZO film was investigated using high-resolution transmission electron microscopy (HR-TEM, JEM-ARM 200F) equipped with an energy dispersive X-ray spectrometer (EDS). The composition of the IZO film was examined using an X-ray depth photoelectron spectroscopy (XPS depth, K-alpha) and time-of-flight secondary ion mass spectroscopy (TOF-SIMS, Ion TOF). The thickness of the IZO and SiO2 films were examined by a spectroscopic ellipsometer (alpha SE). The image and profile of the coplanar homojunction-structured IZO TFT were examined using an optical microscopy (OM) and a surface profiler (DektakXT Stylus Profiler), respectively. The electrical characteristics of the device were measured in a dark box in ambient air using an Agilent 4155C semiconductor parameter analyzer. The parameter of TFTs was extracted from the conventional equations of metal-oxide semiconductor devices and measured under a drain voltage (VDS) of 30.1 V and the gate voltage (VGS) was swept from -30 V to 30 V.

3. Results and Discussion Solution-processed metal-oxide films contain pin holes and pore sites caused by solvent evaporation during annealing process. These defects are known to critically impact upon the electrical characteristics of solution-processed metal-oxide devices.19 To solve this issue, we


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constructed an ultrathin IZO film with a thickness of 14 nm through multi-stacking method (see Supporting Information Figure S1).20,21 To optimize the electrical characteristics of IZO films, we used In rich IZO precursor solution and performed a post-annealing process for 150 min at 230, 280, 330, and 380oC, respectively.22-24 Figure 2a shows the Hall-effect measurements of IZO films for the different post-annealing temperatures. The bulk carrier concentration (Nb) value of the IZO films increased with an increase in post-annealing temperatures, whereas the resistivity decreased; this could be attributed to the formation of oxygen vacancy (Vo) rich IZO films with increased conducting pathways.25,26 Figure 2b shows the device performances of the IZO TFTs and they were in good agreement with the respective IZO film properties confirmed by the Hall-effect measurements. Of the IZO TFTs, those that were annealed at a temperature of 380°C showed no switching characteristics due to their conductive channels having an excessive amount of carrier concentration (highest being that of Nb~1019 cm-3). With regard to thermodynamics, both post-annealing temperature and time significantly affect the variation of film properties regarding the atomic diffusion and Gibbs free energy.27 Here, we could expect that high temperature annealed IZO films were more favorable to induce atomic diffusion at the SiO2/IZO interface and this will be confirmed in the following HR-TEM/EDS analysis. We conducted a comparative study on IZO films annealed at 230 and 380oC using a crosssectional high resolution transmission electron microscopy (HR-TEM) in order to observe the intermixed Si:IZO interface at an atomic level in Figure 3a and 3b. The thicknesses of the featured IZO films annealed at 230 and 380oC were 14.11 and 14.01 nm, respectively. From the dark field HR-TEM images of both IZO films, it was difficult to detect the existence of the Si:IZO interface. Thus, we performed an energy dispersive spectroscopy (EDS) mappings of the HR-TEM images as shown in Figure 3e and 3f. From the EDS mappings, we found a gradient distribution of Si atoms from the interface to upper IZO region in both IZO films.



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However, it was shown that the distribution of Si atoms in the 380oC annealed IZO film was more widespread towards upper IZO region than that in the 230oC annealed IZO film. To observe the gradient of elements in more detail, the line scans of an EDS profile from the SiO2 film to the carbon region was measured in Figure 3c and 3d. From the line scans, we could divide the IZO films into two regions: (i) Si-rich intermixed Si:IZO region at the SiO2/IZO interface and (ii) the rest of the IZO layer. The exact thickness of the intermixed Si:IZO interface was difficult to determine; the interface for the 230 and 380oC annealed IZO films was approximated to be 3.41 and 5.25 nm thick, respectively. The increased thickness of Si:IZO interface in the 380oC annealed IZO film reveals that the high temperature annealed IZO film is more favorable to induce atomic diffusion at the SiO2/IZO interface. In addition, we performed a time-of-flight secondary-ion mass spectroscopy (TOF-SIMS) analysis for the 380oC annealed IZO film (see Supporting Information Figure S2) and the approximated thickness of Si:IZO interface was consistent with that of the TEM analysis. From both the HR-TEM analysis and the TOF-SIMS analysis, we verified that the intermixed Si:IZO interface was formed by the gradual inter-diffusion of Si4+, In3+, and Zn2+. However, in terms of ionic radius — a decisive factor in the diffusion process, we expected that the formation of the intermixed Si:IZO layer would be due to the high possibility of diffusion associated with Si4+, which has a smaller ionic radius (0.040 nm) than that of In3+ (0.080 nm) and Zn2+ (0.074 nm).14,28,29 Ions that have a small ionic radius require less diffusion activation energy; thus, the possibility of interstitial diffusion of Si4+ into the IZO film was quite high in this instance. With regard to In3+ and Zn2+ diffusion into a thermally grown SiO2 film, previous studies have shown that the movement of In3+ and Zn2+ in the thermally grown SiO2 film is limited at low annealing temperatures (300 to 500oC); hence, with regard to our given SiO2/IZO system, it is understandable that the possibility of diffusion of In3+ and Zn2+ is minimal.30 In addition, the post annealing process at 380oC limits the formation of definite


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phases such as zinc silicate (Zn2SiO4) which requires a high formation temperature at 775oC.31 We explained the formation of the intermixed Si:IZO layer in terms of ionic radius. However, the dominant factor has not still been experimentally cleared so that we will perform further study in terms of precise control of diffused elements in each side. As an indirect evidence for the formation of Si:IZO interface, we measured the thickness of SiO2 film before IZO deposition and after IZO etching (see Supporting Information Figure S3). We immersed a P+Si/SiO2 substrate and a P+Si/SiO2/IZO substrate into water-distilled 5% acetic acid solution for 8 min to completely etch away the IZO layer.32 The thickness of the SiO2 film in the P+Si/SiO2 substrate before the etching process was 121.12 ± 0.11 nm, measured by SE analysis. The thickness of the SiO2 film after the etching process was 121.10 ± 0.12 nm; hence, there was no significant change in the thickness. This shows that the 5% acetic acid solution was incapable of etching pure SiO2 film, regardless of etching time. On the other hand, after complete etching of the IZO film, the thickness of the SiO2 film in the P+Si/SiO2/IZO substrate was measured to be 117.72 ± 0.22 nm — 3.39 nm decrement compared to the thickness of the SiO2 film in the P+Si/SiO2 substrate prior to etching. This decrement in the thickness of the SiO2 film is indirect evidence that Si4+ from the SiO2 film has been dispersed for the creation of an intermixed Si:IZO interface; that is, it has been etched away along the IZO film. To observe the electrical variations between the IZO layer and the intermixed Si:IZO interface, we performed a selective etching process on the channel region as a function of etching time in Figure 4. As shown in Figure 4a and Table 1, the transfer characteristics of IZO TFTs showed a significant change as the etching time increased. Although there was a possibility of overestimation in determining the saturation field-effect mobility (µsat) due to peripheral currents by fringing electric fields in the non-patterned IZO films, the 5 min etched IZO TFT had good electrical characteristics with an average saturation field-effect mobility



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(µsat) of 10.14 ± 0.85 cm2 V-1 s-1, a large on/off current ratio over 107, and a sub-threshold voltage swing (S.S) of 0.63 V dec-1.33 As confirmed by SE analysis (see Supporting Information Figure S4), the thickness of IZO film after 5 min of etching was under 5 nm. This means that the active layer of the IZO TFT is completely comprised of the intermixed Si:IZO interface. We concluded that these good electrical characteristics are due to both the unique well-like ultrathin structure of a selectively etched IZO TFT confining the intermixed Si:IZO interface (in the form of an active layer) and the conductive IZO film (in the form of a contact layer) between the intermixed Si:IZO interface and aluminum electrodes. The intermixed Si:IZO interface is responsible for the proper switching characteristics of the IZO TFT, and the conductive IZO contact layer helps to lower the contact barrier between the IZO channel layer and the aluminum source/drain electrodes.34-36 We will discuss the detailed mechanism of reduced electrical conductivity in the intermixed Si:IZO interface in the following XPS analysis section. Those IZO TFTs with an etching time equal to or greater than 7 min were significantly degraded compared to those with an etching time equal to 6 min. This could be attributed to the limited carrier pathway with discontinuous IZO film structure. Eventually, the IZO TFTs showed insulating properties after 8 min of etching. We performed Hall-effect measurements of the IZO films with increasing etching time in Figure 4b; the measurements were in good agreement with the device characteristics. The Nb values of the IZO films decreased with increasing etching time, whereas the resistivity increased. We also calculated the surface carrier concentration (Ns) values of the IZO films and the Ns values of both pristine IZO films and 2 min etched IZO films — both of which were maintained above 1010 cm-2. However, when the Ns value of the intermixed Si:IZO interface was measured after 4 min of etching, the Ns value was found to be significantly below 108 cm-2; that is, the Ns value of the intermixed Si:IZO interface was much lower compared with


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that of the pure IZO films. Thus, the decreasing Nb values of the IZO films was attributed to both decreased IZO film thickness and diffused Si4+ in the IZO layer. To find evidence of diffused Si4+ in the intermixed Si:IZO interface, a depth X-ray photoelectron spectroscopy (XPS) measurement was performed. Figure 5b shows the O1s XPS depth profiles of the IZO film from the surface to the SiO2 layer. The O1s spectra were deconvoluted from three Gaussian curves centred at 530.3 ± 0.2 eV, 531.5 ± 0.2 eV, and 532.5 ± 0.2 eV. 530.3 ± 0.2 eV peak with a low-binding energy region (OI) represents lattice oxygen related to In and Zn metal-oxide bonds (M–O). The 531.5 ± 0.2 eV band with a middle-binding energy region (OII) corresponds to the metal-oxide lattice with oxygen vacancies (VO), and the 532.5 ± 0.2 eV peak with a high-binding energy region (OIII) is attributed to metal hydroxide (M–OH) and Si-oxide bonds (Si-O).37,38 From the O1s spectra of the OIII region, shoulders gradually appeared with increasing proximity to the SiO2 film. As confirmed in the HR-TEM and TOF-SIMs analyses, this transition region could be coresponded to the formation of Si-O bondings at the intermixed Si:IZO layer due to diffusion of Si4+ at the SiO2/IZO interface. Figures 5c-e show the area ratio of M-O, VO, and M-OH/Si-O for different depth thicknesses. In Figure 5d in particular, the relative area ratio of VO decreased after a depth thickness of 7.06 nm — this could be explained as a result of a reduction in carrier concentration (as confirmed by the Hall-effect measurement). In a metaloxide semiconductor, electrical properties are strongly dependent upon the amount of VO as a carrier generation source.39 The strong bonding strength of silicon with oxygen and low standard electrode potential (SEP) value of Si4+ are highly related. That is, an intermixed Si:IZO interface not only reflects the atomic diffusion at an IZO/SiO2 interface but also modulates the electrical properties of an IZO film through a reduction in oxygen vacancies with strong Si-O attraction.34 Additionally, we have analyized In3d5 and Zn2p3 spectra of the IZO film at 2.82 and 11.29 nm from the back-channel surface (see Supporting Information



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Figure S6). We could observe a shift toward lower binding energy in both In3d5 and Zn2P3 spectrum with increasing depth. The oxidized states of In-O and Zn-O compounds exhibit higher binding energy than In and Zn.40,41 The decrease of binding energy near the intermixed Si:IZO interface (at 11.29 nm) reveals that the oxidation states of In and Zn are decreased. Due to higher oxygen-binding ability of Si, some weakly bonded oxygen atoms in In-O and Zn-O may escape from their original bonds to from Si-O bonds leading to the recuction of binding energies of In and Zn. To confirm the critical role of an intermixed Si:IZO layer in TFT modulation, we constructed a P+Si/SiO2/ZrO2 (diffusion barrier)/IZO structure. As shown in Figure S7, the transfer curves of the diffusion barrier-embedded IZO TFTs shifted in a positive direction with increasing etching time because of the reduced IZO thicknesses. However, the IZO TFTs could not be completely turned off at a negative voltage bias compared to those without an embedded diffusion barrier. We concluded that a 10 nm of diffusion barrier effectively prevented the occurence of Si4+ diffusion within an IZO film. Thus, the electrical characteristics of the IZO TFTs could not be completely modulated due to a lack of Si4+ incorporation into IZO film. Meanwhile, the diffusion possibility of Zr4+ into an IZO layer was limited due to the ionic radius of Zr4+ (0.084 nm) — being larger than that of Si4+ (0.040 nm).28 Lastly, based on the results and evidences presented in this work, we fabricated a coplanar homojunction-structured IZO TFT. Instead of depositing source/drain electrodes using a vacuum process, we deposited source/drain shaped photo resist (PR) coatings as shown in Figure 6. After the PR coatings were finished, we continued the selective etching process for 6 min. Then, we stripped off the PR coatings. The conductive IZO films were clearly patterned in the shape of a source/drain electrode. They were then used as such. As we have mentioned privously, the IZO film was successfully etched into a well-like structure by the


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acetic acid solution and this was confirmed by alpha-step analysis (see Supporting Information Figure S8). The selectively etched IZO film between the patterned IZO films was responsible for a good switching performance of the device. The coplanar homojunctionstructured IZO TFT exhibited an average µsat of 0.35 ± 0.7 cm2 V-1 s-1, an on/off current ratio over 106, and a subthreshold voltage swing of 0.58 V dec-1. We believe that the degradation in µsat compared with IZO TFTs with aluminum source/drain electrodes is due to the inferior resistivity value of patterend IZO electrodes. As confirmed by the Hall-effect measurement, the resistivity value of the conductive IZO film is approximately 4.38 ± 1.7 x 10-1 Ω/cm. On the other hand, the resistivity of aluminum electrode is known to be 2.82 x 10-6 Ω/cm (at R.T) which is 5 orders of magnitude lower than that of the conductive IZO film.42 Thus, the higher resistivity value of the patterned IZO electrodes increased the contact resistance resulting in the degratdation of µsat.43 In addition, the relatively smaller channel length (12 µm) of the homojunction-structured IZO TFT might have caused the discrepency of µsat compared with IZO TFTs with aluminum source/drain electrodes. Although these electrical characteristics are inferior to those of the selectively etched IZO TFTs with aluminum source/drain electrodes, this structure has merits in that it can minimize the number of required fabrication steps by eliminating the need for a vacuum metallization process — a process that adds cost and complexity to the TFT fabrication process.44

4. Conclusion We have found crucial evidences for the formation of an intermixed interface between solution-processed IZO film and SiO2 film through various physical characterizations such as HR-TEM, TOF-SIMS, and depth XPS measurements. In addition, we have verified that such as intermixed interface can be utilized for the demonstration of a high performance solutionprocessed metal-oxide TFT via a simple oxide thinning process. The optimized IZO TFT showed a field-effect mobility exceeding 10 cm2 V-1 s-1, a large on/off current ratio over 107,



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and a small sub-threshold voltage swing value of 0.63 V dec-1. This high performance of the solution-processed IZO TFT is attributed to the exclusive utilization of both an ultrathin Si:IZO interface as an active layer and a pure conductive IZO film with source/drain electrodes as a contact layer. Furthermore, a coplanar homojunction-structured IZO TFT was successfully demonstrated to show a proper switching characteristic without additional aluminum source/drain electrodes. We expect this new work is highly expected to be applicable to the mobility and low-cost processability of solution-processed oxide electronics.


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Figures

Figure 1. Device schematics of (a) the selectively etched IZO TFTs and (b) the homojunction-structured IZO TFTs.

Figure 2. (a) Hall characteristics of IZO thin films. (b) Transfer characteristics of IZO TFTs as a function of annealing temperature.



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Figure 3. Cross-sectional HR-TEM images of (a) the 230oC annealed IZO film and (b) the 380oC annealed IZO film. EDS scan profiles of (c) the 230oC annealed IZO film and (d) the 380oC annealed IZO film. EDS mapping data of Si, In, and Zn elements (e) in the 230oC annealed IZO film and (f) in the 380oC annealed IZO film.

Figure 4. (a) Transfer characteristics of the selectively etched IZO TFTs as a function of etching time. (b) Hall characteristics of the IZO thin films.


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Figure 5. (a) A cross-sectional schematic for the formation of intermixed Si:IZO interface. (b) The O1s XPS depth profiles from the surface to the IZO film. The area percentages of (c) MO, (d) VO and (e) M-OH/Si-O as a function of depth. The percentages were computed based on the area integration of each O1s peak area.

Figure 6. Optical microscopic (OM) images of (a) PR coatings and (b) patterned IZO films. (c) The transfer characteristic of the homojunction-structured IZO TFT.



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Table 1. Extracted device parameters of IZO TFTs with increasing etching time. µFE

Etching time [min]

(cm2 V-1 s-1) Pristine 1 min 2 min 3 min 4 min 5 min 6 min 7 min

On/Off

VTH (V)

S. S. (V decade-1)

14.42 ± 0.92

4.11 x 100

-75.37 ± 2.43

54.7 ± 1.72

12.18 ± 0.85

1.35 x 10

1

-46.46 ± 1.27

24.57 ± 1.21

5.20 x 10

2

-12.89 ± 0.75

8.17 ± 0.43

-6.72 ± 0.32

3.78 ± 0.15

-2.42 ± 0.42

0.75 ± 0.12

-1.00 ± 0.38

0.63 ± 0.02

4.34 ± 1.23

0.63 ± 0.05

14.08 ± 0.59 3.41 x 10 Insulating (TFT always off)

1.00 ± 0.14

11.81 ± 0.92 11.24 ± 0.14 11.59 ± 0.42 10.14 ± 0.85 8.20 ± 0.83 1.77 ± 0.32

8 min

4

1.09 x 10 6

8.18 x 10 7

4.91 x 10 7

1.81 x 10 6

Author Information Corresponding Authors Hyun Jae Kim: [email protected]

Acknowledgement J.W.N. and Y.S.R. contributed equally to this work. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(MSIT) (No. 2017R1A2B3008719)

Supporting Information Spectroscopic ellipsometry results for the thickness of IZO film with increasing number of layers; TOF-SIMS profile of the IZO film as a function of depth; spectroscopic ellipsometry results for the thickness of SiO2 films; spectroscopic ellipsometry results for the thickness of IZO films as a function of etching time; XPS depth-profile results for O1s peak extracted at different depths; XPS depth-profile results of In3d5 and Zn2p3 at different depths; transfer characteristics of the selectively etched IZO TFT with ZrO2 Si4+ diffusion barrier as a function of etching time; surface profile analysis of the homojunction-structured IZO TFT


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Table of contents


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Silicon Cations Intermixed Indium Zinc Oxide Interface for High

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