Silicon Nanowire Field Effect Transistor Sensors with Minimal Sensor

Subscriber access provided by University of Florida | Smathers Libraries

Article

Silicon Nanowire Field Effect Transistor Sensors with Minimal Sensor to Sensor Variations and Enhanced Sensing Characteristics Sufi Zafar, Christopher D'Emic, Ashish Jagtiani, Ernst Kratschmer, Xin Miao, Yu Zhu, Renee Mo, Norma Sosa, Hendrik F. Hamann, Ghavam Shahidi, and Heike Riel ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.8b01339 • Publication Date (Web): 22 Jun 2018 Downloaded from http://pubs.acs.org on June 22, 2018

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Silicon Nanowire Field Effect Transistor Sensors with Minimal Sensor to Sensor Variations and Enhanced Sensing Characteristics

Sufi Zafar*, Christopher D’Emic, Ashish Jagtiani, Ernst Kratschmer, Xin Miao,1 Yu Zhu, Renee Mo, Norma Sosa, Hendrik Hamann, Ghavam Shahidi and Heike Riel

IBM T.J. Watson Research Center, Yorktown Heights, NY, 10598 IBM Research, 257 Fuller Road, Albany, NY 12203

1

*Corresponding author: [email protected]

1

ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ABSTRACT Silicon nanowire field effect transistor (FET) sensors have demonstrated their ability for rapid and label free detection of proteins, nucleotide sequences, and viruses at ultralow concentrations with the potential to be a transformative diagnostic technology. Their nanoscale size gives them their ultralow detection ability but also makes their fabrication challenging with large sensor to sensor variations, thus limiting their commercial applications. In this work, a combined approach of nanofabrication, device simulation, materials and electrical characterization is applied towards identifying and improving fabrication steps that induce sensor to sensor variations. An enhanced complementary metal-oxide-semiconductor (CMOS) compatible process for fabricating silicon nanowire FET sensors on 8’’ silicon on insulator (SOI) wafers is demonstrated. The fabricated nanowire (30 nm width) FETs with solution gates have the Nernst limit sub-threshold swing SS=60±1 mV/decade with ~1.7% variations, whereas literature values for SS are ≥ 80 mV/decade with larger (>10 times) variations. Also, their threshold voltage variations are significantly (~3 times) reduced, compared to literature values. Furthermore, these improved FETs have significantly reduced drain current hysteresis (~0.6 mV) and enhanced on-current to off-current ratios (~106). These improvements resulted in nanowire FET sensors with lowest (~3%) reported sensor to sensor variations, compared to literature studies. Also, these improved nanowire sensors have the highest reported sensitivity and enhanced signal to noise ratio with the lowest reported defect density of 2.1x1018 eV-1cm-3, in comparison to literature data. In summary, this work brings the nanowire sensor technology a step closer to commercial products for early diagnosis and monitoring of diseases. KEYWORDS: CMOS compatible fabrication, sensor to sensor variations, silicon nanowire field effect transistor sensors, potentiometric sensors, pH sensing. 2


Page 2 of 40

Page 3 of 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Silicon nanowire FET sensors have demonstrated their ability for fast, high sensitivity and label-free detection of proteins, nucleotide sequences, viruses, cellular signaling and biochemical reactions.1–10 These nanowires FET sensors offers several significant advantages over large area FET sensors. As discussed previously.4,11 nanowire FET sensors with their nanoscale size are particularly well suited for bio-molecule detection at ultra-low concentrations. Also, their reduced footprint makes them suitable for high density sensor arrays, thus enabling multiplexing from a minute sample volume.10 Furthermore, these miniaturized sensors have low power and voltage requirements, and are, therefore, well suited for portable diagnostic applications such as lab-on-chip.4 Another advantage of these nanoscale sensors is their reduced RC time constants, thus enabling observations of molecular binding kinetics at faster rates.4 Although nanowire FET sensors have the potential to be a transformative diagnostic technology, their commercial applications remain limited due to large fabrication-induced sensor to sensor variations that cause reproducibility and repeatability issues.8–10,12,13 The silicon nanowire FET sensor detection ability increases with decreasing nanowire width at ultra-low concentrations.4,11

However, as the nanowire width decreases, sensor to

sensor variations increases due to fabrication challenges at nanoscale.9,10,12,13

To address this

important issue, there have been several fabrication studies with majority of them focused on the top-down fabrication process.3,5,9,10,12,13

Data analysis methods also have been proposed for

reducing the impact of sensor variability.8,10 Despite these research efforts, the nanowire FET sensor variability remains an important issue. In this study, a combined approach of nanofabrication, device simulation, materials and electrical characterization is applied towards identifying and improving key processing steps that 3


ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 4 of 40

cause variations and degradation in silicon nanowire FET sensors. The study identifies defects near silicon/gate dielectric interface and thickness uniformity of gate dielectric layer over the 3dimensional nanowires as major factors causing sensor variations and degradation in nanowire FET sensors. Based on these identifications, special efforts are focused towards the formation of silicon nanowires and gate dielectric stacks that results in optimal interface and gate dielectric layers remains uniformly thick over nanowires during subsequent processing steps. An improved CMOS compatible top-down process for fabricating silicon nanowire FET sensors on 8’’ SOI wafers is demonstrated. The fabricated FET sensor consists of a silicon nanowire (width = height = 30 nm; length 5 µm) forming the channel, a dual layer stack of SiO2/HfO2 as the gate dielectric with HfO2 as the sensing surface, and an aqueous solution forming the top tri-gate. A total of 140 different sensors are characterized for statistical analysis, and the data is compared with those in the literature. The comparison shows that the improved nanowire FET sensors not only exhibit smallest sensor to sensor variations despite having the narrowest width but also have the most enhanced sensor performance.

RESULTS AND DISCUSSION Dependence of sensor variations on FET parameters. Sensor to sensor variations arise due to the variation in FET parameters that impact sensing characteristics. To identify these FET parameters, equations for sensitivity and signal to noise ratio (SNR) are briefly reviewed. FET sensor sensitivity (∆ID /ID) can be defined as:14,15 ∆ID /ID = (Gm / ID) δVψ = 2.303 SS-1 δVψ

4


(1)

Page 5 of 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

where, ID is the drain current, Gm is the trans-conductance, δVψ is the sensing surface potential change, and SS is the sub-threshold swing in the subthreshold region. The SNR per unit bandwidth, can be written as:15,16 SNR per volt = Gm / √ SI (1 Hz)

(2)

where, SI (1 Hz) is the ID noise power density at 1 Hz. From equations (1) and (2), SS and ID noise power density are two critical FET parameters impacting sensing characteristics. These parameters predominantly depend on trap defects at and near the silicon/gate dielectric interface,16,17 and therefore special fabrication efforts will be focused towards reducing these defects. Since these defect densities depend on the silicon/gate dielectric interface quality, processing steps that form nanowires and gate dielectric are important for reducing both variations and degradation in SS and ID noise power density of FETs. In this study, the nanowire length is set to 5 µm to minimize short channel induced SS degradations. To gain further insights into factors impacting sensor to sensor variations and degradation, device simulations are performed for long channel nanowire FET sensors (see Methods for simulation details). Fig. 1(a) shows the schematics for nanowire FET structures used in the simulation that explores the impact of variations in the gate dielectric thickness. Simulated results of Fig. 1(b) show that SS degrades when the gate dielectric thickness varies over the 3-dimensional nanowire: SS degrades by 5% when the gate dielectric is 15% thicker near the nanowire base than at the top. Hence, the gate dielectric thickness variation over a nanowire would degrade SS and would also induce SS variability if this thickness variation is different across the wafer. Fig. 1(b) shows device simulation results for the threshold voltage (VT) dependence on the nanowire width for long channel devices: VT varies rapidly for nanowire 5


ACS Nano

width < 25 nm and shows weaker dependence on wider widths. Based on this simulated dependence, the nanowire width is selected to be 30 nm to reduce width-induced VT variations. Since previous studies indicate that underlapped solution-gated FET sensors exhibit improved reproducibility and stability,18,19 the gate is designed to be underlapped (~30 nm on each side) so that source and drain regions are protected from the solution. Furthermore, device simulations show that the underlapped gate does not impact sub-threshold swing (SS) and threshold voltage but causes small decrease in the on-current in the linear regime (see Fig. S1 for schematics and simulation results for an underlapped FET in Supporting Information).

(a)

(b)

Uniform Thickness 3.2nm

(c) Uniform thickness SS = 60.3 mV/dec

-7

10

0.34

Si fin

0.32

Simulation

0.30

-11

10

Varying Thickness SS = 63.1 mV/dec

0.28

-13

Si fin

BOX

-9

10

22nm

Gate dielectric

Simulation

VT (V)

Varying Thickness 3.2 nm

ID (A)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 6 of 40

10

0.26 -0.4

-0.2

0.0

VGate (V)

10 20 30 40 nanowire width (nm)

Figure 1: Device simulation results for nanowire SOI p-type FETs with long channels and trigates. (a) Schematics showing nanowire structures with uniform and varying gate dielectric thicknesses (buried oxide and silicon substrate not shown; drawings are not to scale). (b) Using schematics shown in (a), simulated dependence of drain current (ID) on the gate voltage; simulations assume zero trap density at the silicon/oxide interface and SS is the subthreshold swing. (c) Simulated dependence of threshold voltage (VT) on nanowire width for nanowires with 30 nm height, 3.2 nm uniformly thick gate dielectric and silicon channel dopant density of 5x1015 cm-3.

6


Page 7 of 40

2.4

∆VHys (mV)

εHfO2 =18

EOT (nm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

2.1 SiO2

Vsol solution HfO 2 SiO 2

1.8

40

HfO2 = 3 nm

20

Si

SiO2

1.5 0

1

Vsub

2

3

4

0

1.0

5

1.5

2.0

2.5

d SiO (nm)

dHfO (nm)

2

2

Figure 2: Pre-fabrication experiments for selecting optimal SiO2 and HfO2 thicknesses for the gate dielectric stack to be used in the nanowire FET. (a) Equivalent oxide thickness (EOT) of the gate dielectric stack dependence on HfO2 layer thickness (dHfO2) with 1.5 nm thick as-grown SiO2 layer; εHfO2 is the HfO2 dielectric constant, estimated from the slope of the dashed blue line. The inset shows the schematics for measuring capacitance of a Si/SiO2/HfO2 stack with solution as the gate; Vsol is the gate voltage applied to the reference electrode immersed in the aqueous solution. (b) Dependence of hysteresis (∆VHys) in the capacitance curve on SiO2 layer thickness (dSiO2) with 3 nm thick HfO2. From (a) and (b), selected HfO2 and SiO2 thicknesses are 3 and 2 nm, respectively.

Selection of optimal gate dielectric. Since the gate dielectric critically impacts FET sensor characteristics such as subthreshold swing, interfacial defect density, hysteresis and threshold voltage,20-25 experiments are performed on blanket films to identify an optimal gate dielectric. A dual layer of SiO2/HfO2 is selected as the gate dielectric to take advantage of high quality Si/SiO2 interface and HfO2 attributes of Nernst limit pH sensitivity,26 superior ion diffusion barrier and low use voltages. Previous studies have shown that SiO2 and HfO2 thicknesses impacts Si/SiO2 interfacial trap densities.21,24,25 To provide guidance for selecting optimal SiO2 and HfO2 thicknesses, capacitance measurements are performed on blanket Si/SiO2/HfO2 stacks that have same thermal budget as the FET fabrication. SiO2 is grown by 7


ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

thermal oxidation, HfO2 is deposited by atomic layer deposition (ALD), and an aqueous solution forms the gate as shown in Fig. 1(a) inset (see Methods for film deposition and measurement details). Fig. 2(a) shows the dependence of equivalent oxide thickness (EOT) of the dual gate dielectric stack on HfO2 thicknesses (dHfO2) with 1.5 nm thick as-grown SiO2. Two linear equations fit the data, where the y-intercept at dHfO2 = 0 nm determines the SiO2 thicknesses. For dHfO2 < 2 nm, the y-intercept determines the SiO2 thickness of 1.8 nm that is thicker than 1.5 nm thick as-grown SiO2, thus indicating additional SiO2 has grown during post deposition anneals. For dHfO2 >2 nm, HfO2 dielectric constant εHfO2 = 18 and SiO2 thickness of 1.5 nm is estimated from the linear fit (dashed line), thereby indicating that the HfO2 film is continuous with minimal SiO2 growth.

Hence, the target HfO2 thickness = 3 nm is selected since thicker HfO2 is

undesirable due to increasing dielectric relaxation currents and charge trapping that induce increased signal drifts at short times.21,25 Fig, 2(b) shows that the hysteresis (∆VHys) decreases with increasing SiO2 thickness; ∆VHys is the flatband voltage shift during the double sweep of capacitance versus voltage curves.

Since hysteresis increases with increasing interfacial trap

density, the target dSiO2 = 2 nm with ∆VHys ~ 0 mV is selected.

Nanowire FET sensor array design. Each chip has an array of 24 individual nanowire FET sensors with 10 µm spacing between neighboring nanowires. Based on Figures 1 and 2 discussions, the nanowire FET sensor is selected to have a silicon nanowire of 30 nm width and height and 5 µm length. The both ends of nanowire (100 nm on each side) are doped to form part of source and drain regions, resulting in channel length of 4.8 µm length. The dual layers of SiO2 (= 2 nm) and HfO2 (= 3 nm) forms the gate dielectric covering the nanowire. HfO2 is the 8


Page 8 of 40

Page 9 of 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

sensing surface with the aqueous solution forming the tri-gate that is underlapped with respect to the channel length. An important sensor array feature is that the HfO2 film is present only on nanowire surfaces and all other surrounding surfaces are comprised of SiO2.

Presence of

dissimilar surfaces enables the sensing surface to be selectively functionalized so that the target molecule would bind only to the sensing surface. This feature is important for biomolecule detection at extremely low (1000 times) larger area compared to the nanowire sensing surface, no or very few target biomolecules would bind to the nanowire surface at low concentrations if there is no selective functionalization of the nanowire surface. Hence, this feature of dissimilar surfaces is included to enable selective nanowire surface functionalization despite increase in the fabrication complexity as discussed later in Fig. 4(d).

9


ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

I. Top Si layer (nanowire) height definition

III. Gate dielectric (SiO2/HfO2) & SiN depositions

II. Top Si layer patterning

V. P+ dopant implant/ activation & silicidation

IV. HfO2 / SiN patterning over nnaowires

Silicon

Page 10 of 40

SiO2

HfO2

SiN

VI. SiO2 (TEOS) deposition & patterning; SiN removal

NiPt Silicide

Figure 3: Sequential processing modules for fabricating CMOS compatible silicon nanowire FET on 8” SOI wafers; top-down (upper) and cross-sectional (lower) schematics are shown for each module. The FET sensor has a silicon nanowire (5 µm long, 30 nm wide and high) with the gate dielectric stack of 2 nm thick SiO2 and 3 nm thick HfO2 layers covering the nanowire on all three sides. Each chip has 24 individual nanowire FET sensors with 10 µm spacing. Drawings are not to scale.

10


Page 11 of 40

(a)

(b) 30 nm

30 nm

(c)

Before

After

HfO2

5 nm

SiO2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Si

Si (E)

(d)

Si

(f)

(e)

Si SiN

(g)

(h)

(i)

HfO22 HfO Si

Si

SiO2

SiO2 10 nm

Figure 4: Silicon nanowire FET images before and after fabrication improvements. (a) Top-down SEM images of a silicon nanowire before (left) and after (right) nanowire sidewall roughness minimization. (b) Cross-sectional TEM images of silicon nanowire sidewalls before and after sidewall roughness minimization and damaged nanowire surface removal. (c) A cross-sectional TEM image of a nanowire with SiO2/HfO2 gate dielectric showing additional non-uniform SiO2 growth that occurs during the dopant activation anneal; the image is recorded before the SiN hard mask optimization. (d) Top-down SEM images of FETs with electron-beam lithography alignment errors, where the patterned HfO2/SiN stacks are completely (left) and partially (right) misaligned with respect to underlying silicon nanowires. (e) Top down SEM images of three randomly selected patterned HfO2/SiN stacks with minimal misalignment after the electron beam lithography exposure optimization. (f) A cross-sectional TEM image showing a nanowire FET with residual SiN on both sides of a nanowire. (g) A cross sectional TEM image of a 11


ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

SiO2/HfO2 covered silicon nanowire, where part of HfO2 layer (as indicated by the arrow) is removed due to the over etching of the SiN hard mask. (h) A cross-sectional TEM image of a silicon nanowire FET fabricated using the improved process. (i) A cross-sectional TEM image of the Si/SiO2 interface of a nanowire FET fabricated using the improved process.

Silicon nanowire FET fabrication improvements. Silicon nanowire p-type FETs are fabricated on commercially available 8’’ silicon on insulator (SOI) wafers with 145 nm thick buried oxide and 55±0.2 nm thick top silicon layer of low (~5x1015 cm-3) doping. Fig. 3 illustrates the six sequential processing modules for fabricating silicon nanowire FET sensors. This section focuses on fabrication improvements, whilst processing details are discussed in Methods section. In module I, the nanowire height is defined by etching back of the top silicon layer (SOI). The main challenge is to ensure that the etched SOI thickness is uniform to achieve minimal nanowire surface area variations. The initial SOI thickness of 55±0.2 nm is thinned to 31±0.9 nm, as estimated from 49-point ellipsometry measurements across the wafer (see Fig. S2 in Supporting Information). In module II, the main challenge is to form 3-dimensional silicon nanowires with minimal sidewall roughness and etch-induced damage, essential for achieving optimal Si/SiO2 interface with negligible defect densities. Since both electron beam lithography (EBL) and etch require higher levels of process control and optimization at nanoscale (

Silicon Nanowire Field Effect Transistor Sensors with Minimal Sensor

Recommend Documents