NANO LETTERS
Silicon p-FETs from Ultrahigh Density Nanowire Arrays
2006 Vol. 6, No. 6 1096-1100
Dunwei Wang, Bonnie A. Sheriff, and James R. Heath* DiVision of Chemistry and Chemical Engineering, California Institute of Technology, Pasadena, California 91125 Received December 28, 2005; Revised Manuscript Received March 21, 2006
ABSTRACT Statistical numbers of field-effect transistors (FETs) were fabricated from a circuit of 17-nm-wide, 34-nm-pitch Si nanowires boron doped at a level of 1018 cm-3. Top-gated 4-µm-wide Si nanowire p-FETs yielded low off-currents (∼10-12 A), high on/off ratios (105−106), good on current values (30 µA/µm), high mobilities (∼100 cm2/V−s), and low subthreshold swing values (∼80 mV/decade between 10-12 and 10-10 A increasing to 200 mV/decade between 10-10−10-8 A).
Semiconductor nanowires (NWs)1 have the potential for applications that include logic and memory circuitry, photonics devices, and chemical and biomolecular sensors.2-5 Although many different types of semiconductor NWs have been investigated, Si NWs have become the prototypes because they can be readily prepared, the Si/SiO2 interface is chemically stable, and Si NWs are utilized in a number of device demonstrations that have well-known silicon technology-based counterparts.2,6,7 Various techniques have been developed to synthesize semiconductor NWs, including the materials method known as vapor-liquid-solid (VLS) growth,2,6 and the templating method known as superlattice nanowire pattern transfer (SNAP).8,9 Each method has advantages. The VLS technique can produce bulk quantities of semiconductor NWs, but those NWs are characterized by a distribution of lengths and diameters, and they also must be assembled into the appropriate device structure (or the device structure must be constructed around the nanowire10). However, VLS NWs may be prepared with various doping configurations,11 and they may be studied on a variety of different substrates.12 The SNAP process can be applied to the production of both metal and semiconductor NWs. Those NWs are characterized by extremely narrow width distributions, they can possess aspect ratios of up to 106, and they are prepared as highly defined arrays with near atomic control over NW width and pitch.8,9 In addition, the growth of VLS Si NWs relies upon a metal particle to seed the growth, and that particle can also serve as an impurity dopant.6 In contrast, SNAP Si NWs are prepared from thin-film materials, and so the purity of the NW is limited only by the purity of the thin film. In any case, the ultimate test of the quality of a * To whom correspondence
[email protected]. 10.1021/nl052558g CCC: $33.50 Published on Web 05/02/2006
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NW is based upon its electronic properties. For VLS Si NWs, field-effect transistors (FETs) with high mobilities and low subthreshold swings have been reported by the Lieber group.7,12 The DC transport characteristics of heavily doped SNAP Si NWs have been reported, and those wires exhibited bulklike conductivity characteristics.13 A key toward achieving that result was the use of spin-on-dopants (SODs). SODs, which have found uses in devices such as thin-film transistors,14 provide a means for controlling doping levels while avoiding the damage that can occur through alternative methods, such as ion implantation. In this letter, we optimize SOD for the production of SNAP Si NW FETs. For p-type FETs, we find high carrier mobilities, high on-current, excellent on/off ratios, and a low subthreshold swing of hole carriers. These results reveal that the SNAP Si NWs have low defects, low surface and interface states, and should eventually operate as extremely high-performance FETs.15 Si NW FETs were fabricated from an intrinsic, 320-Åthick silicon-on-insulator (SOI) film (〈100〉 orientation) (Simgui, Shanghai, China) with a 1500 Å buried oxide. After thorough cleaning and rinsing with DI H2O, the substrate was coated with p-type spin-on dopants (SODs) (Boron A, Filmtronics, Inc., Butler, PA). Dopants were diffused into the SOI film using rapid thermal processing (RTP) at 800 °C for 3 min. Four-point resistivity measurements, correlated with tabulated values, revealed a doping level of ∼1018/cm3. We selected this doping level because, for (macroscopic) Si transistors, it produces reasonable mobility values (∼100 cm2/V‚s for bulk Si),16 good on/off ratios (>105) and high on currents (∼1 mA/µm). Higher doping levels lead to lower mobilities, and lower doping levels lead to reduced on-current values. Arrays of SiNWs were defined by the SNAP technique described previously.8 SNAP translates the atomic control
achievable over the individual layer thicknesses within an MBE-grown GaAs/AlxGa(1-x)As superlattice into a similar level of control over NW width and spacing. It can be utilized to produce highly aligned, high-aspect-ratio arrays of metal or semiconductor NWs. For example, arrays containing up to 1400 metal or Si NWs have been prepared. Each NW can be as long as a few millimeters. Semiconductor and metal NW widths down to 10 and 8 nm have been demonstrated, respectively.8 The NW pitch can be controlled with equal precision, and full-pitch values as small as 16 nm have been demonstrated. Briefly, a superlattice consisting of 800 layers of alternating GaAs and AlxGa(1-x)As thin films was prepared (IQE, Ltd. Cardiff, U.K.). The superlattice was cleaved, and the exposed edge was immersed in NH3/H2O2/H2O (1:20:750 v/v) for a few seconds to selectively etch the AlxGa(1-x)As regions. The resulting edge of the superlattice consists of GaAs ridges separated by AlxGa(1-x)As recessions. Pt metal was deposited using e-beam evaporation onto the edge of the GaAs ridges, with the edge of the superlattice held at a 45° angle to the incident flux of Pt atoms. The Pt-coated superlattice edge was then brought into contact with the doped SOI substrate overcoated with a thin-film PMMA/ epoxy (1:50 wt/wt) that was spun coated (8000 rpm, 30 s) just prior to the pattern transfer. The superlattice/epoxy/SOI assembly was dried on a hot plate (85 °C, 30 min), and the superlattice was then released by a selective etch in H3PO4/ H2O2/H2O (5:1:50 v/v) solution, leaving a highly aligned array of 400 Pt NWs on the surface of the SOI substrate. These Pt NWs served as masks for a reactive ion etch (RIE) process to produce aligned, single-crystal Si NWs. The Pt NWs were then removed using aqua regia to produce an array of 400 Si NWs at a pitch of 34 nm and width of 17 nm (Figure 1A). After Si NW formation, the substrate was cleaned in Piranha (H2SO4/H2O2 ) 4:1) and ALEG (Mallinckrodt Baker, Phillipsburg, NJ) solution to remove contaminants introduced during processing. Then it was treated with an O2 plasma (20 W, 15 mTorr, 2 min) to complete the cleaning process. The Si NW arrays were then sectioned, using e-beam lithography (EBL) and standard processing techniques, into several individual 400 NW arrays, each a few micrometers long. Source (S) and drain (D) contacts were then patterned using EBL. Prior to metal deposition, the EBL exposed areas were treated with ×100 diluted BOE solutions to remove oxides and promote the formation of Ohmic contacts. 200 Å Ti and 500 Å Pt were evaporated as S/D contact metals. Other metal contacts such as Al, Cr, and Ni were also tested, with Ti yielding the best results because of the relatively high work function of Ti and an excellent thermal stability upon annealing. As-made devices were characterized as standard fieldeffect transistors (FETs) by utilizing the underlying Si wafer as a bottom gate electrode (Figure 2A and B). Large variations in on-current and on/off switching amplitudes characterized these devices, suggesting the possible presence of defects. Defects can damage performance in a number of ways: they can act as scattering centers that reduce carrier Nano Lett., Vol. 6, No. 6, 2006
Figure 1. (A) High-magnification SEM image of Si NWs produced by the SNAP technique. Each NW is 17 nm wide, and the array is patterned at a 34 nm pitch. (B) SEM image of a few devices with the top gate color-coded red. Scale bar: 50 µm. (C) Schematic drawing of the active area of a Si NW FET, with the electrodes labeled.
mobilities (leading to lower transconductance and lower oncurrent values) and they can also serve as charge traps that degrade gating efficiency (poorer on/off ratios and large subthreshold swings).16 The device performance could be improved significantly through a forming gas (5% H2 in N2) anneal.17 Prior to annealing, surface-adsorbed H2O was removed to eliminate oxidation and charge traps that can be caused by H2O.18 This was done by spin coating PMMA onto the surface and baking at 130 °C for 30 min. Afterward, PMMA was stripped off in acetone and the substrate was annealed in forming gas at 475 °C for 5 min. FET performance characteristics, again using the Si wafer as a back gate, were assessed and compared with as-made Si NW FETs. Significant improvements in both on-current and on/ off ratios were observed with this treatment (Figure 2A and C). The off-current was also decreased to the same level (∼100 pA) for all of the devices examined. This improve1097
Figure 2. Performance characteristics of Si NW FETs for different processing conditions and device configurations. (A) Source-todrain (IDS) current values vs applied gate voltages for an as prepared, back-gated FET (black trace), a back-gated FET post forming gas anneal (red trace), and a top-gated FET post forming gas anneal. VDS ) -1 V, and the distance between S/D contact is 4 µm () top gate width). This particular device consists of 8 NWs. (B-D) Histograms for each of the device parameters shown in A, but representing statistical numbers of device measurements. Relatively fewer top-gate devices were measured because of the fabrication yield of the top-gate processing steps.
ment was uniform over three batches of samples and over more than 20 devices. The H2O removal step is important; without this step the improvement is limited and the results inconsistent. Other conditions, such as longer annealing times and higher temperature anneals (650 °C), resulted in device degradation due to Si/metal interdiffusion. Annealing in N2 (as opposed to forming gas) yielded only limited improvement. The observed improvement of the Si NW FETs following the anneal step can originate from the removal of surface and/or Si/SiO2 interfacial states, or through the formation of a semiconductor/metal alloy at the S and D contacts. It is well known that a forming gas anneal can reduce defects in Si MOSFETs.16,17 During annealing, Si/SiO2 interface dangling bonds are terminated by H2 in forming gas and charge traps diffuse out, leading directly to increased on-current and improved on/off ratios. The effect of producing a metal/semiconductor alloy at the NW/contact interface would be a decreased Schottky 1098
barrier height. This would typically be manifested as an improved on-current. It is unlikely, however, to reduce offcurrent significantly. We noticed that similar device performance enhancements (i.e., higher on-current and higher on/ off ratios) could be obtained by carrying out the forming gas anneal of the SNAP Si NWs prior to metal contact deposition. Therefore, we speculate that the charge trap removal plays the most important role. Cui et al. have also reported on the effectiveness of a much higher temperature forming gas anneal on VLS grown Si NW FETs.7 The current through our devices (at low VDS) did vary linearly with NW length, as was reported previously for heavily doped SNAP NWs.13 For careful studies of the SNAP Si NW FETs, local gates with relatively thin gate dielectrics were fabricated on top of Si NWs (Figure 1B and C). For this process, the samples that already had S/D contacts and had been treated with forming gas were loaded into an e-beam evaporator for deposition of an Al2O3 gate dielectric. The deposition was carried out in an O2 atmosphere (1 × 10-5 Torr) at a rate of 0.1 Å/s, and a total thickness of 100 Å was deposited. PMMA was then spun-coated and EBL was utilized to define the gate electrodes. The gate electrodes (e-beam evaporated 100 Å Ti and 500 Å Pt) overlapped with the S/D contacts (Figure 1C). The evaporated Al2O3 provided a good isolation of the metal electrodes: no leakage was observed between the overlapped S/D and gate electrodes. Devices were characterized with these top gates (Figure 2A and D). In comparison with the bottom gated devices, the off-current of top-gated devices is decreased greatly, hence increasing the on/off ratios by more than 1 order of magnitude (Figure 2). This originates not only from an improved gating efficiency through the thin Al2O3 dielectric but also from the diffusion-based SOD doping process. The distribution of dopants through the thickness of the NWs follows the 1D diffusion model.9,16,17 Therefore, most of the carriers reside near the top surface of the NWs, making a gate modulation from the top more effective. This is in accordance with our observations (Figure 2A) and indicates that the SOD-doped SiNWs are ideal for a top-gated highperformance FET device. Recently, we have reported on the use of these NWs as highly sensitive biomolecular sensors, detecting as little as 200 attoM concentrations of specific DNA oligomers in 0.15 M electrolyte solutions.15 It is likely that some of this sensitivity arises because the DNA hybridization events occur near the top surface of the NWs, where most of the charge carriers reside. Once the device has a top gate, the bottom gate modulation is weak compared with the top gate (see the Supporting Information). For many reported high-performance NW or nanotube (NT) FETs,19,20 the gate electrode surrounds the sides and the top of the NW or NT, forming a “multigate” structure. Such a gate can improve the performance of the FETs, but it is impractical when the starting circuit consists of very high-density NW arrays because the deposited gate materials do not penetrate into the very narrow spaces between the NWs. Typical drain current versus gate voltage (IDS-VGS) and IDS versus drain voltage (VDS) data are plotted in Figure 3. Nano Lett., Vol. 6, No. 6, 2006
using the dimensions of our device. The mean mobility value of ∼100 cm2/V‚s is close to the bulk Si value for a doping level of ∼1018/cm3. An additional figure of merit is the subthreshold swing (S), which is defined as:16 S)
Figure 3. High performance, top-gated p-type Si NW FETs. (A). IDS-VGS characteristics at different bias source-drain biases. The dashed line represents the fitted subthreshold slope value of 83 mV/ decade. (B). IDS vs VDS at different gate voltages, from -3 V (darkest colored trace) to 1 V (lightest colored trace), at 0.5 V/step. At least 5 µA current can be driven through a single device (consisting of ∼8 NWs) without noticeable degradation while the experiments are carried out under ambient conditions without precautions to prevent oxidation. (C and D) Statistics from topgated Si NW FETs for both carrier mobilities and for transconductance.
Several quantities can be extracted from these plots. First, the on-current of the devices is high. As shown in Figure 3A and B, we obtained 5 µA on-current through an individual device consisting of ∼8 NWs. Considering that each NW is ∼17 nm wide × 30 nm high in cross-section, the current density equals ∼1.3 mA/µm2 (or an on current level of 30 µA/µm). This does not represent a fully saturated current value because we held the VDS value at -2.5 V to keep within a safe operation range of the thin (10 nm) Al2O3 gate dielectric. Furthermore, the effectiVe height of the NWs is significantly less than 30 nm: measured dopant profiles through the thickness of the SOI film indicate that the majority of the carriers reside within the top 10 nm of the film.9 This implies that our current density represents a lower limit and would not likely change were the SOI film only 10 nm thick. The current density can likely be increased through, for example, the incorporation of high-κ gate dielectrics through atomic layer deposition.21 A second positive characteristic was the large on/off current ratios measured, typically from 105-106 (Figure 2D). In addition, the measured on-current levels exhibited less than twofold variations from device to device. These results confirm the statistical significance of the performance characteristics of SNAP Si NW FETs. The mobility and transconductance values of each device were calculated following literature methods,20 and those values are summarized in Figure 3C and D. We estimated the gate capacitance as originating from a simple parallel plate capacitor with an Al2O3 dielectric, Nano Lett., Vol. 6, No. 6, 2006
[ ]
Ci kT ln10 1 + q C
(1)
where C is the entire gate capacitance and Ci includes the component of the capacitance that arises from interface states and parasitic capacitance: when Ci ) 0, ideal behavior is obtained. A low S is desired for low power operation and can be obtained only with low defect density devices. In addition, for the case of NW sensors, minimizing S can maximize the sensitivity. We extracted the S values of our devices using literature methods for NWs and NTs.22,19 Different from conventional MOSFET devices, NW and NT FETs often exhibit a nonlinear subthreshold slope, which is attributed to a competing mechanism between tunneling and thermionic emission. Thus, Koo et al.19 and Appenzeller22 extracted a subthreshold slope in the range of 10-12-10-15 A for NW and NT FETs, respectively. Over that range, our highest performing device yielded an S value of ∼80 mV/ decade. If we extract the S in the range of
