Letter www.acsami.org
Simple Interface Engineering of Graphene Transistors with Hydrophobizing Stamps Soo Sang Chae,†,‡ Won Jin Choi,†,‡ Cheol-Soo Yang,‡ Tae Il Lee,*,§ and Jeong-O Lee*,‡ ‡
Advanced Materials Division, Korea Research Institute of Chemical Technology (KRICT), Daejeon 34114, South Korea Department of BioNano Technology, Gachon University, Seongnam, Gyeonggi-Do 13120, South Korea
§
S Supporting Information *
ABSTRACT: We demonstrate a simple surface engineering method for fabricating graphene transistors by using hydrophobizing stamps. By simply contact-printing hydrophobizing stamp that is made with polydimethylsiloxane (PDMS) on a standard silicon substrate for a certain contact-time, it was possible to control the contact angle of the substrate and electrical characteristics of the graphene transistors supported on the substrate. Moreover, graphene transistors supported on the engineered silicon substrate showed improved performances, including an increase in carrier mobility and loss of hysteresis. As a proof-of-concept experiment, a simple logic gate operation was demonstrated by connecting a pristine graphene device with an interface-engineered device.
KEYWORDS: graphene, polydimethylsiloxane, hydrophobizer, transistor, interface engineering raphene emerged as a “pioneer” of the 2D material era, and has great potential for applications in electronics and other fields because of its excellent electrical characteristics. Having a thickness of a single atom, graphene displays quantum mechanical transparency behavior that had never previously been reported. For example, graphene is optically transparent even though there is no energy band gap, and it has thus become an ideal candidate for use as a flexible transparent electrode.1 Graphene has also been reported to be transparent to electrons, which have been shown to penetrate graphene to make charge-transfer interactions.2 However, these types of transparency displayed by graphene lead to an unwanted strong dependence of electronics properties of graphene on the electronic state of a given substrate on which graphene is supported, and such a dependence may be a serious obstacle for electronic device applications. In particular, the charge carrier mobility of graphene has been shown to be degraded on commonly used SiO2/Si substrates, which provide numerous scattering centers and charge-trapping sites for the deposited graphene.3 To overcome this issue, various approaches have been developed and introduced to engineers working on electronic device fabrication using graphene. A promising substrate involves hexagonal boron nitride (hBN), which is an ideal interface dielectric for graphene devices.4,5 However, large-scale synthesis of uniform hBN is not trivial,6,7 and the methods used to directly grow graphene on hBN also need to be further improved.8 Another approach involves using a substrate covered with a self-assembled monolayer (SAM) of organic molecules.9 SAM technique does not involve high temper-
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© XXXX American Chemical Society
atures, and could be a cost-effective alternative to hBN, so this technique has been an attractive option for many researchers. Lee et al. studied the relationship between the carbon chain length of SAM molecules and the charge carrier mobility in graphene devices supported on these molecules and confirmed an increase of the mobility with increasing chain length.10 Cernetic and colleagues investigated the effect of binding groups, packing density, and dipole magnitude/directions of SAMs11,12 and concluded that graphene devices could be systematically controlled by the z-component of the SAM dipole. Furthermore, SAM-induced interface engineering is not only useful for enhancing the performance of graphene devices, but also could be used for various electronic applications. For example, p−n junction devices using SAM-based interface engineering13 and the possibility of spatially controlling graphene functionalization by patterning the substrate with a SAM14 have been reported. Despite the above-mentioned advantages, SAM-based interface engineering may not ensure the long-term stability of a graphene device because SAM molecules may degrade in ambient conditions.15 Here we describe an interface engineering strategy based on a polydimethylsiloxane (PDMS) hydrophobizing stamp as an alternative to the use of SAMs. Un-cross-linked low-molecular weight (LMW) PDMSs have recently been shown to diffuse out of bulk PDMS stamps and onto the target contact surface and make it hydrophobic.15,16 It could be a drawback for soft Received: February 22, 2016 Accepted: May 30, 2016
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DOI: 10.1021/acsami.6b02166 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
Figure 1. Interface engineering of a SiO2/Si substrate when using the hydrophobizing stamp. (a) Schematic set of diagrams showing the different steps of the hydrophobizing stamp method. (b) Fractions of Si−C and C−H found on the engineered substrate as a function of the contact time with the stamp. (c) Dependence of the surface energy on the contact time with the hydrophobizing stamp.
lithography based on contact printing, but it could also be used as a stable surface modifier for various applications.17−19 By using a PDMS stamp instead of a SAM treatment, we can tailor the carbon fractionand hence the hydrophobicityof the surface of the substrate without introducing other chemical elements such as F and N that are usually included in the SAM. And one more attractive characteristic of the PDMS-based hydrophobizer is that it is more stable than any other SAM even in harsh conditions. This property could be a beneficial when the sample undergoes extra processes such as postannealing and wet etching. Chae and colleagues showed that the PDMS-derived hydrophobizer exhibits superior thermal and chemical stability; it showed robust hydrophobization characteristics throughout the pH range of 2−13 and up to 300 °C, whereas most of the investigated SAMs were observed to lose their ability to modify surfaces at the extremes of these conditions.20 In this study, we systematically engineered the surface states of SiO2/Si substrates using PDMS contact printing by modulating the percentage of the surface of the substrate occupied by LMW PDMSs. In this effort, we also investigated the behavior of graphene on the engineered substrates by using X-ray photoelectron spectroscopy (XPS), contact angle measurements, Raman spectroscopy, and electrical transport measurements. Finally, we demonstrate a simple logic device operation, by integrating a pristine graphene transistor with a device fabricated on interface engineered substrates by using hydrophobizer. Graphene was grown using the low-pressure chemical vapor deposition (LPCVD) method on a Cu foil, and wet-transferred to a target substrates with a poly(methyl methacrylate) (PMMA) support. Hydrophobizing stamps were first made by mixing ten parts Sylgard 184 (Dow Corning Chemicals, MI, USA) prepolymer and one part curing agent. The mixed PDMS was poured onto an atomically flat silicon substrate and cured at 80 °C for 4 h, and then cut into pieces for interface engineering. Before the substrate engineering, the PDMS stamp was pretreated with oxygen plasma for 1 min at 80 W (Covance, FEMTO Science). The fabricated hydrophobizing stamps were placed onto silicon substrates with a 300 nm thick
layer of thermal oxide, and held for various contact times before removing them from the substrates. To investigate the effect of the oligomeric PDMS hydrophobizer, the above contact printing could be repeated multiple times, and used as engineered substrates for graphene. Figure S1 shows longterm stability of PDMS hydrophobizer in air and in water conditions. Both in air and water conditions, PDMS hydrophobizer exhibited stable hydrophobizing characteristics until 14 days. Graphene devices were constructed on pristine, and interface engineered substrate using photolithography, metallization with Cr (5 nm)/Au (30 nm), and oxygen plasma etching. Dimensions of such fabricated devices are 100 μm long and 50 μm wide. Details regarding graphene growth, transfer, and device fabrication are shown in the Supporting Information. Figure 1a shows a schematic of the use of the PDMS hydrophobizing stamp in carrying out the interface engineering in this work. Un-cross-linked LMW PDMS slowly diffused out of the bulk PDMS and deposited on SiO2/Si. Because a continuous film of LMW PDMS typically was obtained with a contact time of near 30 min, we tested contact times of 1 s, and 1, 3 and 30 min. The surface coverage of LMW PDMS for each contact time was measured by atomic force microscope (AFM) and the results are shown in the Figure S2. The occupying ratio of LMW PDMS on SiO2/Si clearly increased with contact time, indicating that the surface gradually changed from silica to PDMS. Here, deposition rate of the LMW PDMS may also be controlled by changing the mixing ratio of PDMS stamp as shown in the Figure S3. In addition, the change in the chemical composition of the engineered surface was quantitatively determined by using XPS, and the results are shown in Figure 1b. The raw data for the XPS spectra are shown in the Figures S4 and S5. The increasing fractions of C−H and Si−C signals with time indicated an increase in the amount of the SiO2/Si surface covered by PDMS. Moreover, a linear relationship between these fractions and the log of contact time was observed, and this unexpected result provides engineers with the ability to control the surface energy of a given substrate when a particular surface energy value is required. B
DOI: 10.1021/acsami.6b02166 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
Figure 2. Electrical transfer characteristics of graphene devices fabricated on the engineered substrates. (a) From top to bottom: liquid-gate transfer characteristics of graphene devices fabricated on a bare SiO2 substrate (ref), and liquid-gate transfer characteristics of graphene devices fabricated on SiO2 substrates treated with the hydrophobizing stamp for 1 s (PDMS1), 1 min (PDMS2), 3 min (PDMS3), and 30 min (PDMS4), respectively. Inset figure in the top graph shows a schematic of the measurement setup. All measurements were done with 10 mV bias voltages. (b) Measured topgate hysteresis values (c) charge neutrality points (Dirac points), and (d) hole-mobility values are shown for the various hydrophobizer treatment contact times.
(PDMS2), 3 min (PDMS3), and 30 min (PDMS4). As shown in the figure, the reference device showed very poor transfer characteristics; no charge neutrality point (CNP) was observed even with a liquid gate, and the mobility value deduced from the transfer curve was rather low (≲1000 cm2/(V s)). The mobility values were calculated according to the previous report by Fu and colleagues.16 However, upon engineering the substrate with the hydrophobizer, the charge neutrality point began to move to the zero gate bias, and the mobility value also increased with longer hydrophobizer treatments. Figure 2b−d summarizes the relationships between the duration of the hydrophobizer treatment and the hysteresis, position of the CNP, and mobility values, respectively. As shown in the figures, the Dirac point shifted from positive gate voltages toward zero, and was about 0 V for 30 min of hydrophobizer treatment. Hysteresis almost disappeared at this point, even though the measurement was performed in ambient atmospheric conditions. We also compared contact resistances of graphene devices to give credibility to measured mobility values. As shown in the Figure S6, contact resistance measured from graphene device on engineered substrate fall in the similar range to that of pristine graphene device: graphene devices
To determine the range of surface energy values that can be imparted onto the engineered substrate through our hydrophobizing stamp approach, we measured the surface energy density values of our engineered substrates by using a contact angle analyzer. Figure 1c shows the surface energy as a function of the contact time. The surface energy density of SiO2 used in this work was measured to be 68.24 mJ/m2. As the coverage of LMW PDMS on the surface increased, the surface energy decreased from 39.48 to 13.46 mJ/m2, which is about the same as that of bulk PDMS. Lowering the surface energy makes the surface of the engineered substrate electrostatically smoother; and we can thus expect to be able to modulate the Dirac point of the graphene transistor on the engineered substrates with the PDMS hydrophobizer. Using the engineered substrates in Figure 1, graphene devices were fabricated and their electrical transport characteristics were compared in a top-gate geometry using 1-butyl-3methylimidazolium hexafluorophosphate ([BMIM][PF6]) as the gate electrolyte and Pt wire for the gate electrode. (inset figure in Figure 2a). Figure 2a shows transfer characteristics of graphene devices supported on a bare SiO2/Si reference substrate, and on the substrates treated with the hydrophobizer printing for 1 s (denoted in the figure as “PDMS1”), 1 min C
DOI: 10.1021/acsami.6b02166 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
Figure 3. Raman spectra of graphene supported on engineered substrates. (a) Distribution of the FWHMs of the Raman G peaks as a function of G peak position (PosG). Blue circles are for the reference devices (those on bare substrate), black squares for PDMS1, violet triangles for PDMS2, magenta inverse triangles for PDMS3, and red diamonds are for PDMS4. (b) Distribution of FWHMs of the 2D peaks as a function of 2D peak position (Pos2D). (c) Correlation between the G and 2D positions of graphene on the engineered substrates. (d) The ratio of the 2D peak intensity over G peak intensity (I2D/IG) as a function of G peak position.
Figure 4. Simple logic gate fabricated with the hydrophobizer engineering. (a) Optical microscope image of the device. While the top transistor device was heavily hole doped by the bare silicon oxide substrate as shown in the band diagram, the bottom transistor device, which was made on the hydrophobizer-engineered substrate, exhibited the Dirac point at zero gate bias (scale bar is 50 μm). (b) Equivalent circuit diagram of the device in panel a. (c) Measured inverter performance of the engineered device.
graphene supported on SiO2 substrates show relatively large spatial variations; the positions of G and 2D, and the full widths at half maximums (FWHMs) of the G and 2D peaks show large spatial variations. Such position-dependent Raman spectra may be attributed to the polycrystalline nature of CVD graphene, yet it is more likely due to doping effects from SiO2 substrates
fabricated on engineered substrate exhibited the more uniforms values. We also investigated the effect of hydrophobizer treatment by measuring Raman spectra of graphene supported on SiO2/Si substrates with varying hydrophobizer treatment times. Normally, Raman spectra measured from large-area CVD D
DOI: 10.1021/acsami.6b02166 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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graphene devices systematically by varying the duration of stamping, various electronic device applications such as inverter devices could be fabricated as shown in this work. Besides, instead of controlling contact time, it is possible to use repeated contact method that can be further extended to roll-to roll process as shown in the Figure S9. Being a simple method that can be scaled up and that uses a device that has been shown to display long-term stability, the PDMS-based hydrophobizing stamping technique could be applied to a variety of applications.
since defect-related Raman peaks (D peak) are negligible throughout the entire regions of graphene surfaces. As shown in Figure 3, while the positions and FWHMs of the G and 2D peaks showed wide distributions in the reference device and PDMS1, devices stamped with the hydrophobizer for 3 min (magenta inverse triangles) and 30 min (red diamonds) exhibited much narrower distributions. The dotted lines in Figure 3 are visual guides, and highlight the change of the Raman signal distribution with hydrophobizer treatment. In Figure S7, we compared Raman deviation map images for G position, G intensity, and 2D intensity in pristine and hydrophobizer engineered graphene devices. As shown in the images, Raman spectrum shows more uniform distribution for graphene on engineered substrate. The observed changes with hydrophobizer treatment may be quantitatively explained as follows. Pristine SiO2 surfaces are mostly hydrophilic, and are terminated with -SiOH groups. As reported by Yang et al. and Nagashio et al., silanol groups on the surface may induce a significant charge redistribution and act as scattering centers.17,18 Upon hydrophobizer treatment, a surface on which graphene will be supported becomes functionalized with −CH3 groups, and hence becomes more hydrophobic. As shown by Chen et al. using density functional theory, the electronic properties of graphene strongly depend on the underlying SiO2 surface properties and the percentage of hydrogen passivation. 21 The Figure S8 shows surface functionalization with −CH3 groups and expected surface energy changes (calculations and measured data). To calculate the surface energy of heterogeneous substrates, simple Cassie’s law has used.22 From this, one may expect that ∼90% of the surface was terminated with − CH3 groups after the hydrophobizer treatment for 30 min. Certainly, we cannot completely ignore the effects of surface topography since surface roughness increases with hydrophobizer treatment. However, increase in surface roughness with hydrophobizer treatment is rather small (Figure S2), and considering that topographic substrates cause degradation in carrier mobilities of graphene devices, the effects of hydrophobizer treatment are mostly coming from the chemical compositions of the substrate. Finally, we explored the potential of applying the hydrophobizing stamping technique by constructing a graphene logic device. Since pristine graphene device supported on SiO2 shows heavily hole-doped behavior, a pristine graphene device connected with a hydrophobizing stamped device may function as an inverter. Figure 4a shows an optical microscope image of the fabricated device. In the image, the top transistor is the pristine graphene device, which was heavily p-doped as shown in the schematic band diagram, and the bottom transistor, which was treated with the hydrophobizer, showed the CNP at zero gate bias voltages. Figure 4b shows the equivalent circuit diagram of the device. As shown in the Figure 4c, the device functioned as an inverter, with a maximum gain is ∼4. In summary, we have demonstrated a simple surface engineering method for fabricating graphene electronics devices using hydrophobizing stamps. The surface energy value of the SiO2 substrate gradually decreased with increasing amounts of hydrophobizer treatment, reaching a value comparable to that of bulk PDMS after the hydrophobizer treatment for 30 min. The electronic properties of graphene also improved when the substrate was treated with the hydrophobizer: the CNP moved to zero gate voltages, hysteresis decreased, and the mobility improved. Because it is possible to control the CNP of
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ASSOCIATED CONTENT
* Supporting Information S
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b02166. Experimental methods for growing graphene and graphene device fabrication, long-term stability of PDMS-based hydrophobizer, AFM images that show evolution of surface topography with hydrophobizer treatment, The deposition rate of the low molecular weight PDMS layer, raw XPS spectra measured from engineered substrates, Raman map images for graphene on engineered substrates, and simulated surface compositions and measured (calculated) contact angles of such substrates (PDF)
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AUTHOR INFORMATION
Corresponding Authors
*E-mail:
[email protected]. *E-mail:
[email protected]. Author Contributions †
S.S.C. and W.J.C. contributed equally to this work
Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS We acknowledge funding from the NRF-ANR program through the National Research Foundation of Korea funded by the Ministry of Science, ICT and Future planning (NRF_2011K2A1A5-2011-0031552). We also acknowledge the support by Leading Foreign Research Institute Program Recruitment through the Nation Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future planning (MSIP)(2010-00453).
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REFERENCES
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