Spatially Selective, High-Density Placement of Polyfluorene-Sorted

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Spatially Selective, High Density Placement of PolyfluoreneSorted Semiconducting Carbon Nanotubes in Organic Solvents Bharat Kumar, Abram L. Falk, Ali Afzali, George S. Tulevski, Satoshi Oida, Shu-Jen Han, and James B. Hannon ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.7b00088 • Publication Date (Web): 27 Jul 2017 Downloaded from http://pubs.acs.org on July 29, 2017

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Spatially Selective, High Density Placement of Polyfluorene-Sorted Semiconducting Carbon Nanotubes in Organic Solvents Bharat Kumar,*† Abram L. Falk,† Ali Afzali,† George S. Tulevski,† Satoshi Oida,† Shu-Jen Han,† James B. Hannon† †

IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598

*[email protected] Abstract

High performance logic based on carbon nanotubes (CNTs) requires high density arrays of selectively placed semiconducting CNTs. Although polymer-wrapping methods can allow CNTs to be sorted to a >99.9% semiconducting purity, patterning these polymer-wrapped CNTs is an outstanding problem. We report the directed self-assembly of polymer coated semiconducting CNTs using self-assembled monolayers that bind CNTs into arrays of patterned trenches. We demonstrate that CNTs can be placed into 100 nm wide HfO2 trenches with an electrical connection yield as high as 90%, and into 50 nm wide trenches with a yield as high as 70%. Our directed self-assembly method is an important step forward in pitch scaling.

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KEYWORDS: carbon nanotube· logic· transistor· CNTFET· nanotechnology

For decades, the steady improvement in transistor performance was based on Dennard scaling: shrinking the dimensions of the transistor while keeping most of the materials the same.1 More recently, industries have incorporated new materials (e.g. metal gates and high-k dielectrics) and new architectures (e.g. FinFETs). The outstanding properties of carbon nanotube (CNT)-based transistors make them a particularly promising ‘post silicon’ option for the channel material.2-4 Both the channel length and the contact size of CNT transistors can be scaled down to sub-10 nm.5,6 Complementary logic with both p-type and n-type transistors constructed on CNTs was also achieved. 7,8 Nonetheless, many material challenges must be overcome in order to realize CNT complimentary metal-oxide-semiconductor (CMOS) technology. Two of the most critical are placement and purity. For competitive high-performance logic, billions of individual CNTs must be placed at precise locations on a target substrate. In addition, metallic CNTs must be eliminated.9 Among the currently known methods for sorting semiconducting CNTs,10-12 use of conjugated polymers is an appealing method as it can isolate semiconducting CNTs directly from the raw material with high purity and concentration.13 Recent work using fluorene copolymers


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demonstrated remarkable efficiency of this sorting process, with the semiconducting purity exceeding 99.9%.14-16 Selectively placing the sorted CNTs directly onto target substrates is an important next step. Several placement methods were developed using aqueous solutions as well as organic solutions of bare CNTs.17-19 However, no placement methods are currently known to place CNTs of desired purity at the desired pitch for logic applications. To date, even the placement methods that have achieved a high placement density of individual CNTs are not compatible with polymer-wrapped CNTs. This incompatibility is because of the solvents and surfactants used for the sorting and placement methods. For example, the method developed by Park et al., which achieved a record placed density of 109 CNTs/cm2, employs surfactant-wrapped CNTs dispersed in water and exploits an electrostatic attraction between the surfactant and a surface monolayer.20 One potential solution would be to remove the polymer from the CNTs after purification and re-disperse them in water with a surfactant. However, no simple method to accomplish this change of solvent is currently known. In this work, we demonstrate a method based on surface chemistry that is designed specifically to bind polymer-wrapped CNTs dispersed in solvent. It therefore enables high-density selective placement of CNTs directly after purification with no exchange of solvent or polymer removal. In addition, our method results in higher CNT densities than the water-based methods, enabling scaling to smaller CNT pitch.20 We exploit the selective self-assembly of monolayers on patterned oxide surfaces. The starting substrates have rectangular HfO2 regions (‘trenches’) that are the target areas for the CNTs and an SiO2 ‘field’ oxide that surrounds the HfO2 trenches.20 We employ a 11-(4-aminophenoxy)-1-undecylhydroxamic acid (AMUHA) monolayer, containing a hydroxamic acid end group that selectively binds to the HfO2 regions, leaving the SiO2 regions


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bare. The in-situ conversion of the amino groups of the monolayer to a diazonium salt results in selective binding of the polymer-wrapped CNTs into narrow trenches, while maintaining excellent selectivity. The placement is characterized using both scanning electron microscopy (SEM) and electrical testing. Automated electrical testing has the advantage that thousands of devices can be efficiently measured. The primary metric that we use is the connection yield, defined as the fraction of devices that exhibit an on-state drain current greater than 1 nA at a source-drain bias of 0.5 V. We find that electrical connection yields greater than 90% can be achieved for devices made on 100 nm wide HfO2 trenches. We measure this yield from hundreds of devices on a single chip and hence, demonstrate potential uniformity of our placement over large areas. Results and discussion The CNTs used in this study were purified using a method based on the polymer extraction technique.13 A copolymer, poly[(9,9-dioctylfluorenyl-2,7-diyl)- alt-co-(6,6’-{2,2’-bipyridine})] (PFO-BPy), was used to selectively extract semiconducting single walled CNTs via a simple sonication and centrifugation process. This method leads to both high purity and high concentration. An n-doped silicon wafer with a uniform blanket film of 10 nm HfO2 was covered by 5 nm of SiO2. Standard lithographic patterning and etching were used to selectively remove SiO2 in places to form dense arrays of HfO2 trenches. The exposed HfO2 defined the target area for the CNT deposition and also served as the gate dielectric for subsequent device fabrication (the doped Si wafer was the common back gate for all devices). Each test chip was designed to have thousands of CNT transistors, with a pitch of 200 nm between devices. The trench dimensions are W x L,


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where W = 50 nm or 100 nm, and L = 750 or 1500 nm. Prior to depositing the monolayer, the substrate was cleaned by high temperature annealing in vacuum (400 ͦC for 10 mins at 10-7 Torr). The C11-monolayer AMUHA, which is known to self-assemble on HfO2, was synthesized using a published procedure.21 The CNT deposition was carried out using a one-step procedure where amyl nitrite was directly added into the CNT solution to diazotize the monolayer. After the diazotization step, polymer-wrapped CNTs were observed to bind predominately to HfO2 while binding to SiO2 was much weaker. Nearly complete removal of the CNTs from the SiO2 was achieved with a simple sonication step while retaining high CNT density in the trenches. SEM images show excellent selectivity, with CNTs found almost exclusively on the HfO2 regions (figure 1 and S4). We first tested the placement in 100 nm wide trenches with 1.5 µm and 500 nm length (figure 1). While the trench dimensions are similar to those used by Park et al.,20 the CNT density achieved here is atleast twice as high. This improvement in density allows the trench width to be further reduced while maintaining a reasonable density.


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Figure 1. SEM images of (A) 100 nm wide trenches with 1.5 µm length and (B) 100 nm wide trenches with 500 nm length (scale bar is 200 nm).

Indeed, we achieved selective placement with good density in trenches with widths as small as 50 nm (figure 2). To quantify the CNTs density in these narrow trenches, we analyzed a number of SEM images and found that the CNT density in these narrow trenches typically is 3-4 tubes/trench. SEM images recorded after etching the SiO2 field oxide also showed good alignment of CNTs along the longer axis of the trenches (figure 2b). Comparing figure 1 and figure 2, we observe that, CNT alignment significantly improves as the trench width is narrowed.


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Figure 2. SEM image of placement in (A) 50 nm wide trenches and (B) in 50 nm trenches after etching SiO2 (scale bar is 200 nm).

To understand the source of the high density and good selectivity, we systematically varied parameters of the monolayer deposition process outlined above. We used UV-Vis absorption and X-ray photoelectron spectroscopy (XPS) to investigate the role of amyl nitrite and found that amyl nitrite is essential for the diazotization and hence, the placement (figure S6). We investigated the diazotization by recording XPS spectra before and after amyl nitrite treatment (figure 3b). After amyl nitrite treatment, a new nitrogen feature appears at 409 eV corresponding to the reactive diazonium salt.22,23


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Figure 3. (A) Conversion of aniline to diazonium salt. (B) XPS spectra of N1s peak before and after addition of amyl nitrite (see also SI of reference 23).

One possibility is that the diazonium salt reacts directly with the CNT, forming a covalent bond. In fact, a very similar reaction was used by Klinke et al. to attach functional groups to CNTs for placement.21 They showed that fully-functionalized CNTs exhibit extremely low conductivity, presumably because covalent bonding disrupts the CNT band structure. Upon annealing to 600 ͦC, the CNT bonds are restored. In this spirit, we used conductivity measurements to qualitatively assess the degree of covalent bonding to the CNT (figure 4), by simply skipping the annealing step following CNT deposition. If covalent bonding is significant, the conductivity will be poor, atleast until the surface is annealed and CNT bonds are restored. We find that the on-state current (Ion, defined as the current at a 1 V overdrive relative to the threshold voltage) is similar both before and after the CNTs are annealed. The relatively similar on-state currents show that significant covalent functionalization of the CNT does not occur. The CNT-polymer solution does not show any significant changes upon addition of aniline before diazotization suggesting absence of any charge transfer interactions with aniline, whereas charge transfer interactions can be observed after diazotization (figure S8). Finally, free polymer dispersed


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in toluene does not show any change in UV absorption upon the addition of diazonium salt (figure S9), indicating that the polymer does not react with the monolayer under our placement conditions. The results of this conductivity test, combined with UV-Vis, XPS and SEM experiments indicate that the mechanism of this placement method involves a charge-transfer complexation with either CNTs, without significant covalent bonding, or to the electron-rich pyridyl containing polymer units that wrap the CNTs.24

Figure 4. Gate-transfer curves for four representative devices. The blue curves are taken from devices that were fabricated without annealing the nanotubes. The devices were then annealed at 400 ͦC for 30 minutes, and the gate-transfer curves were retaken (black curves). The drain voltage is 0.5 V (channel length is 150 nm).

As noted above, large-scale device fabrication and testing is a convenient method for characterizing the placement yield. Device fabrication is also critical for establishing that the placement process does not adversely impact device performance. Following CNT placement, we formed 2 nm Ti/40-nm thick Pd contacts using standard electron-beam lithography and metal evaporation. The doped Si substrate is used as common back gate to modulate the devices.


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The transfer curves for 368 devices with 100 nm wide trenches from a single chip are shown in figure 5a. For each device, we protected only one trench and etched away all CNTs outside that single trench with oxygen plasma. The average ‘on’ current and sub-threshold slope are 1.1 µA and 126+/-30 mV/dec respectively, which is typical for un-encapsulated CNT devices (i.e. devices in which the CNT is exposed to air).20 The connection yield for this set of devices is 89%, and no devices with metallic CNTs were observed. The distribution of the threshold voltage, Vt, is shown in the upper panel of figure 5c. These results are typical for CNTs in atmospheric conditions and show that the placement scheme does not adversely affect device performance. In actual CNT CMOS technology, it is anticipated that high-performance CNT devices will contain as many as six CNTs per channel in order to deliver sufficient drive current. 3 Measuring devices that span multiple trenches in parallel also gives us the opportunity to explore how performance and connection yield depend on the effective channel width (i.e. on the number of CNTs in the device). With the particular trench layout used here, it is possible to explore the performance of devices that span more than one trench. That is, source and drain electrodes can be patterned such that more than one trench is connected. As expected, the connection yield for the composite devices increases with the number of trenches. In addition, there is a beneficial effect of averaging on the distribution of the Vt variation, as shown in figure 5c.25 Moreover, Vt variation is also found to be similar to that of devices made by using polyfluorene-sorted CNTs.26


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Figure 5. (A) Gate-transfer curves for 100 nm-wide trenches and 1 trench connected per device. The bias voltage is 0.5 V. (B) Connection yield vs number of trenches connected in parallel. Each data point represents the best connection yield measured in a 368 device block, where 1-3 blocks were measured for each device layout. (C) Narrowing of Vt from 1 trench/device (top) to 6 trench/device (bottom) (channel length is 150 nm).

Conclusion We have demonstrated a method for selectively placing highly-purified polymer-wrapped CNTs from toluene onto patterned oxide substrates with high density. The mechanism of the placement method involves diazotization of aniline monolayers. With 50-100 nm trench widths, connection yields as high as 90% can be obtained. Large-scale device fabrication and testing has been used to quantify the placement yield. Our placement method does not significantly alter the electrical properties of the CNTs.


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Materials and Methods All chemicals were purchased from Sigma Aldrich and used without any further purification unless specified. The monolayer compound AMUHA was synthesized using a previously published procedure.21 UV-Visible spectra were recorded using a Perkin-Elmer Lamda 950 spectrometer. Scanning electron microscope images were obtained using a Zeiss LEO SEM. The 5 mM monolayer solution was prepared using 1:1 ethanol:toluene. PFO-Bpy was purchased from American Dye Source and the SWCNTs (AP-CNT) was purchased from Carbon Solutions Inc. PFO-Bpy (10 mg) was dissolved in 10 ml of toluene with gentle heating (~90 ͦC) to fully dissolve the polymer. Approximately 20 mg of SWCNTs was added to the toluene solution and sonicated with a 6 mm sonication tip (Sonics VCX 250) for 30 minutes at 1 sec pulses while being cooled in a water bath. Following sonication, the solution was centrifuged for 10 minutes at 15 krpm in a SW T41 rotor (Beckman). The top 90% of the solution was then collected and used as is. Each substrate was precleaned using vacuum annealing at high temperature (600 ͦC at 107

mTorr) and immersed in the AMUHA solution (5 mM in 1:1 ethanol:toluene) for 1 hour followed

by rinsing in copious amounts of ethanol and toluene, followed by drying under nitrogen. For the chips with 50 nm wide trenches, this step was followed by coating with HMDS (to coat the SiO2 surface) using vapor-phase deposition at 75 ͦC. 6 µl of neat Amyl Nitrite was added for every ml of CNT solution. The treated CNT solution was then sonicated at room temperature for 45 minutes prior to deposition. The substrate was dipped in the CNT solution for 1 hour and 45 minutes where the solution with the substrate was


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sonicated at room temperature for the final 45 minutes. The substrate was then rinsed with toluene, acetone and isopropanol followed by drying under nitrogen. For most of our measurements, only a single trench is contacted. The trench was isolated using a PMMA / HSQ mask and oxygen reactive ion etching to etch away CNTs in neighboring trenches (see figure S5). This procedure ensures that the conductance measures is from a single trench. For the chips with a poly-silicon trench pattern, the trench pattern is then wet-etched using NH4OH heated to 50 °C. The chips are then annealed at 400 - 500 °C for 30 minutes in a vacuum annealing tool (base pressure is ~ 10-8 torr. The device contacts are then lithographically defined (ebeam), followed by Ti (2nm) and Pd (25nm) deposition. Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Acknowledgements The authors would like to acknowledge J. Bucchignano for assistance with electron-beam lithography. Supporting Information Additional experimental details and SEM images. This material is available free of charge via the Internet at http://pubs.acs.org.


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