Steep Subthreshold Swing n- and p-Channel Operation of Bendable

Letter pubs.acs.org/NanoLett

Steep Subthreshold Swing n- and p‑Channel Operation of Bendable Feedback Field-Effect Transistors with p+−i−n+ Nanowires by DualTop-Gate Voltage Modulation Youngin Jeon, Minsuk Kim, Doohyeok Lim, and Sangsig Kim* Department of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul, 136-701, Republic of Korea S Supporting Information *

ABSTRACT: In this study, we present the steep switching characteristics of bendable feedback field-effect transistors (FBFETs) consisting of p+−i−n+ Si nanowires (NWs) and dual-top-gate structures. As a result of a positive feedback loop in the intrinsic channel region, our FBFET features the outstanding switching characteristics of an on/off current ratio of approximately 106, and point subthreshold swings (SSs) of 18−19 mV/dec in the n-channel operation mode and of 10− 23 mV/dec in the p-channel operation mode. Not only can these devices operate in n- or p-channel modes, their switching characteristics can also be modulated by adjusting the gate biases. Moreover, the device maintains its steep SS characteristics, even when the substrate is bent. This study demonstrates the promising potential of bendable NW FBFETs for use as low-power components in integrated circuits or memory devices. KEYWORDS: Field-effect transistor, silicon nanowires, subthreshold swing, sub-kBT/q switch, feedback loop, bendable substrate

H

(FBFETs), which were proposed by Hu et al., are promising candidates for next-generation switching devices.20,21 Compared to other steep switching devices, FBFETs demonstrate low SS, low operation voltage, and high Ion while maintaining simple device structure. These outstanding switching characteristics originate from the positive feedback loop that operates via control of the potential barrier height in the intrinsic channel region. Furthermore, the use of nanowires (NWs) as channels in FBFETs allows for simple fabrication of the trigate portion of a gate-all-around (GAA) structure without requiring any complicated fabrication methods.22,23 Hence, the height of the potential barrier in the channel region of an NW can be efficiently controlled. Despite the outstanding switching characteristics of FBFETs, their operation requires that high gate voltage biases be applied for several seconds so as to trap electrons and holes in the gatesidewall charge spacers; these charges are necessary to create a positive feedback loop.20,21,37 However, they may cause unintentional device degradation or failure. To overcome this hindrance to achieving a low operation voltage, alternative device structures without trapped charges are needed. Recently, S. Cristoloveanu’s group introduced a positive-feedback-loopbased steep switching device (called a “Z2-FET”) that was built on a fully depleted silicon-on-insulator (SOI) substrate.24−26 Instead of trapping charges in the gate-sidewall charge spacers,

istorically, the evolution of complementary metal oxide semiconductor (CMOS) technology has led to revolutionary progress in information technology by means of scaling down the device dimensions and scaling up the functions that a chip can perform. Recently, however, the scaling of conventional CMOS technology has reached its practical and theoretical limits.1,2 In particular, the 60 mV/dec subthreshold swing (SS) limit at T = 300 K in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been a major obstacle to reducing operating voltage and power consumption.3−5 Moreover, because leakage power will predominate the total power consumption in future CMOS technology, power management is an important consideration.6 To overcome the theoretical limits of conventional MOSFETs and to realize future low-power electronics, it is crucial that research into new types of devices and materials applicable to switching devices be performed. Steep switching devices have been attractive for overcoming the aforementioned theoretical limits.7−9 Innovative operation principles such as band-to-band tunneling, avalanche breakdown, mechanical switching, and negative capacitance have been used to propose and develop devices that demonstrate low SS values and low power consumption [e.g., tunneling FETs (TFETs),10−12 impact-ionization MOSFETs (i-MOSFETs),13−15 nanoelectro-mechanical FETs (NEMFETs),16,17 and ferroelectric negative capacitance FETs (NCFETs)18,19]. However, as a consequence of the low on-current (Ion), high operation voltage, and complicated operating principles of these devices, it remains a challenge to use them in place of MOSFETs. On the other hand, feedback field-effect transistors © XXXX American Chemical Society

Received: February 12, 2015 Revised: July 21, 2015

A

DOI: 10.1021/acs.nanolett.5b00606 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

Figure 1. (a) Schematic illustration. (b) Illustration of device cross section and channel energy band diagram of the NW FBFET in the off state. (c) Optical images of the bendable dual-top-gate NW FBFET on a plastic substrate.

Figure 2. (a), (b) IDS versus VDS characteristics of the NW FBFETs with various VGp and VGn. Note that the IDS versus VDS curves (a) and (b) were obtained from FBFET1 and FBFET2, respectively. (c) Energy band diagrams of the positive feedback loop for the NW FBFET with positive VDS.

the Z2-FET creates potential barriers via a single front gate and a back gate bias. Nevertheless, it is quite difficult to precisely control the potential barrier under the back gate structure of a single device. Moreover, the use of an SOI substrate makes it difficult to achieve bendable devices. Hence, we propose a newly designed dual-top-gate structure consisting of p+−i−n+ Si NW FBFETs on bendable substrates both to enhance the control of the potential barriers in the intrinsic channel regions and to prevent device degradation caused by a high gate bias.

Results and Discussion. An illustration of the basic structure, an energy band diagram, and optical images of a representative bendable NW FBFET are shown in Figure 1. The basic device structure consists of a channel of five parallel p+−i−n+ Si NWs, and dual-top-gate electrodes (Figure 1a,c). On the upper side of the channel region (length = 5 μm), two top-gate electrodes (width = 2.5 μm) are arranged side by side; the gate electrode located near the p+ drain region is named Gate1, and the other gate electrode, located near the n+ source region, is named Gate2. To provide a simple description of the B


Letter

Nano Letters

first one is the fluctuation in the device parameters. Like conventional FETs, device parameter fluctuation due to the position mismatches and line edge roughness of the gate electrodes, or the NW diameter variation, can occur in our NW FBFETs.31 This fluctuation significantly affects the shape of the potential barrier, including its height. The second one is the surface potential variation. The surface potential arises from the presence of randomly distributed defects in the NW channel, the gate oxide layer, or the interface region between the channel and the oxide layer. The surface potential can distort the potential barrier shape in the intrinsic channel region.32 For these two reasons, the potential barrier shape can be different for FBFET1 and FBFET2, even under the same gate bias voltage.33,34 The unintentional modification in the positive feedback loop gain caused by either the device parameter fluctuation or by the surface potential variation leads to the variation of the latch-up voltage and Ion/Ioff from device to device. Nevertheless, both of our devices exhibit unique latchup characteristics, which originate from the positive feedback loop. Additionally, the “latch-down” phenomenon, the abrupt decrease in the diode current, is seen in Figure 3 as VDS is swept

basic operation of the NW FBFET, a cross section of the device structure and its corresponding off-state energy band diagram at a drain-to-source voltage (VDS) of 0 V are shown in Figure 1b. To set the off state, a positive gate voltage (VGp) is applied to Gate1 and a negative gate voltage (VGn) is simultaneously applied to Gate2. These gate voltages create potential barriers in the intrinsic channel region and block the injection of charge carriers from the source or from the drain to the channel. If the potential barriers are removed, the device is in the on state. The following section describes the specific operation mechanisms in more detail. The drain current (IDS) versus VDS characteristics of two NW FBFETs (named FBFET1 and FBFET2) prepared in this study are presented in Figure 2a,b. The NW FBFET displays the ordinary diode characteristics under lower gate bias voltages. It is interesting to note that abnormal IDS characteristics can be observed when higher gate bias voltages (e.g., over VGp = 3 V and VGn = −3 V for FBFET1 in Figure 2a, and over VGp = 2 V and VGn = −2 V for FBFET2 in Figure 2b) are applied. As VDS is swept upward, IDS remains below 10−14−10−10 A under relatively low VDS, but IDS abruptly increases by 4−8 decades as VDS reaches higher voltages (over 1−1.5 V for FBFET1 in Figure 2a and 3−5 V for FBFET2 in Figure 2b). The abrupt increase in the diode current corresponds to the “latch-up” phenomenon, which has also been observed in biristors,27,28 thyristors,29 and field-effect diodes.30 In our NW FBFETs, the generation of a positive feedback loop triggers the latch-up phenomenon. Figure 2c uses energy band diagrams to illustrate the positive feedback loop in the NW FBFET that generates latch-up as VDS increases. When a positive gate voltage VGp and a negative gate voltage VGn are applied to Gate1 and Gate2, respectively, the energy band structure of the NW FBFET becomes the band diagram of a p−n−p−n diode. This phenomenon in turn creates a reverse bias in the intrinsic channel. Because the potential barriers in the intrinsic channel region are high enough to block the injection of electrons (or holes) from the source (or the drain) to the channel, the device remains in the off state, even when a lower VDS is applied. However, as the increasing VDS reduces the energy level of the p+ drain, holes can flow from the drain to the intrinsic channel region; some holes flow toward the n+ source and others accumulate at the potential barrier generated by VGn. The accumulation of holes reduces the height of the potential barrier, thereby allowing electrons in the n+ source to flow toward the intrinsic channel region. Similar to the injection of holes, some electrons flow toward the p+ drain and other electrons are accumulated in the potential barrier generated by VGp. As charge carriers are injected, they continue to accumulate, and the height of the potential barriers becomes exponentially lower. In a very short period of time, a positive feedback loop is produced as a result of the recursive and mutual interaction between the potential barriers and charge carriers. Finally, the positive feedback loop eliminates the potential barriers and triggers the abrupt increase in the diode current in the NW FBFET. Some variations in the latch-up voltage and the on/off current ratio (Ion/Ioff) of our NW FBFETs can be seen in Figure 2a,b. Because the height of the potential barrier depicted in Figure 2c is one of major factors in determining the electrical characteristics, the variations imply that different shapes of the potential barriers are formed in FBFET1 and FBFET2, even under the same gate bias voltages. Two possible reasons for the origin of the different shapes are briefly described here. The

Figure 3. Hysteretic IDS versus VDS characteristics of the NW FBFET (or FBFET2) with various VGp and VGn.

downward from 5 to −1 V (after the upward sweeping for FBFET2 in Figure 2b); IDS first remains over ∼10−6 A, and then, abruptly drops as VDS approaches 1 V. Therefore, counterclockwise hysteresis is observed in the VDS versus IDS characteristics because of the difference of latch-up and latchdown VDS. The width of the hysteresis window is determined by the gate bias voltages: the higher gate bias voltage causes the wider hysteresis window. The unique hysteretic IDS versus VDS characteristics also demonstrate this device’s operation as a memory device. The top gate oxide can act as a capacitor in which charge carriers injected from the source or from the drain are accumulated. The charging and discharging in the gate oxide capacitors leads to the hysteresis characteristics, which can be exploited to read the “0” and “1” logic states. The operation principle of the charging and discharging without any external capacitor is similar to that of a capacitor-less 1transistor dynamic random access memory (1T-DRAM) cell, which exploits the inherent floating body effect of partially depleted SOI devices.35 As a result of its positive feedback loop, a single NW FBFET exhibits steep switching behaviors in n- and p-channel operation modes. The energy band diagrams of a single NW FBFET in n- and p-channel operation modes are depicted in Figure 4. The operation mode of the NW FBFET can be modulated by adjusting VGp and VGn. To set the n-channel C


Letter

Nano Letters

of 1 V. For the n-channel operation mode, IDS versus VGS characteristics are displayed using a fixed VGp of 4 V as VGn varies from −4 to 0 V. Similarly, for the p-channel operation mode, VGp varies from −1 to 3 V while VGn is fixed at −6 V. By exhibiting an Ion/Ioff of approximately 105, the device demonstrates abrupt switching characteristics when the variable gate voltage reaches threshold voltages (Vth) of −2.55 or 0.9 V, where Vth is extracted using a constant-current method at Ids = 10−7 A/μm for Vds = 1 V. When operating in the subthreshold region, the average SS (SSavg) values, defined as the inverse slope of the logarithmic IDS versus gate voltage characteristic between the off-state voltage and the threshold voltage, expressed by the following equation, [(log10Ith − log10Ioff)/ (Vth − Voff)]−1, are 36 mV/dec for the n-channel operation mode and 57 mV/dec for the p-channel operation mode. The IDS versus VGS curves (obtained from FBFET2) plotted in Figure 5b provide an SSavg of 98 mV/dec for the n-channel operation mode and an SSavg of 27 mV/dec for the p-channel operation mode with Vds = 1 V. Figure 5c,d displays the variations of the point SS (SSpoint), defined as [d(log10|IDS|)/ dVGS]−1, extracted from the IDS versus VGS curves (obtained from FBFET1) in Figure 5a. The minimum SSpoint values obtained in the subthreshold region are 19 mV/dec for the nchannel operation mode and 23 mV/dec for the p-channel operation mode, in a narrow VGS range of 0.05 V, and the

Figure 4. Energy band diagrams of the NW FBFET in the n- and pchannel operation modes.

operation mode, VGp for Gate1 is fixed to a positive bias and VGn for Gate2 is varied. When the device operates in this condition, VGn can modulate the height of the potential barrier and control IDS; a slight increase in VGn causes the lowering of the height of the potential barrier generated by VGn. When VDS is positive, some electrons from the n+ source can be injected into the intrinsic channel region, thereby very quickly generating a positive feedback loop. Similar to the n-channel operation mode, the device can be set to the p-channel operation mode by varying VGp and setting VGn to a fixed negative bias. Next, we analyze the switching characteristics of our NW FBFETs under variation of the gate biases. Figure 5a shows the representative IDS versus VGS characteristics of FBFET1 at a VDS

Figure 5. (a,b) Transfer (IDS−VGn, IDS−VGp) characteristics of the n- and p-channel operation modes of the NW FBFETs at VDS = 1 V. Note that the transfer curves in (a,b) were obtained from FBFET1 and FBFET2, respectively. (c,d) SSpoint values are extracted from the corresponding IDS−VGn and IDS−VGp curves (of FBFET1). D


Letter

Nano Letters

Figure 6. Transfer characteristics of the (a) n- and (b) p-channel operation modes of the NW FBFET (or FBFET1) with various fixed gate voltages (fixed VGp for the n-channel operation mode and fixed VGn for the p-channel operation mode) at VDS = 1 V.

Figure 7. Transfer characteristics of the (a) n- and (b) p-channel operation modes of the NW FBFET (or FBFET1) with various VDS.

demonstrate the modulated switching behaviors of the n- and p-channel operation modes in FBFET1 under various fixed gate biases at VDS = 1 V. For the n-channel operation mode shown in Figure 6a, the fixed gate bias VGp is varied from 4 to 0 V in −1 V steps, which corresponds to a change of the potential barrier height. As the fixed VGp changes from 4 to 2 V, the device exhibits steep switching behaviors with small variations in Ion/Ioff and the SSpoint values (19 → 32 → 20 mV/dec). Furthermore, a wide shift of Vth occurs (−2.55 → −5.4 → −6.3 V). However, as the fixed VGp reaches 1 and 0 V, the device does not function as a switching device; the IDS of the device is over 10−6 A for the entire range of VGn, and the switching properties such as SS, Vth, and Ion/Ioff cannot be extracted. Similar to the n-channel operation mode, there is also modulation of the switching behavior of the device when in the p-channel operation mode, as shown in Figure 6b. The fixed gate voltage VGn varies from −6 to 0 V in 1 V steps. Initially, the device exhibits steep switching behavior when the fixed VGn is −6 V. However, as the fixed VGn varies from −6 to −4 V, SSpoint increases (23 → 24 → 36 mV/dec, respectively), Vth shifts (0.9 → 1.4 → 1.95 V), and Ion/Ioff decreases. Moreover, the device does not show switching behavior when VGn is fixed between −3 and 0 V. This significant change in switching behavior implies that the height of potential barriers plays an important role in the observed switching properties; the high potential barriers from large gate biases enable a highgain positive feedback loop. In particular, IDS is based on diode current equations that are determined by junction voltage drops in the source, channel, and drain, as well as the height of builtin potentials generated by VGp and VGn. Furthermore, the junction voltage drops and built-in potentials are determined by the variations of IDS. In the positive feedback loop model, IDS, junction voltage drops, and built-in potentials undergo mutual interactions; as the built-in potentials vary by a small amount, IDS fluctuates exponentially and this fluctuation subsequently affects the junction voltage drops. At this point, high potential barriers resulting from large fixed VGp or VGn values can

minimum SSpoint values of 18 mV/dec (for the n-channel operation mode) and 10 mV/dec (for the p-channel operation mode) can also be extracted from the IDS versus VGS curves (obtained from FBFET2) in Figure 5b. Compared to conventional MOSFETs, which have a theoretical SS limit of 60 mV/dec at room temperature, our device exhibits extremely low average and point SS characteristics. One of our NW FBFETs exhibits excellent switching characteristics of ∼10 mV/ dec SSpoint with ∼106 Ion/Ioff. In addition, the hysteresis characteristics are present in IDS versus VGS curves in the n- and p-channel operation modes of all of the FBFETs (see Supporting Information). In comparison to other steep switching devices such as TFETs or i-MOSFETs, our NW FBFETs have excellent features for application as a complementary switching device. As depicted in Figure 5, the NW FBFETs with a dual-top-gate structure can easily realize both n- and p- channel operation modes in a single device; this implies that the NW FBFET can be applied to logic applications such as inverter, NAND, and NOR circuits. Recently, complementary TFETs (cTFETs) with low SS have been investigated for use as a replacement for CMOS devices to reduce power consumption in logic gates. The ambipolar transport behavior of cTFETs is a major drawback of those devices, however, because both n- and pTFETs turn on simultaneously when the input gate is in either of the two logic states. To address the ambipolar issue in cTFETs, complicated methods such as an asymmetric sourcedrain doping or a carefully designed gate underlap must be employed.36 In contrast, our NW FBFETs do not require any complicated fabrication methods, because these FBFETs do not exhibit any ambipolar behavior. Moreover, NW FBFETs with a dual-top-gate structure can be converted to n- or p-channel operation mode simply by adjusting gate biases; in this way, they can easily achieve the complementary characteristics required of logic gates. The switching behavior of our NW FBFET can be modulated by changing the fixed gate bias voltages. We now E


Letter

Nano Letters generate higher built-in potentials and junction voltage drops; this enables an abrupt and exponential increase of IDS with low SSpoint values and a high Ion/Ioff, as depicted in Figure 6a,b.26,37 Moreover, with high fixed gate biases, the device effectively maintains the off-state at low variable gate biases. Furthermore, the device turns on at a relatively low |Vth| because the height of the potential barriers is sufficient to prevent the unwanted injection of electrons. On the contrary, in the presence of low fixed gate biases electrons and holes are injected into the channel region, and a sufficient positive feedback loop cannot be generated. In this condition, the device turns on at an early stage and exhibits a large off current and inferior switching properties, such as a large SSpoint and Ion/Ioff. In addition to the fixed gate biases, VDS can also influence the electrical characteristics of the NW FBFET (or FBFET1). Figure 7a,b shows the change of switching behaviors of the NW FBFET with various VDS in both n- and p-channel operation modes. Note that with the exception of VDS, the biases are identical to those depicted in Figure 5a. At approximately 1−2 V of VDS, the device shows abrupt switching characteristics with low SS and high Ion/Ioff. However, in the cases where VDS is too low or too high (below 1 V or over 2 V), the device does not exhibit switching characteristics. This indicates that the abrupt switching behaviors in the NW FBFET are created under appropriate VDS values, which enables the injection of charge carriers into the channel region to generate an effective positive feedback loop. In the presence of a low VDS, the energy level in a p+ drain cannot be reduced sufficiently. As a result, only a few holes can flow toward the intrinsic channel region; the device then turns on gradually without the sufficient conditions to generate a positive feedback loop. On the other hand, when a high VDS is applied, the energy level in a p+ drain drops drastically, and the potential barrier cannot block the injection of electrons and holes into the channel region. Consequently, electrons and holes flow unimpeded from the source/drain into the channel. Therefore, no positive feedback loop occurs and the device turns on normally. The mechanical bendability of our bendable NW FBFET is of crucial interest. The switching behaviors while the device is in various bent states are now investigated. The task is performed by bending the plastic substrate mechanically along the channel transport direction to achieve upwardly and downwardly bent states. A strain with a value of 1.02% is induced; this percentage is obtained from the following expression: t + rSi NW Strain (%) = 100 × s 2 × Rc

Figure 8. Variation of the minimum SSpoint values of the n- and pchannel operation modes of the NW FBFET (or FBFET1) under strains of ±1.02%. The inset shows optical images of the upwardly and downwardly bent devices on a bending stage.

traps in the gate oxide layers affects the energy band structure of the channel while in the bent state. The modulated band structure in the bent state influences the feedback amplification mechanism and changes the SS characteristics. In spite of the aforementioned affects, the SS values of our NW FBFET in the bent state remain below 60 mV/dec. Table 1 shows the comparison between the electrical characteristics of our bendable NW FBFETs and other standard Si and Si NW CMOS-technology devices constructed on bulk or SOI substrates.42−47 The Ion and Ion/Ioff values of our device are comparable to (and competitive with) those of wafer-based Si or Si NW device counterparts. Moreover, one of our devices exhibits a very low SSpoint value of ∼10 mV/dec, which cannot be achieved in standard Si and Si NW CMOS-technology devices. Table 2 summarizes the device features and switching characteristics of our present NW FBFET and those of other FBFETs.20,21,24−26,37 Our present NW FBFETs can guarantee relatively low operation voltages and improved reliability compared to our previous NW FBFETs, which contain charge trap spacers.37 NW FBFETs with p+-i-n+ Si NW channels and sputtered Pt nanocrystal (NC) charge spacers located in the ungated intrinsic channel regions have shown superior switching characteristics, such as a high Ion/Ioff, low SS, and memory characteristics. These devices, however, require that a programming procedure be used in which high gate voltages of ±10 V are applied for several seconds to trap electrons and holes in the NC charge spacers to create potential barriers in the intrinsic channel region. Consequently, damage to gate oxide layers or the creation of unintentional oxide-trapped charges may occur because of the high gate voltages, which, in turn, can lead to device degradation or failure. In contrast, our present NW FBFETs do not require any such programming step because the NC charge spacers are replaced by the dualtop-gate structure. Therefore, the NW FBFETs with the dualtop-gate structure realize low gate bias voltages, and guarantee the enhanced reliability of the device. Compared to other FBFETs on SOI substrates, our NW FBFETs have more versatile practical advantages.20,21,24−26 By combining Si NWs and bendable plastic substrates, we verify the abrupt steep switching characteristics in bent states. Although other research groups achieved very low SS characteristics, their FBFETs are not bendable. Our present study demonstrates for the first time the abrupt switching characteristics of FBFETs in a state of mechanical bending. Our device may be compatible with future bendable or wearable electronic devices Conclusions. We demonstrate the steep switching characteristics and n- and p-channel operation modes of bendable

where the thickness of the substrate (ts) is 200 μm, the radius of the Si NW (rSi NW) is 100 nm, and the radius of curvature (Rc) is 9.7 mm.38 Figure 8 shows the variation of the minimum SSpoint values of FBFET1 in the flat- and bent-substrate states. Compared to the flat state, the minimum SSpoint values in the upwardly and downwardly bent states are slightly increased. We assumed that the tensile and compressive strain would have a large influence on the SS characteristics; when the device is in a bent state, tensile, or compressive strains are applied to the device; these strains affect the physical properties of the Si NW channel and gate oxide layers. The applied strain leads to band splitting and carrier repopulation in the Si NW channel area39,40 or to the generation and relocation of the traps located at the interface or the gate oxide layer.41 The physical deformation of the NWs and the generation/relocation of F


Letter

Nano Letters

Table 1. Comparison of the Electrical Characteristics of our NW FBFET and Standard Si/Si NW CMOS-Technology Devices ref

Tox

device type/technology

channel size

42

fully depleted SOI trigate CMOS

43

22 nm SoC platform trigate CMOS

44

5 nm Si NW GAA

45 46

20 nm vertical Si NW GAA vertical Si NW GAA high-k/metal gate

47

GAA nanowire channel-last process

this work

Si NW FBFET, plastic substrate, dual top gate, 17 nm bending compatible Al2O3

9 nm SiO2 ∼5 nm 20 nm Al2O3 10 nm SiO2

minimum SSpoint (mV/dec)

|Vds| (V)

68

1.3

∼10−3

∼103

2003

71

0.75

∼10−3

∼105

2012

63

1.2

∼1.5 × 10−3

∼ 106

2006

80 96

1.2 1

∼10−3 ∼5.2 × 10−6

∼107 10 −105

2008 2014

64

0.8

∼10−5

∼106

2015

10

1

∼10−5

∼106

2015

h = 36 nm w = 55 nm l = 60 nm h = 90 nm w = 30 nm l = 34 nm d = 5 nm d = 20 nm d = 100 nm l = 320 nm d = 12−17 nm l = 100 nm h = 150 nm l = 5 μm

Ion (A/μm)

Ion/Ioff

4

year

Table 2. Comparison of the Electrical Characteristics of Steep Subthreshold Switching Devices ref

features

channel size

20

SOI, FinFET, gate sidewall charge spacers

21

SOI, FinFET, gate sidewall charge spacers

24−26

FD-SOI, mesa structure, single top gate

37 (our previous work) this work

Si NW, plastic substrate, Pt NC charge spacers

h = 50 nm w = 200 nm l = 0.3−1 μm h = 50 nm w = 45 nm l = 0.37 μm h = 20 nm w = 10 μm l = 0.9 μm h = 100 nm l = 4 μm

Si NW, plastic substrate, dual top gate, bending compatible

h = 150 nm l = 5 μm

formation of potential barrier (minimum bias)

|Vds| (V)

Ion/Ioff

year

Charge trapping (programming) at charge spacers (VGS = 4 V, VDS = 6 V)

∼ 2 (point) 40 (avg.)

1.2

∼107

2008


0.35 (point)

1.25

∼106

2009

Top and back gate bias (VBG = 2 V)

∼ 1 (point)

1−1.5

∼108

2012


18.4 (point) 30.2 (avg.)

1

>105

2014

Dual top gate bias (VGn = −3 V, VGp = 3 V, VDS = 1 V)

18, 10 (n, p/point) 36, 27 (n, p/avg.) ∼ 20 (bent, point)

1

∼106

2015

SSmin (mV/dec)

To prevent shorting the gate electrodes together, an Al2O3 isolation layer was formed. It is noteworthy that, except for the Si NW fabrication, all of the device fabrication processes were conducted on a plastic substrate at a process temperature of less than 150 °C. Measurement. All of the electrical characteristics were measured using a semiconductor-parameter analyzer (HP4155C, Agilent) at room temperature. The morphologies of the NWs on a bulk-Si wafer were observed via scanning electron microscopy (SEM: S-4300, Hitachi). The bending of the device was performed using a custom-built bending apparatus. We examined the electrical characteristics of several individual NW FBFETs.

NW FBFETs with a dual-top-gate structure. Using a positive feedback loop, our NW FBFETs exhibit the excellent switching characteristics in the n- and p-channel operation modes, including 10−23 mV/dec SSpoint with ∼106 Ion/Ioff. The switching properties of NW FBFETs can be modulated by adjusting fixed values of VGp and VGn, or the applied VDS. Moreover, the device maintains the steep switching characteristics well in the bent states. The present study demonstrates the promising possibility of NW FBFETs for application to steep switching bendable electronics. Experimental Section. Device Fabrication. First, p+-i-n+ Si NWs were fabricated using CMOS-compatible top-down processes. An approximately 1016 cm−3 (100)-orientation bulkSi substrate was prepared; NWs were then formed utilizing photolithography, crystallographic wet etching using a tetramethylammonium hydroxide solution, and masked ionimplantation. The NWs were triangular in shape with a height of approximately 150 nm; their doping concentrations were 1020 cm−3. Next, the fabricated NWs were transferred onto a plastic polyether sulfone (PES) substrate using a direct transfer method.48 After this step, Al source and drain electrodes were formed on top of the NWs using photolithography and thermal evaporation and an approximately 17 nm high-k Al2O3 gate oxide layer was deposited via atomic layer deposition. Side-byside Al dual-top-gate structures with widths of 2.5 μm were also formed via photolithography and thermal deposition processes.

■

ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b00606. Hysteresis characteristics in the n- and p-channel operation modes. (PDF)

■

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. G


Letter

Nano Letters Notes

(20) Padilla, A.; Yeung, C. W.; Shin, C.; Hu, C.; Liu, T. J. K. Feedback FET: A Novel Transistor Exhibiting Steep Switching Behavior at Low Bias Voltages. IEDM Technol. Dig. 2008, 1−4. (21) Yeung, C. W.; Padilla, A.; Liu, T. J. K.; Hu, C. Programming Characteristics of the Steep Turn-On/Off Feedback FET (FBFET). VLSI Symp. Technol. Dig. 2009, 176−177. (22) Auth, C. P.; Plummer, J. D. Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET’s. IEEE Electron Device Lett. 1997, 18, 74−76. (23) Lee, J. H.; Kim, B. S.; Choi, S. H.; Jang, Y. J.; Hwang, S. W.; Whang, D. M. A Facile Route to Si Nanowire Gate-All-Around Field Effect Transistors with a Steep Subthreshold Slope. Nanoscale 2013, 5, 8968−8972. (24) Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. Z2-FET: A Zero-Slope Switching Device with Gate-Controlled Hysteresis, VLSI Technology, Systems, and Applications (VLSI-TSA), 2012. International Symposium on 2012, 1−4. (25) Wan, J.; Cristoloveanu, S.; Le Royer, C.; Zaslavsky, A. A Feedback Silicon-on-Insulator Steep Switching Device with GateControlled Carrier Injection. Solid-State Electron. 2012, 76, 109−111. (26) Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. A Systematic Study of the Sharp-Switching Z2-FET Device: From Mechanism to Modeling and Compact Memory Applications. SolidState Electron. 2013, 90, 2−11. (27) Han, J. W.; Choi, Y. K. BiristorBistable Resistor Based on a Silicon Nanowire. IEEE Electron Device Lett. 2010, 31, 797−799. (28) Moon, D. I.; Choi, S. J.; Kim, S.; Oh, J. S.; Kim, Y. S.; Choi, Y. K. Vertically Integrated Unidirectional Biristor. IEEE Electron Device Lett. 2011, 32, 1483−1485. (29) Yang, E. S. Turn-Off Characteristics of p-n-p-n Devices. SolidState Electron. 1967, 10, 927−933. (30) Salman, A. A.; Beebe, S. G.; Emam, M.; Pelella, M. M.; Ioannou, D. E. Field Effect Diode (FED): A Novel Device for ESD Protection in Deep Sub-Micron SOI Technologies. Proc. IEEE IEDM 2006, 1−4. (31) Hong, B. H.; Cho, N.; Lee, S. J.; Yu, Y. S.; Choi, L.; Jung, Y. C.; Cho, K. H.; Yeo, K. H.; Kim, D. W.; Jin, G. Y.; et al. Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge. IEEE Electron Device Lett. 2011, 32, 1179−1181. (32) Wang, D.; Sheriff, B. A.; Heath, J. R. Silicon p-FETs from Ultrahigh Density Nanowire Arrays. Nano Lett. 2006, 6, 1096−1100. (33) Yang, Y.; Salman, A. A.; Ioannou, D. E.; Beebe, S. G. Design and Optimization of the SOI Field Effect Diode (FED) for ESD protection. Solid-State Electron. 2008, 52, 1482−1485. (34) Domeij, M.; Danielsson, E.; Lee, H.-S.; Zetterling, C.-M.; Ostling, M. Current Gain of 4H-SiC Bipolar Transistors Including the Effect of Interface States. Mater. Sci. Forum 2005, 483, 889−892. (35) Lee, M.; Moon, T.; Kim, S. Floating Body Effect in Partially Depleted Silicon Nanowire Transistors and Potential Capacitor-Less One-Transistor DRAM Applications. IEEE Trans. Nanotechnol. 2012, 11, 355−359. (36) Lee, M.; Jeon, Y.; Jung, J. C.; Koo, S. M.; Kim, S. Multiple Silicon Nanowire Complementary Tunnel Transistors for UltralowPower Flexible Logic Applications. Appl. Phys. Lett. 2012, 100, 3559− 3562. (37) Jeon, Y.; Kim, M.; Kim, Y.; Kim, S. Switching Characteristics of Nanowire Feedback Field-Effect Transistors with Nanocrystal Charge Spacers on Plastic Substrates. ACS Nano 2014, 8, 3781−3787. (38) Suo, Z.; Ma, E. Y.; Gleskova, H.; Wagner, S. Mechanics of Rollable and Foldable Film-on-Foil Electronics. Appl. Phys. Lett. 1999, 74, 1177−1179. (39) Koo, J.; Jeon, Y.; Lee, M.; Kim, S. Strain-Dependent Characteristics of Triangular Silicon Nanowire-Based Field-Effect Transistors of Flexible Plastics. Jpn. J. Appl. Phys. 2011, 50, 065001. (40) Shiri, D.; Kong, Y.; Buin, A.; Anantram, M. P. Strain Induced Change of Bandgap and Effective Mass in Silicon Nanowires. Appl. Phys. Lett. 2008, 93, 073114. (41) Lee, M. H.; Hsieh, B. F.; Chang, S. T. Electrical Properties Correlated with Redistributed Deep States in a-Si:H Thin-Film

The authors declare no competing financial interest.

■

ACKNOWLEDGMENTS This work was partly supported by the Midcareer Researcher Program (NRF-2013R1A2A1A03070750) through the National Research Foundation of Korea (NRF), and the KSSRC program (Development of printable integrated circuits based on inorganic semiconductor nanowires).

■

REFERENCES

(1) Frank, D. J.; Dennard, R. H.; Nowak, E. P.; Solomon, M.; Taur, Y.; Wong, H.−S. P. Device Scaling Limits of Si MOSFETs and Their Application Dependencies. Proc. IEEE 2001, 89, 259−288. (2) Haensch, W.; Nowak, E. J.; Dennard, R. H.; Solomon, P. M.; Bryant, A.; Dokumaci, O. H.; Kumar, A.; Wang, X. J.; Johnson, B.; Fischetti, M. V. Silicon CMOS Devices beyond Scaling. IBM J. Res. Dev. 2006, 50, 339−361. (3) Van Overstraeten, R. J.; DeClerck, G. J.; Muls, P. A. Theory of the MOS Transistor in Weak Inversion-New Method to Determine The Number of Surface States. IEEE Trans. Electron Devices 1975, 22, 282−288. (4) Cheung, K. On The 60 mV/dec @ 300 K Limit for MOSFET Subthreshold Swing, VLSI Technology Systems and Applications (VLSI-TSA), 2010. International Symposium on 2010, 72−73. (5) Theis, T. N.; Solomon, P. M. In Question of the “Next Switch”: Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor. Proc. IEEE 2010, 98, 2005−2014. (6) Sakurai, T. Perspectives of Low Power VLSI’s. IEICE Trans. Electron 2004, E87-C, 429−436. (7) Islam, A. E. Current Status of Reliability in Extended and Beyond CMOS Devices. IEEE Trans. Device Mater. Reliab. 2014, 1. (8) Nikonov, D. E.; Young, I. A. Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking. Proc. IEEE 2013, 101, 2498−2533. (9) Tura, A.; Woo, J. C. S. Performance Comparison of Silicon Steep Subthreshold FETs. IEEE Trans. Electron Devices 2010, 57, 1362− 1368. (10) Choi, W. Y.; Park, B. G.; Lee, J. D.; Liu, T. J. K. Tunneling FieldEffect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE Electron Device Lett. 2007, 28, 743−745. (11) Björk, M. T.; Knoch, J.; Schmid, H.; Riel, H.; Riess, W. Silicon Nanowire Tunneling Field-Effect Transistors. Appl. Phys. Lett. 2008, 92, 193504. (12) Ionescu, A. M.; Riel, H. Tunnel Field-Effect Transistors as Energy-Efficient Electronic Switches. Nature 2011, 479, 329−337. (13) Gopalakrishnan, K.; Griffin, P. B.; Plummer, J. D. I-MOS: A Novel Semiconductor Device with a Subthreshold Slope Lower Than kT/q. IEDM Technol. Dig. 2002, 289−292. (14) Gopalakrishnan, K.; Griffin, P. B.; Plummer, J. D. Impact Ionization MOS (I-MOS)Part I: Device and Circuit Simulations. IEEE Trans. Electron Devices 2005, 52, 69−76. (15) Sarkar, D.; Singh, N.; Banerjee, K. A Novel Enhanced ElectricField Impact-Ionization MOS Transistor. IEEE Electron Device Lett. 2010, 31, 1175−1177. (16) Kam, H.; Lee, D. T.; Howe, R. T.; King, T. J. A New NanoElectro-Mechanical Field Effect Transistor (NEMFET) Design for Low-Power Electronics. IEDM Technol. Dig. 2005, 463−466. (17) Kam, H.; Liu, T. J. K. Pull-In and Release Voltage Design for Nanoelectromechanical Field-Effect Transistors. IEEE Trans. Electron Devices 2009, 56, 3072−3082. (18) Salahuddin, S.; Datta, S. Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices. Nano Lett. 2008, 8, 405−410. (19) Yeung, C. W.; Khan, A. I.; Sarker, A.; Salahuddin, S.; Hu, C. Low Power Negative Capacitance FETs for Future Quantum-Well Body Technology, VLSI Technology, Systems, and Applications (VLSITSA), 2013. International Symposium on 2013, 1−2. H


Letter

Nano Letters Transistors on Flexible Substrates Undergoing Mechanical Bending. Thin Solid Films 2013, 528, 82−85. (42) Jan, C. H.; Bhattacharya, U.; Brain, R.; Choi, S.-J.; Curello, G.; Gupta, G.; Hafez, W.; Jang, M.; Kang, M.; Komeyli, K.; et al. A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications. IEEE International Electron Devices Meeting (IEDM) 2012, 3.1.1−3.1.4. (43) Doyle, B. S.; Datta, S.; Doczy, M.; Hareland, S.; Jin, B.; Kavalieros, J.; Linton, T.; Murthy, A.; Rios, R.; Chau, R. High Performance Fully-Depleted Tri-Gate CMOS Transistors. IEEE Electron Device Lett. 2003, 24, 263−265. (44) Singh, N.; Agarwal, A.; Bera, L. K.; Liow, T. Y.; Yang, R.; Rustagi, S. C.; Tung, C. H.; Kumar, R.; Lo, G. Q.; Balasubramanian, N.; Kwong, D.-L. High-Performance Fully Depleted Silicon Nanowire (Diameter ≤ 5 nm) Gate-All-Around CMOS Devices. IEEE Electron Device Lett. 2006, 27, 383−386. (45) Yang, B.; Buddharaju, K. D.; Teo, S. H. G.; Singh, N.; Lo, G. Q.; Kwong, D. L. Vertical Silicon-Nanowire Formation and Gate-AllAround MOSFET. IEEE Electron Device Lett. 2008, 29, 791−794. (46) Zhai, Y.; Mathew, L.; Rao, R.; Palard, M.; Chopra, S.; Ekerdt, J. G.; Register, L. F.; Banerjee, S. K. High-Performance Vertical Gate-AllAround Silicon Nanowire FET With High-k/Metal Gate. IEEE Trans. Electron Devices 2014, 61, 3896−3900. (47) Ma, X.; Yin, H.; Hong, P. Gate-All-Around Silicon Nanowire Transistors with Channel-Last Process on Bulk Si Substrate. IEICE Electronics Express 2015, 12, 20150094. (48) Lee, M.; Jeon, Y.; Moon, T.; Kim, S. Top-Down Fabrication of Fully CMOS-Compatible Silicon Nanowire Arrays and Their Integration CMOS Inverters on Plastic. ACS Nano 2011, 5, 2629− 2636.

I


Steep Subthreshold Swing n- and p-Channel Operation of Bendable

Recommend Documents