Letter pubs.acs.org/NanoLett
Subnanowatt Carbon Nanotube Complementary Logic Enabled by Threshold Voltage Control Michael L. Geier,† Pradyumna L. Prabhumirashi,† Julian J. McMorrow,† Weichao Xu,§ Jung-Woo T. Seo,† Ken Everaerts,‡ Chris H. Kim,§ Tobin J. Marks,†,‡ and Mark C. Hersam*,†,‡ †
Department of Materials Science and Engineering and ‡Department of Chemistry, Northwestern University, Evanston, Illinois 60208, United States § Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota 55455, United States S Supporting Information *
ABSTRACT: In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems. KEYWORDS: SWCNT, transistor, CMOS, inverter, NAND, NOR
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ratio (ION/IOFF).13,14,17 However, when implemented in logic circuits, unipolar devices sustain high steady-state currents, which lead to significant steady-state power consumption during operation. In contrast, CMOS logic is the backbone of modern microelectronics since either the constituent p-type or n-type transistor is turned off in each logic gate, resulting in intrinsically low power consumption and thus the ability to be implemented in efficient large-scale integrated circuits.28 Moreover, CMOS logic offers wide noise margins, which allows robust and reliable operation in highly complex circuitry that inevitably encounters large parametric shifts. These enabling advantages of CMOS technology not only require the realization and integration of p-type and n-type transistors but also precisely tuned, well-separated threshold voltages to ensure that the complementary devices are not concurrently passing current and thus not dissipating steady-state power. This critical issue has not been addressed in previous SWCNT TFT studies,14−23 and thus stands as the key challenge limiting the realization of highly integrated SWCNT-based CMOS electronics. In this Letter, we demonstrate threshold voltage control for both p-type and n-type SWCNT TFTs via a local Ni gate structure, which enables ultralow power complementary device operation. A high-performance SWCNT CMOS inverter (NOT gate) is provided as an initial illustration of this device
ingle-walled carbon nanotubes (SWCNTs) possess exceptional electronic characteristics and have been explored for applications in solution processable, flexible, high-performance electronics.1−5 In particular, advances in semiconducting SWCNT sorting6−10 and integration techniques11−13 have enabled the fabrication of random network unipolar14−20 and ambipolar21−23 logic devices ranging from transistors to 4-bit row decoders.24 However, as SWCNT electronics move from individual device demonstrations to highly integrated circuits, unipolar/ambipolar transistors present significant issues, most notably high power consumption. Although there have been demonstrations25−27 of random network SWCNT-based complementary metal-oxide-semiconductor (CMOS) circuits, this early work did not realize the principal advantage of CMOS logic, namely low power consumption, due to suboptimal threshold voltage control. Here, we demonstrate SWCNTbased CMOS logic circuits with subnanowatt static power consumption via threshold voltage tuning of the constituent ptype and n-type SWCNT transistors. The resulting ultralow power SWCNT CMOS logic circuits possess symmetric voltage transfer curves, high gain, and wide noise margins that are suitable for logic gate cascading and large-scale integration. The development of solution-processed semiconducting SWCNTs has allowed large-area deposition of random network SWCNT films, leading to extensive studies of SWCNT thinfilm transistors (TFTs) in a variety of device structures.15,16,21 Because of adventitious atmospheric doping of SWCNT TFTs under ambient conditions, p-type unipolar devices have dominated prior efforts that have primarily focused on optimizing the trade-off between mobility and current on/off © XXXX American Chemical Society
Received: July 6, 2013 Revised: September 7, 2013
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Figure 1. SWCNT CMOS device structure. (a) Schematic of the SWCNT CMOS inverter including the unencapsulated p-type TFT and benzyl viologen doped n-type TFT. (b) Schematic cross-section of an individual SWCNT TFT consisting of a 300 nm SiO2 on Si substrate, a local Ni (25 nm thick) gate patterned by photolithography, a conformal 10 nm Al2O3 layer deposited via atomic layer deposition (ALD), >99% semiconducting purity SWCNTs deposited by vacuum filtration film transfer, and Cr/Au (2 nm/50 nm) source/drain contacts. (c) Atomic force microscopy image of the SWCNT film morphology in the TFT channel region.
Figure 2. SWCNT TFT electrical characteristics. (a) Log−linear transfer characteristics (IDS vs VGS) of a p-type TFT (blue) at VDS = −1 V and ntype TFT (green) at VDS = 1 V. (b) Output characteristics (IDS vs VDS) of a p-type TFT (left axis) from VGS = −1 to 0 V in 0.25 V steps and n-type TFT (right axis) from VGS = 1 to 0 V in 0.25 V steps. (c) Linear-linear transfer characteristics for PMOS (blue) at VDS = −1 V and for NMOS (green) at VDS = 1 V with the linear region fit shown for VT extraction. (d) Statistical distribution of VT for 30 p-type TFTs (blue) and 30 n-type TFTs (green).
drains. In addition, the p-type TFT source is connected to the power supply (VDD), and the n-type TFT source is connected to ground (GND). Figure 1b is a schematic cross-section that shows further details of the SWCNT TFT structure. In addition, the atomic force microscope (AFM) image shown in Figure 1c illustrates the uniformity of the SWCNT network in
architecture. A schematic of the inverter structure is shown in Figure 1a and consists of an unencapsulated SWCNT p-type TFT and a SWCNT n-type TFT that is chemically doped with benzyl viologen (Supporting Information Figure S1).29 The ptype and n-type TFTs share a common input voltage (VIN) at their gates and a common output voltage (VOUT) at their B
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Figure 3. SWCNT CMOS inverter electrical characteristics. (a) Voltage transfer curves for VDD = 0.8, 1, and 1.25 V (inset shows the circuit diagram of the inverter). (b) Power and (c) gain characteristics of the CMOS inverter at the same values of VDD. (d) Linear dependence of peak gain as function of VDD.
the TFT channel region with a linear tube density of ∼18 nanotubes/μm (∼99% semiconducting purity SWCNTs; see Supporting Information Figure S2 for more information). Figure 2a shows the log−linear transfer characteristics of the constituent p-type and n-type TFTs with channel lengths of 20 μm and widths of 100 μm. The individual transistors have ION/ IOFF of ∼105 and subthreshold slopes of ∼125 mV/decade (ptype) and ∼175 mV/decade (n-type) over the CMOS operating voltage range of each device, namely VGS of the ptype TFT is between −VDD and GND, and VGS of the n-type TFT is between GND and VDD. The gate dielectric (10 nm Al2O3) has a leakage current of less than 100 pA (Supporting Information Figure S3) in the operational voltage window (−1 to 1 V) and a capacitance of ∼850 nF/cm2 (Supporting Information Figure S4). Figure 2b shows well-balanced output characteristics for the p-type TFT (VGS varied from 0 V to −1 V in 0.25 V steps) and n-type TFT (VGS varied from 0 to 1 V in 0.25 V steps). VT for both the p-type and n-type TFTs is determined by extrapolation from the linear transfer characteristics as shown in Figure 2c. The use of the local metallic (Ni) gate structure is critical to obtaining a negative VT for p-type SWCNT TFTs as demonstrated previously.15 Upon conversion of the p-type TFTs to n-type TFTs via benzyl viologen doping, the VT for the n-type TFT becomes analogously positive, thus achieving the symmetric VT separation required for ultralow power CMOS. In particular, Figure 2d shows a histogram of extracted VT for the p-type and n-type TFTs, demonstrating clearly separated and symmetric VT with negative VT for the ptype TFTs and positive VT for the n-type TFTs. The CMOS inverter performance is investigated using the device geometry shown in Figure 1a. The inset of Figure 3a displays the circuit diagram for the CMOS inverter, which is composed of one p-type TFT and one n-type TFT connected
in series. Figure 3a shows the inverter voltage transfer characteristics for different supply voltages (VDD = 0.8, 1.0, and 1.25 V). At low input voltage (VIN = GND), equivalent to logic “0”, VOUT is pulled up to VDD, equivalent to logic “1”. Similarly at high input voltage (VIN = VDD), equivalent to logic “1”, VOUT is pulled down to GND, equivalent to logic “0”. Thus, the SWCNT CMOS inverter demonstrates a full rail-torail (VDD to GND) transfer curve in a symmetric operating voltage window. The noise margins (NM) for this device are NMLOW = 0.32 VDD and NMHIGH = 0.54 VDD for all VDD, thereby providing excellent tolerance against incoming signal variation and suitability for inverter cascading as well as further device integration. Figure 3b shows the power consumption (P = VDD × IGND) of the CMOS inverter during transfer at different supply voltages. The power consumption is less than 0.1 nW in the static states of VIN = VDD and VIN = GND. The peak power consumption is less than 10 nW (for all VDD) and occurs approximately at the midpoint of the transfer state (VIN = VOUT) when the p-type and n-type TFTs are simultaneously in the ON-state. The ultralow power consumption demonstrated by these devices, representing the lowest reported value by 3 orders of magnitude for random network SWCNT-based CMOS logic,25−27 is enabled by the symmetric and wellseparated threshold voltages for the p-type and n-type TFTs. Figure 3c shows the gain (dVOUT/dVIN) of the inverter, including a peak gain in excess of 25 at VDD = 1.25 V. The peak gain shows a linearly increasing relationship (Figure 3d) with respect to VDD and is likely due to VDD being comparable to the threshold voltages of the TFTs, allowing increasing transconductance with increasing VDD. To demonstrate the next level of CMOS integration, NAND and NOR logic gates were fabricated. A NAND logic gate is C
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Figure 4. Two-input CMOS NAND and NOR gate electrical characteristics. (a) NAND and (b) NOR circuit diagram and associated truth tables. (c) NAND and (d) NOR output voltages (VOUT) for each possible two input state. (e) NAND and (f) NOR power consumption for each possible two input state. The supply voltage (VDD) for the circuits is 0.8 V. Input voltages of 0 V (GND) and 0.8 V (VDD) are treated as logic “0” and “1”, respectively.
In conclusion, we have demonstrated SWCNT-based CMOS inverter, NOR, and NAND gates, which constitute the fundamental building blocks of large-scale integrated digital logic circuits with subnanowatt static power consumption, thereby realizing the primary benefit of the CMOS architecture. This enabling advance was accomplished through precise tuning of the p-type and n-type TFT threshold voltages to match the ideal conditions for an integrated CMOS device. The resulting logic gates exhibit symmetric rail-to-rail operation and excellent noise immunity, which will allow for cascaded multiple logic gates in highly integrated circuits. These results coupled with the many other unique attributes of SWCNTs (e.g., solution processability, mechanical flexibility, chemical and thermal stability, and high mobility) provide a direct pathway to large area, ultralow power nanoelectronic systems.
realized by connecting two n-type TFTs in series and two ptype TFTs in parallel, while NOR logic gates employ two ntype TFTs in parallel and two p-type TFTs in series (Figure 4a,b shows the circuit diagrams and associated truth tables for NAND and NOR gates, respectively). Figure 4c,d shows VOUT for the four possible input states of A and B for NAND and NOR gates, respectively. In all cases, VIN (A and B) is set at VDD for the logic state “1”, and VIN is set at 0 V (GND) for the logic state of “0”. For the CMOS NAND logic gate, VOUT becomes logic “0” only when both A and B are in the logic “1” state. Conversely, for the CMOS NOR logic gate, VOUT is the logic “1” level only when both A and B are in the logic “0” state. These tests confirm that in both SWCNT CMOS NAND and NOR devices, the logic gates demonstrate ideal rail-to-rail output voltages for the appropriate two input state. In all static states, the power consumption is on the order of 0.1 nW as shown in Figure 4e for the NAND gate and Figure 4f for the NOR gate. In addition, during the transition between the output states of logic “1” (VOUT = VDD) and “0” (VOUT = GND), the NAND and NOR gates show a peak power of ∼10 nW as expected from the earlier inverter discussion (see Supporting Information Figures S5 and S6 for further details on NAND and NOR operation, respectively). The gain behavior of NAND and NOR gates (see Supporting Information Figure S5 for NAND and Supporting Information Figure S6 for NOR) is also similar to the inverter, showing a linear increase in peak gain with respect to applied voltage, VDD. Overall, these CMOS NAND and NOR logic gates are suitable for further integration into complex circuits due to their ideal input and output voltage behavior while concurrently possessing subnanowatt static power consumption.
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ASSOCIATED CONTENT
S Supporting Information *
Preparation of benzyl viologen solution; dispersion, separation and characterization of SWCNTs; device fabrication procedure; electrical testing setup; dielectric characterization; NAND and NOR logic gate characterization; environmental stability of inverters; hysteresis and key device metrics of the n-type SWCNT TFTs. This material is available free of charge via the Internet at http://pubs.acs.org.
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. D
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Author Contributions
(20) Chen, P.; Fu, Y.; Aminirad, R.; Wang, C.; Zhang, J.; Wang, K. L.; Galatsis, K.; Zhou, C. Nano Lett. 2011, 11, 5301−5308. (21) Ha, M.; Xia, Y.; Green, A. A.; Zhang, W.; Renn, M. J.; Kim, C. H.; Hersam, M. C.; Frisbie, C. D. ACS Nano 2010, 4, 4388−4395. (22) Bisri, S. Z.; Gao, J.; Derenskyi, V.; Gomulya, W.; Iezhokin, I.; Gordiichuk, P.; Herrmann, A.; Loi, M. A. Adv. Mater. 2012, 24, 6147− 6152. (23) Ha, M.; Seo, J. T.; Prabhumirashi, P. L.; Zhang, W.; Geier, M. L.; Renn, M. J.; Kim, C. H.; Hersam, M. C.; Frisbie, C. D. Nano Lett. 2013, 13, 954−960. (24) Cao, Q.; Kim, H.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.; Alam, M. A.; Rogers, J. A. Nature 2008, 454, 495− 500. (25) Lee, S. Y.; Lee, S. W.; Kim, S. M.; Yu, W. J.; Jo, Y. W.; Lee, Y. H. ACS Nano 2011, 5, 2369−2375. (26) Zhang, J.; Wang, C.; Fu, Y.; Che, Y.; Zhou, C. ACS Nano 2011, 5, 3284−3292. (27) Wang, C.; Ryu, K.; Badmaev, A.; Zhang, J.; Zhou, C. ACS Nano 2011, 5, 1147−1153. (28) Weste, N. H. W.; Harris, D. M. CMOS VLSI Design: A Circuits and Systems Perspective; Addison-Wesley: Boston, 2006. (29) Kim, S. M.; Jang, J. H.; Kim, K. K.; Park, H. K.; Bae, J. J.; Yu, W. J.; Lee, I. H.; Kim, G.; Loc, D. D.; Kim, U. J.; Lee, E.-H.; Shin, H.-J.; Choi, J.-Y.; Lee, Y. H. J. Am. Chem. Soc. 2009, 131, 327−331.
The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS This work was supported by the Office of Naval Research MURI Program (N00014-11-1-0690) and the National Science Foundation (DMR-1006391 and DMR-1121262). A National Science Foundation Graduate Research Fellowship (M.L.G.) and a NASA Space Technology Research Fellowship (J.J.M.) are also acknowledged. The device fabrication was performed at the NUFAB clean room facility at Northwestern University. The AFM and SEM characterization was performed in the NUANCE facility at Northwestern University, which is supported by the NSF-NSEC, NSF-MRSEC, Keck Foundation, and State of Illinois.
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