Temperature-Dependent Performance of Printed Field-Effect

Nov 1, 2016 - KIT-TUD Joint Research Laboratory Nanomaterials, Institute of Materials Science, Technical University of Darmstadt (TUD), D-64287 Darmst...
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Temperature-Dependent Performance of Printed Field-Effect Transistors with Solid Polymer Electrolyte Gating Falk von Seggern,*,†,∥ Inna Keskin,† Erin Koos,‡,§ Robert Kruk,† Horst Hahn,†,∥ and Subho Dasgupta*,†,⊥ †

Institute of Nanotechnology, Karlsruhe Institute of Technology (KIT), D-76344 Eggenstein-Leopoldshafen, Hermann-von-Helmholtz Platz 1, Germany ‡ Institute for Mechanical Process and Mechanics, Karlsruhe Institute of Technology (KIT), Straße am Forum 8, D-76131 Karlsruhe, Germany § Department of Chemical Engineering, KU Leuven, Celestijnenlaan 200f, 3001 Heverlee, Belgium ∥ KIT-TUD Joint Research Laboratory Nanomaterials, Institute of Materials Science, Technical University of Darmstadt (TUD), D-64287 Darmstadt, Jovanka-Bontschits-Straße 2, Germany ⊥ Department of Materials Engineering, Indian Institute of Science, Bangalore 560012, India S Supporting Information *

ABSTRACT: Printable, physical, and air-stable composite solid polymer electrolytes (CSPEs) with high ionic conductivity have been established as a suitable alternative to standard dielectric gate insulators for printed field-effect transistors (FETs) and logics. We have performed a stress and temperature stability study involving several CSPEs. Mechanical tensile and shear tests have been performed to determine the physical condition of CSPEs. A comprehensive temperature dependent study has been conducted within the working temperature range which electric double layer (EDL) capacitors or CSPE-gated FETs may typically experience during their lifetime. Moreover, calorimetric measurements have been performed to investigate the CSPEs stability, especially at low temperatures. Mechanical characterizations have shown tensile strength and shear modulus of the material that is typical for solid polymer electrolytes while DSC measurements show no change in the physical state within the measured temperature range. An expected increase in ionic conductivity of the CSPEs of nearly 1 order of magnitude has been observed with an increase in temperature, while an anomalous positive temperature relationship to EDL capacitance has also been noticed. Interestingly, the transistor performance characteristics, namely, on-current and threshold voltage, are found to be quite independent of the temperature, thus ensuring a large and stable operation temperature window for CSPE-gated FETs. The other parameters, subthreshold slope and the device mobility, have varied following the classical semiconductor behavior. In fact, the present study not only provides a detailed understanding of temperature dependence of the CSPE-gated FETs but also offers an insight into the physical and electrical properties of the CSPEs itself. Therefore, these results may very well help to comprehend and improve EDL capacitors, supercapacitors, and other devices that use CSPEs as the active material. KEYWORDS: composite solid polymer electrolyte, physical properties, temperature dependence, field effect transistor, electrolyte gating

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INTRODUCTION Field-effect transistors (FETs) are the basic building blocks of electronic circuits and are indispensable for every-day modern devices and gadgets. The most commonly used FETs use Si technology that offers wide range of novelties, such as miniaturization, high frequency switching, inexpensive production, and so forth. The gating mechanism of these devices is typically based on high-k metal-oxide dielectrics with minimal thickness, negligible leakage currents, and superior film and interface quality. However, this highly matured technology requires enormous initial investment, high temperature, and ultrahigh vacuum (UHV) processing that limit its suitability for flexible and printed electronics. In this regard, for printed electronics based on organic/inorganic semiconductors, an © 2016 American Chemical Society

alternative gating mechanism, namely electrolyte gating (electrolyte as electric insulator), can be very well suited.1−7 Electrolytes offer exceptionally large polarizability, thereby, they reduce the operation voltages down to 1−2 V and make the electrolyte-gated devices highly favorable for portable electronic applications. Furthermore, electrolytes can provide a highly conformal interface with rough semiconductor surfaces.5 As examples of the superior interface quality printed, highly porous and nanoparticulate semiconductor channel FETs can be cited.8−10 Additionally, composite solid polymer electrolytes Received: August 30, 2016 Accepted: November 1, 2016 Published: November 1, 2016 31757

DOI: 10.1021/acsami.6b10939 ACS Appl. Mater. Interfaces 2016, 8, 31757−31763

Research Article

ACS Applied Materials & Interfaces

solution was slowly added under continuous stirring at 50 °C to the second one, until a mass ratio of 7:30 was reached. The final solution, when turned completely transparent and homogeneous, was filtered through a 0.2 μm polytetrafluorethylene (GE Healthcare, PTFE) filter (CSPE-1). In the same manner, two other CSPEs were prepared where PC was substituted either by a mixture of PC and diethylcarbonate (DEC) or a mixture of PC and ethyl methyl-carbonate (EMC) with molar ratio of 1:1, in both cases (CSPE-2 and CSPE-3, respectively). The electrolyte is liquid in the as-prepared state, but turns into a solid when evaporation of the excess solvent is initiated, i.e. after printing. Preparation of Parallel Plate Capacitors. Commercially available, metallic conducting (R□ = 20 Ω) tin-doped indium oxide (ITO) coated high quality float glass (Präzisions Glas & Optik GmbH) substrates were used for the preparation of parallel plate capacitors. The passive structures were realized by laser ablation of the ITO-coated glass with pulsed IR-Laser (Trumpf, TruMicro 5000). Next, two glass slides with structured electrodes of the same size (2 × 1 mm2) were assembled in parallel arrangement with the ITOelectrodes facing each other, as shown in Figure 1a; in order to ensure

show very good tensile and physical strengths making them quite suitable for flexible electronic applications. However, often a trade-off has to be considered between the physical strength and the ionic conductivity.11−14 The rather moderate ionic conductivity of common solid polymer electrolytes in the range of 10−3 to 10−5 S cm−1 is often thought as a major drawback for this kind of gating mechanism, as it may limit the switching speed of the electrolyte-gated FETs. However, the category of composite solid polymer electrolytes (CSPEs) may actually overcome this reservation. As will be shown in the present study, CSPEs may actually show competitive physical properties compared to pure polymeric electrolytes, however, with large ionic conductivities pushing to 10−2 S cm−1 values. In fact, electrolyte-gated FETs have already been demonstrated to operate beyond 100 kHz frequencies.7,15,16 In particular for printed FETs, the speed constraint due to ionic conductivity becomes less important as the device speed is actually critically limited by the resolution of typical commercial printers (in the order of tens of micrometers).2 The suitability of different printable electrolytes for applications, aiming at all-solid state devices, has been investigated by various research groups. Different categories of solid electrolytes have been considered. Ion gels, a combination of ionic liquids and block-co-polymers, have widely been tested for organic semiconductor,17−21 inorganic oxide1,2,4,6,22 and carbon nanotube15,16 based FETs. Also solid polymer electrolytes,23 ceramic solid electrolytes,24 and cation doped β-alumina25,26 have shown considerable promise. In the present study, a comprehensive investigation of the physical and temperature stability of a range of carefully chosen CSPEs have been performed, within the temperature range that FETs may typically get exposed to during their operation lifetime. In this regard, the tensile stress tests and shear modulus measurements have offered information about the physical strength of the CSPEs; while, differential scanning calorimetry (DSC) measurements provided insight into the change of aggregate state during the temperature variation. In order to study the temperature behavior, CSPE-dielectric parallel plate capacitors and CSPE-gated FETs have been prepared, and the key performance parameters have been measured in the temperature range between −35 to 45 °C. As will be demonstrated, the chosen CSPEs offer high ionic conductivity2 and the composition of the CSPEs has been adjusted to combine high polarizability, high conductivity, and excellent inkjet printability. It is worth mentioning that unlike ionic liquids, this class of CSPEs also demonstrates good environmental stability,3 sufficient for printing, processing, and operation of devices at ambient conditions. The experiments have produced quite encouraging results as most of the device characteristics are found to be either unchanged over the entire temperature range or changing according to theoretical predictions.

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Figure 1. (a) Parallel plate capacitor with ITO electrodes and CSPE, placed in a Teflon boat which is used for the in situ room temperature drying of the composite polymer electrolyte. Inset shows schematic of the ITO electrode. (b) Schematic of the CSPE-gated field-effect transistor with the in-plane gate geometry. exact parallel alignment spacers with thickness of 1 mm were attached. The entire assembly was placed in a Teflon vessel, which served as the reservoir for the CSPE, when in the liquid state; with subsequent drying, the CSPEs underwent a mass loss of ∼90%. Thus, the Teflon vessel was carefully filled with the appropriate amount of liquid CSPE, in order to ensure that the final CSPE level exactly matches with the electrode height at the end of drying process. The preparation of the parallel plate capacitor, the drying process, as well as the data acquisition was done in an argon filled glovebox. The temperature variation in the temperature dependent measurements was carried out using a thermostat, capable of covering a temperature range from −80 °C to 60 °C. For accurate temperature calibration, a thermocouple was placed in between the glass plates inside the dried CSPE of a model cell. The electrical impedance measurements were carried out in the temperature range from −45 °C to 45 °C using a Biologic SP-150 Value Oriented Research grade Electrochemical Impedance Spectrometer (EIS) with capabilities for potentiostatic/galvanostatic measurements in the frequency range of 1 Hz to 1 MHz. An acvoltage amplitude of Vac = 5 mV was chosen; 15 points per decade were recorded and averaged over 50 measurements, at each frequency. Preparation of Electrolyte-Gated Field-Effect Transistors. The passive structures of the FETs were patterned using a pulsed IRlaser. The FETs were prepared following the in-plane device geometry, as shown in Figure 1b. The channel length was fixed at 50 μm; the electrode structuring was followed by a cleaning procedure using 2propanol (for analysis 99.5%, Merck Millipore), acetone (for analysis 99.8%, Merck Millipore), and ethanol (absolute 99.5%, Merck Millipore). The oxide precursor channel and the electrolytic gate dielectric were printed using Dimatix 2831 desktop inkjet printer. The precursor used for the channel preparation was 0.05 molar solution of

EXPERIMENTAL SECTION

Preparation of Composite Solid Polymer Electrolyte. The CSPEs were prepared using the following steps. First, lithium perchlorate (LiClO4, 99.99% Sigma-Aldrich GmbH) and propylenecarbonate (PC, anhydrous 99.7%, Sigma-Aldrich GmbH) were mixed in a mass-ratio of 1:9 in a sealed glass beaker and stirred at room temperature until a clear solution was obtained. In a different beaker poly(vinyl alcohol) (PVA, hydrolyzed 98%, 13k−23k Mw, SigmaAldrich GmbH) and dimethyl sulfoxide (DMSO, anhydrous 99.9%, Sigma-Aldrich GmbH) were mixed at a mass-ratio of 1:10 at 50 °C for 12 h. All chemicals were used without further purification. The first 31758

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ACS Applied Materials & Interfaces indium(III) nitrate (99.99%, Sigma-Aldrich) dissolved in double deionized H2O and glycerol (99.5%, Merck) with a volume ratio of 8:2. After printing the precursor, the substrate was placed on a hot plate at 100 °C for 10 min, followed by a heating step at 400 °C for 2 h, in a box furnace (Nabertherm P330). To avoid contamination of the transistor channel, the CSPE was printed immediately after annealing treatment. The electrolyte was printed to completely cover the channel area and a large part of the gate electrode. The thickness of the CSPE layer was determined with a Dektak 6 M profilometer to about 1 μm after drying. Following the transistor preparation, the substrate with the device was sealed in a plastic pouch with Al-contact strips reaching out of the pouch (schematically shown in Figure 1b). To ensure good thermal contact, the substrate was glued to the inner side of the pouch using a conductive double-sided electrically conducting carbon tape. Finally, the pouch was sealed by local heating to fuse the plastic along with the Al contacts. For the measurements of temperature dependent electrical characteristics, the pouch was immersed inside a silicon oil bath, in order to ensure a homogeneous and accurate temperature control. The thermostat (Lauda CS 80) was capable of changing the temperature between −35 and 60 °C with an accuracy of 0.1 °C. The characterization of the FET was performed using an Agilent 4156C Precision Semiconductor Parameter Analyzer. To measure the transfer characteristics, the drain-source voltage (Vds) was fixed to 1 V and the gate-source voltage (Vgs) was swept from −0.3 to 0.9 V. For the output characteristic curves, Vgs was kept constant, while Vds was swept from 0.0 to 1.6 V. Results and Discussion. In printed electronics, the choice of substrate is often limited to flexible materials. A CSPE utilized in a printed device on such a substrate needs to have a certain physical strength. Therefore, in order to better understand the composition, consistency, and physical properties of the chosen CSPEs, in their dried state, in situ weight loss, rheological, and tensile strength measurements were carried out. To determine the final composition of the dried CSPEs three samples were prepared with the compositions of CSPE-1, -2, and -3, respectively. Figure 2 shows the chemical composition of the three CSPEs.

loss of the three samples during the drying process is obtained to be 91.5, 91.0, and 91.8 wt %, respectively. Following the performed weight loss tests, the final mass ratio in CSPE-1, -2, and -3 can be found as solvents/LiClO4/PVA = 0.36:0.12:0.52, 0.40:0.11:0.49, and 0.34:0.12:0.54, respectively. Previous experiments performed by Nasr et al. for CSPE-1 have verified the presence of both solvents, PC and DMSO, in the dried state of CSPE-13; although, those experiments have confirmed the solvent retention, however, it was found not possible to determine the exact ratio between DMSO and PC. To investigate the consistency of the material, we chose CSPE-1 as the model system and tested tensile strength (TS) and shear modulus. Even though there is a considerable amount of solvent left in the dried CSPE film, the material still shows remarkable TS. While performing tensile test measurements in order to determine the ultimate TS, the film ruptures upon application of a tensile load of 2.4 MPa and with a linear elongation of ∼80% (refer to S2 of the Supporting Information, SI). The rheological measurement performed versus temperature with a heating rate of 0.5 °C min−1 between −35 and 50 °C has shown values in the range of 106 to 107 Pa for the storage modulus and 105 to 106 Pa for the loss modulus. In a viscoelastic material the storage modulus represents the energy stored in the material, i.e., the elastic portion, and the loss modulus represents the energy dissipated in heat, i.e., the viscous portion (refer to S3). The measurement suggest that the CSPE has the properties of a strong gel and thus physical properties are comparable to other solid polymer electrolytes (refer to S4). After investigating the composition and rheology of the CSPEs, the characterization of the temperature dependent performance was initiated. The main focus was on the ionic/electrolyte conductivity (σel) and double layer capacitance (Cdl) of the CSPEs with respect to temperature. The method of choice was impedance spectroscopy due to its nondestructive nature and the possibility to extract both parameters from the same set of measurement. The impedance measurements were carried out on the CSPE filled ITO-electrode parallel plate capacitors for all three CSPE compositions. Figure 3a

Figure 3. (a) Nyquist plot of a representative CSPE filled parallel plate capacitor (the selected data is for CSPE-1, which is later used for the FET preparation); a detailed view of the high frequency region is shown in the inset. The blue and the red curves represent the experimental and fitted data, respectively; (b) the equivalent circuit that is used for fitting the experimental result. The fitting components are as follows: Rext represents ITO lead and contact resistance, Relec is the ionic resistance of the electrolyte, Cext is the capacitance of the external leads, Cpseudo is the pseudocapacitance of the ITO−CSPE interface, Rpseudo is the resistance against redox chemical reaction at the ITO−CSPE interface and finally Cdl is the electric double layer capacitance at the ITO−CSPE interface.

Figure 2. Structural formula of the three investigated CSPEs: (a) PVA + PC + DMSO + LiClO4; (b) PVA + PC:DEC (1:1) + DMSO + LiClO4; and (c) PVA + PC:EMC (1:1) + DMSO + LiClO4.

shows a typical, as recorded Nyquist plot; the equivalent circuit used for fitting the data is shown in Figure 3b. The equivalent circuit model used in this study is closely related to the circuit used by Dasgupta et al.2 Nonetheless, owing to minor differences in the experimental setup, certain modifications had to be introduced. The equivalent circuit presented here, considers all components needed to describe the charging processes. Rext and Cext represent the sum of the resistances and capacitances of the connecting cables, leads, and contacts. Cpseudo

After drying under ambient conditions a transparent and rubber-like film remains that shows constant weight for 3 days. To determine the composition of the dried CSPEs, precise weight loss measurements computing from the as-cast and the dried electrolyte foils were carried out. Assuming that the mass of PVA and LiClO4 remains constant during the drying process, the difference in weight can be attributed solely to the evaporation of DMSO and PC/EMC/DEC. The mass 31759

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glass forming materials.28 In fact, for all three CSPEs, the temperature dependence of σel can be very well fitted to the modified VTF model and show glass transition temperatures of 93, 167, and 182 K for CSPE-1, -2, and -3, respectively. This result is supported by the DSC measurement on CSPE-1 that shows no glass transition or crystallization taking place within the temperature range of interest (refer to S6). However, it is also quite obvious from Figure 4 that there is no specific advantage of adding other lower melting solvents with reduced viscosity, such as DEC and EMC to PC; the electrolyte conductivity of CSPE-1 stays superior for the entire temperature regime. The relationship between Cdl and temperature is more complex. The double layer model of Stern explains the effects at the electrode− electrolyte interface as a combination of a Helmholtz- and a Gouy− Chapman-layer. The Helmholtz-layer of fixed ions at the interface with a distance of the solvation radius predicts a decrease of Cdl with an increase in temperature due to the following reasons. The hydrodynamic radius Rhyd is one of the parameters that determine the distance of the nearest possible approach of ions to the electrode surface in the Helmholtz-double-layer. Hence, it is easy to infer that the closer the ions can approach the electrode surface, the higher the capacitance value can become (C ∝ 1/Rhyd). Now, the hydrodynamic radius (Stokes’ radius) is given by the following:

and Rpseudo are the pseudocapacitance of the ITO-electrode parallel plate capacitor and the faradaic resistance due to redox chemical reactions, respectively. Relec is the electrolyte resistance, which is a function of the mobility and density of ions in the CSPE. Finally the double layer capacitance created at the ITO−CSPE interface is represented by Cdl.27 In order to assess the temperature dependent behavior of the CSPEs, in relation to their suitability for later applications at low temperatures, it is necessary to analyze the temperature dependence of σel and Cdl. The values of σel are obtained from the measured electrolyte resistance Relec; values of Cdl and Relec have been calculated by fitting the impedance data using the equivalent circuit shown in Figure 3b. The temperature dependencies of σel and Cdl are shown in Figure 4 for the temperature range from −45 to 45 °C.

R hyd =

kBT 6πηD

(1)

where kB, T, η, and D are the Boltzmann’s constant, temperature, viscosity, and diffusion coefficient, respectively. The equation shows a direct proportionality between Rhyd and temperature, which should result in an inverse relationship between the double layer capacitance and the absolute temperature, given by C ∝ 1/T.29 The influence of the diffused Gouy−Chapman double layer can be neglected following Bourg et al. as the double layer thickness is extremely small for high ionic concentration electrolytes.30 However, contrary to this analogy, it can easily be noticed that the measured Cdl value shows positive temperature dependence, i.e. it increases monotonically with increasing temperature. This behavior of Cdl has been observed earlier for ionic liquids,31,32 ion gels,33 and molten salts.34,35 Despite these observations of positive temperature dependence reported in the literature, which goes against the classical double layer model, a widely accepted explanation of this phenomenon has not yet been presented. Considering the permittivity of the solvent at the microscopic level to be constant, an increase in Cdl can be observed either due to an increase in the number of ions at the electrode surface forming the double layer or due to a decrease in the distance of nearest approach of the ions to the electrode. The latter can be ruled out due to the prior described behavior of Rhyd with temperature. The other possibility that is the increased number of ions at the electrolyte−ITO interface could originate from a growing concentration of dissolved ions in the CSPE with increasing temperature. During the drying process, the concentration of LiClO4 increases and upon reaching the solubility limit at certain polymeric pockets, recrystallization may take place. Notably, as the solubility of a salt in a solvent increases with temperature the ionic concentration in the CSPE may also increase

Figure 4. (a) Conductivity values in the course of a temperature change for CSPE-1, -2, and -3 extracted from the impedance spectroscopy. The squares represent the measured values and the solid lines the calculated curves fron the VTF-model. (b) Electric double layer capacitance at the CSPE−ITO interface, calculated for different CSPEs with respect to a variation in temperature. The definition of ionic conductivity, σel = enμion, shows a direct dependency on ionic concentration n and mobility μion. During the performed impedance measurements, the ionic concentrations do not change, thus σel is solely dependent on μion. The higher μion upon an applied electric field, the higher is the ion velocity v according to the relationship v = μE and consequently the faster will be the related transistor response. The absolute value of ionic mobility is a material property and can be tailored by substituting the salt, polymer, or solvent, as it has been done for CSPE-2 and -3. DEC and EMC were chosen to improve the low temperature behavior of the CSPEs. Both materials have a freezing point and viscosity lower than PC (refer to S1) and were thus considered to be promising candidates for an improvement in σel. The σel dependence on temperature is shown in Figure 4a. All three CSPEs show an increase in σel by nearly 1 order of magnitude within the measured temperature range. The data can be consistently represented by the VTF (Vogel−Tamann−Fulcher) model. Stallworth et al. have shown that solid polymer electrolytes containing PC, as well as liquid electrolytes based on PC as the solvent can be considered as

Figure 5. Typical transfer and output characteristics of a CSPE-gated (CSPE-1), printed FET at measured at 30 °C; (a) transfer characteristic with Id vs Vgs (green), Ig vs Vgs (red), and Id1/2 vs Vgs (blue); (b) output characteristics of the same FET with Vgs varying from 0.0 to 0.9 V. 31760

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Figure 6. Temperature dependent transistor characteristics calculated for a CSPE-gated (Sample 1) printed FET; (a) off-current, (b) on/off-ratio, (c) threshold voltage, (d) subthreshold-slope with theoretical minimum value (ideal value) at every temperature36 (brown), (e) field-effect mobility with theoretically expected T-dependence due to electron−phonon interaction37 (brown), and (f) saturated drain currents (Id,sat). with temperature leading to an increasing Cdl. In order to validate this hypothesis we measured Cdl of two liquid electrolytes consisting of PC and LiClO4; one of which was saturated, and the other one 1000 times diluted compared to the first one. Both electrolytes show a similar behavior, that is an increase in Cdl with respect to temperature (refer to S7). Consequently, the influence of the solubility change in the CSPE as the underlying reason for the observed anomalous behavior of Cdl with respect to temperature can also be ruled out. Lastly, the other possible reason for an availability of increased number of surface ions to result in an increased strength of the double layer could be the reduced viscosity of the CSPE with increase in temperature. However, this hypothesis would need further investigation and thus is beyond the scope of the present study. After studying the behavior of the CSPEs using an ideal model system, such as a parallel plate capacitor, we finally would like to comprehend the applicability of the CSPEs in more complex devices. Thus, the temperature-dependent transistor performance of CSPEgated (CSPE-1 was chosen, as it showed the best performance) FETs was investigated for the temperature range between −35 °C to 60 °C. As the figures of merit, we evaluated and compared the key performance parameters of FETs, such as the on/off switching ratio with the corresponding on- and off-current, the threshold voltages, subthreshold swing and of course the field effect mobility values at extreme and every intermediate temperature. Figure 5 shows typical transfer and output characteristics of a CSPEgated FET measured at 30 °C. The complete set of data measured at every temperature can be found in the SI (refer to S8). From the Id1/2 vs Vgs plot (Figure 5a (blue)), the threshold voltage (Vth) can be obtained by a linear fit of the Id1/2 at high Vgs values, by extrapolation to Id1/2 = 0. At the next step, the field effect mobility, μFET, has been derived using the formula: Id =

W μFETCdl(Vgs − Vth)2 2L

Thus, an accurate estimation of the saturation mobility can be obtained from the value of experimentally obtained a using the following:

μFET =

W μFETCdl 2L

(4)

Notably, the above equation is additionally robust, when compared to eq 2, as in this case, the precise calculation of the device mobility does not depend on an accurate estimation of the threshold voltage values. From the transfer and output characteristics measured at every temperature (refer to S8), all of the FET characteristics are calculated and plotted versus temperature in Figure 6. Figure 6a shows that the off-current of the FETs increases with temperature. In fact, for an accumulation mode FET this is an expected behavior; for a nondegenerate semiconductor material like In2O3, the number of thermally activated carriers increases with temperature and accordingly the off-state conductivity rises. In effect, the on/off ratio is seen to decrease with the increase in off-currents and an inverse shape as compared to Ioff vs T can be noticed (Figure 6b). Figure 6c illustrates the threshold voltage of the CSPE-gated FETs with varying temperature. The positive values indicate that the FETs operate in enhancement-mode over the entire temperature range; in fact, the value of the threshold voltage is found to be nearly temperature independent. In this regard, referring to the literature, we know that because of a reduction in the bandgap, the threshold voltage decreases by ∼1 mV K−1 in the considered temperature range.38 For highly doped materials, the value shrinks to ∼0.7 mV K−1 and for a semiconductor-like In2O3 with a typical intrinsic carrier concentration of >1019 cm−3 this value can be further smaller. Thus, a change in the threshold of about 70 mV or smaller can be expected for the measured temperature range; owing to the graphical method used for the threshold voltage calculations, such a small value may actually be within the error limits, for example, a fluctuation in the calculated threshold voltage of about tens of millivolts has been observed. The subthreshold slope is plotted in Figure 6d with respect to temperature. SS is defined as the gate voltage required to alter the drain current by 1 order of magnitude and is given by the following:

(2)

where L is the channel length, and W is the channel width. Taking the square root at both sides of eq 2, the slope of the Id1/2 vs Vgs plot for Vgs > Vth can then be written as follows: a=

2La2 WCdl

SS = ln(10)

(3) 31761

dVgs d(ln(Id))

(5) DOI: 10.1021/acsami.6b10939 ACS Appl. Mater. Interfaces 2016, 8, 31757−31763

Research Article

ACS Applied Materials & Interfaces Equation 5 may also be written as follows:

⎛ k T ⎞ C + CD SS = ln(10)⎜ B ⎟ ox ⎝ q ⎠ Cox

polymeric electrolytes for capacitors, supercapacitors, and allsolid state batteries.

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(6)

⎛k T ⎞ SS = ln(10)⎜ B ⎟ ⎝ q ⎠

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b10939. A complete set of temperature dependent FET characterization and Bode-plots of the impedance measurements, as well as a discussion of the reaction time of the electrolyte (PDF)

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AUTHOR INFORMATION

Corresponding Authors

*E-Mail: [email protected] (F.v.S.). *E-Mail: [email protected] (S.D.).

(7)

The values of SS, calculated from eq 7, are plotted in Figure 6d (brown line). SS increases with temperature and follows an identical slope as has been predicted by the theories. It should be noted that the near ideal (minimum possible) value of SS at every temperature confirms an excellent gating efficiency of the CSPE dielectric. The temperature dependent field-effect mobility calculated from the saturation regime of the transfer curve is shown in Figure 6e. A decrease in the mobility with an increase in temperature is noticed. The intrinsic mobility (μ) of crystalline semiconductors decreases with elevated temperatures due to an increased electron−phonon scattering, and can be approximated according to the relation,37

μ = CT −3/2

ASSOCIATED CONTENT

S Supporting Information *

where, Cox is the capacitance of the gate insulator, and CD is the depletion layer capacitance.36 In the present case, Cox should be replaced by Cdl. However, the accumulation-mode FETs that are being discussed do not have any typical depletion layer. Nonetheless, surface and trap states can compromise the subthreshold slope and result in a contribution similar to that of depletion layer capacitance. However, the absolute values being so close to the theoretical minimum ascertain that the interface trap state density is very small. Therefore, we believe that in this case the component (Cox − CD)/Cox can be considered equal to 1 and eq 6 can be rewritten as follows:

Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors acknowledge the financial support from Helmholtz Association in the form of Helmholtz Virtual Institute VI-530. REFERENCES

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(8)

The calculated mobility variation (Figure 6e, brown) matches very well with the experimentally observed values (refer to S9). Lastly, the oncurrent Id,sat measured at Vgs = 0.9 V and Vds = 1.0 V does not change significantly with temperature as shown in Figure 6f. This can be explained with the inverse behavior of Cdl and μFET with temperature and a constant or an insignificant change in the value of Vth.

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CONCLUSONS In summary, this work demonstrates the mechanical reliability and wide range of temperature tolerance of the chosen CSPEs and shows their suitability as alternative gate dielectrics, especially for printed FETs. Strain and rheology measurements infer considerable stress resistance and promising values for applications in flexible devices. The prepared CSPE-gated, printed, low-voltage FETs work reliably over a wide temperature range between −35 °C to 60 °C, as may be required in various applications. The temperature-driven changes in FET characteristics can largely be explained with known models for semiconductors and electric double layers. A notable exception is the double layer capacitance, which has been observed to vary, only by a moderate amount between 5 to 7 μF cm−2; however, with a positive temperature coefficient. Ionic solubility variations with temperature considered being the origin of this phenomenon has been ruled out; however, a reduced viscosity of the CSPEs with temperature and corresponding higher ionic mobility and ionic concentration increase at the electrode surface could very well be responsible for the observed increase in Cdl. However, the transistor characteristics are found to be quite insensitive to a variation in temperatures; especially the measured on-currents have shown temperature independent behavior. This results from a beneficial interplay of temperature dependencies of Vth, Cdl, and μFET, respectively. In summary, we may claim that the present study can be very interesting not only for the future developments of printed CSPE-gated electronics, but to a larger community working with solid 31762

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Research Article

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