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Ultra-low noise atomic scale structures for quantum circuitry in silicon Saquib Shamim, Bent Weber, Daniel Wilkinson Thompson, Michelle Y. Simmons, and Arindam Ghosh Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.6b02513 • Publication Date (Web): 15 Aug 2016 Downloaded from http://pubs.acs.org on August 20, 2016

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Ultra-low noise atomic scale structures for quantum circuitry in silicon Saquib Shamim,1,∗ Bent Weber,2,3 Daniel W. Thompson,2 Michelle Y.Simmons,2 and Arindam Ghosh,1 1

Department of Physics, Indian Institute of Science, Bangalore 560 012, India 2

Centre for Quantum Computation and Communication Technology, University of New South Wales, Sydney NSW 2052, Australia and 3

School of Physics and Astronomy,

Monash University, Melbourne VIC 3800, Australia

Abstract The atomically precise doping of silicon with phosphorus (Si:P) using scanning tunneling microscopy (STM) promises ultimate miniaturization of field effect transistors. The one-dimensional (1D) Si:P nanowires are of particular interest, which retain exceptional conductivity down to the atomic scale, and predicted as interconnects for a scalable silicon-based quantum computer. Here we show that ultra-thin Si:P nanowires form one of the most stable electrical conductors, with the phenomenological Hooge parameter of low-frequency noise as low as ≈ 10−8 at 4.2 K, nearly three orders of magnitude lower than even carbon nanotube-based 1D conductors.. An in-built isolation from the surface charge fluctuations due to encapsulation of the wires within the epitaxial Si matrix is the dominant cause for the observed suppression of noise. Apart from quantum information technology, our results confirm the promising prospects for precision-doped Si:P structures in atomic-scale circuitry for the 11 nanometer technology node and beyond. Keywords: δ-doped Si:P, silicon, 1D wires, quantum dots, low-frequency noise, STM lithography

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Recent developments have demonstrated that

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Si forms an ideal environment for silicon

based qubits with coherence times of ∼ 1 s for electron spin qubits and 35 s for nuclear spin qubits [1, 2]. In the long term it is important to determine the limiting source of noise within the environment of the qubit to further optimise the coherence times. It is known that the slow fluctuations in the local electrostatic environment of doped silicon nanostructures cause performance degradation by introducing low frequency noise and decoherence in quantum processes [3–7]. Charge noise can lead to decoherence of charge based qubits and whilst individual electron spin qubits in donors are more immune as a result of weak spin-orbit coupling in silicon, the charge fluctuations can still lead to a relaxation of spins [4, 8, 9]. Moreover, schemes for spin read-out and control rely on spin-to-charge conversion via electrical manipulations of electron wave functions. This makes these schemes inherently susceptible to charge fluctuations in the environment, limiting the accuracy of spin readout and two spin logic gates [10, 11]. The detrimental effects of charge noise on the qubit operations demand an extensive investigation on ways to isolate the qubits from the charge fluctuations. In this work we report an ultra-low noise in the electrostatic environment of STM patterned donor-based device architectures [12–15] which have been embedded in high-quality epitaxial silicon and show that these atomic scale structures are immune against the background charge fluctuations. The charge fluctuations in the environment of quantum nanostructures usually arise from the occupancy fluctuations of trap states in supporting substrates or at surfaces and interfaces and manifests in low frequency conductance noise of the device. Random trappingdetrapping of charge at the channel-oxide interface is the dominant source of noise in SiMOSFETs [16], graphene FETs [17], nanowire FETs of silicon [18] and other semiconductors [19–22]. The traps also induce potential fluctuations in the Schottky barriers at the metal-semiconductor contacts leading to 1/f noise, as observed in carbon nanotubes [23] or ultra-high mobility graphene [24]. Even though long range Coulomb interaction between the trapped charges can suppress population fluctuations, and hence reduce the overall noise magnitude [18], a more robust scheme to minimize the influence of the traps on electrical transport is essential for high performance nanoelectronic devices, especially in silicon technology. We previously showed that the two-dimensional (2D) epilayers of phosphorous in silicon display exceptionally low electrical low noise magnitude [25] due to two key factors that con2


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tribute to the superior isolation of the conducting channels, from the time varying disorder potential. Firstly, the high activation barrier (∼ 600 K) for the diffusion of P donors within the crystal, which are the main source of scattering in these systems [26], leads to “freezing” > 25 nm below of disorder. Secondly, the dopant layer in the 2D Si:P system is buried ∼ the silicon surface which naturally provides a physical separation between the surface traps (or dangling bonds, terminations) and active part of the device. Instead, the high-quality epitaxial silicon surrounding provides an electrostatically quiet environment promising ultralow noise operation of quantum information devices. Here we have used the STM patterned nanostructures as sensitive probe to the local electrostatic environment inside the silicon matrix. By studying the low frequency electrical noise, we identify the statistical population and depopulation events involving the charge traps at the silicon-silicon oxide interface as the major source of noise and electrostatic instability in these nanostructures. Figure 1a shows a schematic of the STM-based fabrication process for atomic scale devices. Details can be found in Supporting Information and earlier references [12, 13, 15]. We have carried out measurements on two types of nanostructures, namely 1D wires and zero dimensional (0D) quantum dots. Two 1D wires W1 (STM image in Fig. 1b) and W2 (Fig. S1 in Supporting Information) with diameters of 1.5 nm and 4.6 nm respectively, were measured in a quasi-four probe geometry as shown in Fig. 1b. Two capacitively coupled P-doped side gates tune the conductance of the wires. Figure 1c shows the image of the STM-patterned quantum dot device D1 where a phosphorous doped in-plane plunger gate (PG) tunes its energy levels. The effect of confinement manifests in Coulomb blockade oscillations in the nanowire W1 and quantum dot D1 at 4.2 K as seen in the gate voltage characteristics in Fig. 1d (wire W1) and Fig. 1e (quantum dot D1). In the absence of intentional tunnel barriers, a diffusive coupling to the source and drain likely leads to weak longitudinal confinement in the thinner wire (W1) [13]. No Coulomb blockade was observed in W2 down to 0.1 K, and an observation of universal conductance fluctuations indicates diffusive electron transport in these systems [13]. Thus in view of distinct transport regimes in W1 and W2, it is natural to ask whether the mechanism of noise is device specific or has a generic origin in STM patterned nanostructures. The measured electrical noise, illustrated in Fig. 1f and Fig. 1g for W1 and D1, respectively, depends on the gate voltage, and the corresponding conduction process. In W1, the time dependent conductance consists of random telegraph noise (RTS) at extreme negative 3


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gate voltages (shown by the blue curve for Vg = −0.43 V in Fig. 1f) where Coulomb blockade oscillations dominate electrical transport, implying the existence of one or few active fluctu> e2 /h (red curve in Fig. 1f), the ators. At the large positive Vg and the wire conductance G ∼ RTS is absent. This results in a strong reduction in the normalized noise amplitude (δG/G) and indicates a Coulombic origin of the fluctuators that are effectively screened at higher carrier densities. Similar behavior was observed in device W2 (see Fig. S2 in Supporting Information). In contrast, for D1, the noise consists of discrete and abrupt jumps between a low and a high conductance state irrespective of gate voltages applied (shown by the red and blue curves in Fig. 1g corresponding to different coulomb blockade peaks marked by the arrows in Fig. 1e). This can also be attributed to one or few charged fluctuators that are capacitively coupled to the dot causing random shifts in the state of transmission resonance. The blue curve in Fig. 1g shows a slow initial drift which is likely due to an ensemble of background impurities (such as substrate dopants) which charge/discharge via the intentionally doped regions in the device (including the micron scale contact arms). This ensemble is expected to have a broad distribution of distances to the active device and hence a wide distribution of tunnel times, giving rise to the observed charge drift [27–30]. For a comparative estimate of the noise magnitude in the wire devices, we calculate the power spectral density, SG , by a Fourier transformation of the autocorrelation function based on the conductance time series [25, 31]. The power spectral density is shown in Fig. 2a from the time series of Fig. 1f. The spectrum shows transition from a Lorentzian (SG → constant for f < fc , and → 1/f 2 for f ≫ fc , where fc is the characteristic switching rate) at negative gate voltages, an important feature of RTS noise, to 1/f -like behavior (SG ∝ 1/f α , where α ≈ 1) at large positive gate voltages where the RTS was absent. The switching rate fc ≈ 1 Hz is readily evaluated from a peak in f SG /G2 as a function of frequency (Fig.2b), and varies very little with gate voltage. Importantly, by normalizing the noise magnitude in terms of the dimensionless Hooge parameter (γH ) as γH = SG N f α /G2 , where N is the total number of carriers, we find γH (at 1 Hz) decreases sharply at positive gate voltages (metallic regime) in both wires, and becomes as low as ≈ 2 × 10−8 in W1 (Fig. 2c) and ≈ 1 × 10−7 in W2 (Fig. 2d) which are the lowest value when compared to other 1D systems as will be discussed in Fig. 2e. We emphasize that: (1) Although γH has traditionally been used for bulk materials in which the noise is dominated by mobility fluctuations, we have used it here as a benchmark for comparison with other low dimensional systems from metals 4


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and semiconductors, and secondly, (2) the measured fluctuations arise primarily from the 1D wire region since > 95% of the voltage drop occurs across the 1D wire (the resistance of the 2D region at the ends of the wire being negligible, see Supporting Information and Ref. [13]). To further compare the noise performance of the Si:P 1D wires with nanostructures in other material environment, we have compiled the Hooge parameter of various Si-based devices [25, 32, 33], carbon nanotubes (CNT) [34, 35] and nanowires of different materials such as InAs [36], ZnO [37], Ag [38] and Ni [39], in the bar graph of Fig. 2e. It is evident that the high-quality epitaxial silicon forms one of most stable electrical in terms of low-frequency noise, amongst other material systems leading to a noise magnitude in 1D Si:P wires which is lower than other 1D systems. The combination of low resistivity and exceptionally low electrical noise in the 1D Si:P wires in the metallic regime thus provides an excellent material/device platform for interconnects and circuits, particularly for quantum information-related technologies and implementation as qubit host material. Slow occupancy fluctuations at capacitively coupled charge traps, such as unintentional donor states in GaAs/AlGaAs heterstructures [40] or substrate-channel interface states in CNT [35] or Si nanowire FETs [18], causes noise in many epitaxial or crystalline quasi-1D or 0D systems. Due to the capacitive coupling, the traps effectively impart a fluctuating gate potential on the device, leading to the conductance noise ⟨δG2 ⟩ ∼ (dG/dVg )2 × ⟨δVg2 ⟩, where ⟨δVg2 ⟩ is the fluctuation in the effective gate voltage [20, 41]. To explore the origin of the traps in the 1D Si:P wires, we compare the normalized variance of conductance fluctuations, ⟨δG2 ⟩/⟨G2 ⟩ =

∫

SG /G2 df (obtained by integrating the PSD over the experimental band-

width) to the transconductance (dG/dVg ) of the wires. As illustrated in Fig. 3a for W1 in the Coulomb blockaded regime, ⟨δG2 ⟩/⟨G2 ⟩ ∝ (dG/dVg )2 , which establishes that the charge trap-mediated noise arises predominantly from the 1D wire, since transconductance of the 2D lead regions is virtually negligible. A larger range of values of the transconductance in W1 (due to sharp Coulomb blockade resonances), leads to larger variation in conductance for the same effective gate voltage fluctuation. This leads to a wider range of the Hooge parameter in W1 compared to W2. As seen in Fig. 2c and 2d, the noise magnitude of the wire W1 varies by four orders of magnitude (at negative gate voltage) as compared to wire W2 where it changes by an order of magnitude. However, at large positive gate bias - where both wires enter the metallic regime - the Hooge parameter is comparable (see Fig. S3 in 5


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Supporting Information). A quantitative estimation of ⟨δVg2 ⟩ can be obtained from [16, 20], ⟨δVg2 ⟩

⟨δG2 ⟩ = ⟨G2 ⟩

(

I gm

)2

(1)

where gm = dI/dVg , and I is the source-drain current. The ⟨δVg2 ⟩ for W1 and W2 at 4.2 K is shown in Fig. 3b, where we find ⟨δVg2 ⟩ ∼ 10−9 − 10−8 V2 and varies weakly with gate voltage in both wires. We note that the measured ⟨δVg2 ⟩ is an order of magnitude lower than the 2020 International Technology Roadmap for Semiconductors (ITRS) benchmark for normalized gate voltage fluctuations, δVg Lg W ≃ 30, for low frequency noise in CMOS transistors [42]. The dashed lines in Fig. 3b indicates the 2020 ITRS benchmark of ⟨δVg2 ⟩ computed using gate length Lg ∼ 50 nm and width W ≈ 1.5 nm (W1) and 4.6 nm (W2). In Fig. 3d, we illustrate the effect of charge noise on the device with the example of a single Coulomb blockade peak centered around Vg = −0.49 V, sensing charge-fluctuations in the environment. Charging events of the trap intermittently shifts the effective gate potential on the wires causing G to change oppositely on the two sides of the resonance. Possible traps that can give rise to noise in the epitaxial Si:P systems are the stray P donors in the bulk Si [12] or the charge traps at the interface of silicon and its native oxide at the surface. The role of dangling bonds at the surface as the source of charge traps can be neglected as the formation of a native oxide drastically reduces the number of surface dangling bonds [43]. To identify the microscopic origin of the traps we first consider the switching rate of RTS noise which provides an estimate of the distance between the traps √

as [16], fc = f0 exp(2αT DT ), where DT is the tunneling distance and αT =

(2m∗ ϕB /¯ h2 ),

with ϕB being the barrier height. Taking ϕB ∼ 0.1 eV (Si conduction band offset for the trap states at the Si/SiO2 interface) (see schematic in Fig. 3c), experimental fc ≈ 1 Hz and f0 ∼ 1012 Hz (typical phonon frequency in Si), we find DT ∼ 15 nm, which agrees well with inter-trap separation ∼ 30 nm at the Si/SiO2 interface (with a realistic trap density of states ≈ 1014 cm−2 eV−1 ) [16, 44]. For the stray phosphorous donors, ϕB ∼ 0.045 eV, which leads to an inter-trap separation of DT ∼ 22 nm. However, the density of states ∼ 2×1016 cm−3 eV−1 of the stray P donors in the bulk [12] suggests an average trap separation ∼ 300 nm, and hence unlikely to explain the measured noise. In addition, to support the conclusion that surface traps give rise to the noise mechanism

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in Si:P wires, we observe the magnitude of the gate voltage noise ⟨δVg2 ⟩, where the physical embedding of the channel to a depth d below the surface plays a crucial role (Fig. 3b). The shift in the effective (side) gate voltage from a single charging event (e.g. via exchanging an electron between two traps), can be estimated as, ∆Vg ≈ (e/Cg ) × (qT F d)−1 , where Cg = 1.6 aF is the gate capacitance [13]. The factor (qT F d)−1 accounts for the screening due to the quasi-metallic nature of the 1D wires, where qT F ∼ 1.2 × 1010 m−1 is the ThomasFermi screening wavevector [12]. Using the observed ⟨δVg2 ⟩ ∼ 10−8 V2 (Fig. 3b) we get qT F ∼ 1010 m−1 in agreement with earlier report [12] thus supporting the above mentioned mechanism of noise. Finally, we have examined the impact of surface trap charging events on the stability of STM-designed Si:P quantum dots, which themselves have been suggested as a promising qubit platform, as well as spin and charge sensors for single shot spin readout [14, 15, 45]. We examined the stability of two quantum dot devices by repeatedly recording the conductance resonances over a fixed range of the in-plane plunger gate (quantum dot D1, schematic in Fig. 4a) or the top gate Vtg (quantum dot D2) voltage, where a low temperature SiO2 dielectric has been grown on the top surface (schematic in Fig. 4b). The trap charging events lead to an intermittent shift in the resonance condition, causing the quantum dot to switch between ON and OFF state (Fig. 1g). A 2D map of the conductance as a function of gate voltage and sweep number is shown for D1 and D2 in Fig. 4c and 4d respectively. Quantum dot D2 is clearly more unstable with a larger number of random switchings than D1, because application of a bias across the SiO2 layer rapidly increases the number of active surface charge traps (see the schematic in the right panel of Fig. 4b, where Vts is the fluctuating voltage due to surface trap charging events which is coupled to the quantum dot with capacitance Cts ). A histogram of the gate voltage shift ∆Vg , obtained by measuring the shift of the conductance peaks in successive Coulomb blockade oscillations, indicates an average value of ∼ 5 mV for D1 (Fig. 4e) and a broad distribution up to ∼ 30 mV for D2 (Fig. 4f). This shift in Vtg corresponds to partially screened fluctuations in the gate voltage due to surface trap charging events (∆Vtg ∼ e/Ctg ≃ 50 meV for Ctg ≃ 3 aF [46]). Thus modification to the surface changes the stability of the Si:P nanostructures and hence confirms the conclusion that charging events at the surface leads to noise magnitude in these devices. In order to compare the noise performance of D1 and D2 with other Sibased quantum dots we have computed the power spectral density of charge fluctuations 7


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SQ (see Fig. S5 in Supporting Information). A value of SQ ∼ 3 × 10−9 e2 Hz−1 for D1 and ∼ 10−8 e2 Hz−1 at f = 1 Hz compares favorably with the value of SQ ∼ 3 × 10−9 e2 Hz−1 at f = 1 Hz in Ref. [30]. To summarize, we have investigated the origins of low frequency noise in STM-patterned device architectures for their use as potential qubit host environments and interconnects in quantum computation. We find that noise in the material is dominated by statistical population and depopulation of individual charge traps at the silicon surface which give rise to a fluctuating electrical potential. As a result of the high-quality and crystallinity of the epitaxial silicon, we show that STM-patterned device architectures provides one of the most electrically stable environments in terms of low frequency charge noise compared to most other materials and nanostrucutures. The Hooge parameter of the wires is ∼ 10−8 which is among the lowest when compared to other 1D systems, making these an excellent candidate for interconnects in high-stability silicon quantum quantum computation. Embedding of the devices tens of nanometres below the surface leads to a reduction in noise magnitude. Hence the all-epitaxial STM-patterned nanostructures buried deep below the silicon surface have excellent noise performance as compared to existing nanodevices of other materials. Acknowledgement: We thank Department of Science and Technology (DST), Government of India and Australian-Indian Strategic Research Fund (AISRF) for funding the project. SS thanks CSIR for financial support. MYS acknowledges a Laureate fellowship.

SUPPORTING INFORMATION AVAILABLE

The Supporting Information includes the process of fabrication of STM-patterned nanostructures, technique for measurement of low frequency noise and additional details of charge noise in 1D wires and quantum dots. This material is available free of charge via the Internet at http://pubs.acs.org. Corresponding Author *Email: [email protected] Note: The authors declare no competing financial interest.

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[37] Xiong, H. D.; Wang, W.; Li, Q.; Richter, C. A.; Suehle, J. S.; Hong, W.-K.; Lee, T.; Fleetwood, D. M. Appl. Phys. Lett. 2007, 91, 053107. [38] Singh, A.; Sai, T. P.; Ghosh, A. Appl. Phys. Lett. 2008, 93, 102107. [39] Singh, A.; Mukhopadhyay, S.; Ghosh, A. Phys. Rev. Lett. 2010, 105, 067206. [40] Buizert, C.; Koppens, F. H. L.; Pioro-Ladrière, M.; Tranitz, H.-P.; Vink, I. T.; Tarucha, S.; Wegscheider, W.; Vandersypen, L. M. K. Phys. Rev. Lett. 2008, 101, 226603. [41] Peters, M. G.; Dijkhuis, J. I.; Molenkamp, L. W. J. Appl. Phys. 1999, 86, 1523–1526. [42] RF and analog/mixed-signal technologies (RFAMS) 2013 tables ITRS 2013 edition. [43] Hull, R. Properties of crystalline silicon; INSPEC, The Institution of Electrical Engineers, London, United Kingdom, 1999. [44] Gray, P. V.; Brown, D. M. Appl. Phys. Lett. 1966, 8, year. [45] Watson, T. F.; Weber, B.; House, M. G.; B¨ uch, H.; Simmons, M. Y. Phys. Rev. Lett. 2015, 115, 166806. [46] Thompson, D. W. Ph.D. thesis, University of New South Wales, 2011.

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Nano Letters

(b)

(d) D

G (e2/h)

V2

W1

W1 W2

G2

G1

60nm

(f) 0.02

4.2K

V1

G/G

(a)

1

S

0.01

0.00 0.1 -0.6

0.0

400

0.6

Vg (V)

(c)

G (10 e /h)

2

2

QD

58nm D S

D1 0.8 -3

-3

62nm S

800

(g) D1, 4.2K

1.0 PG

600

Time (s)

(e) G (10 e /h)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 12 of 16

0.5

0.4

0.0

0.0 -0.3

0.0

0.3

VPG (V)

0

1

2

Time (hrs)

FIG. 1: Conductance and conductance fluctuations of Si:P wires and quantum dots. (a) Schematic of scanning tunneling lithography used to fabricate the 1D wires and 0D quantum dots. Scanning tunneling microscope image of (b) Wire W1 of diameter 1.5 nm (c) Quantum dot D1 with source, drain and gate electrodes. The conductance, G, as a function of gate voltage, Vg at temperatures 4.2 K for (d) Wires W1, W2 and (e) Quantum dot D1. (f) Time dependence of conductance fluctuations of wire W1 at three different gate voltages corresponding to the arrows in Fig. 1d. (g) The comparable trace for quantum dot D1 on two separate Coulomb blockade peaks (as shown by the arrows in Fig. 1e) at 4.2 K.

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Page 13 of 16

(c)

-7 2

10-7

10

5

1/f

0.01 0.1

1

10

-0.55V -0.5V -0.47V -0.43V -0.41V 0V 0.41V

(d)

10-5

10-7

0 0.01 0.1

1

(Hz)

10

Ni

Other 1D systems and nanowires

Ag ZnO 2e-8

10-9 -0.6

InAs -0.3

0.0

0.3

0.6

W2, 4.2K

H

(b)

-0.43V 0V 0.41V

Hooge parameter

10-11

W1, 4.2K

2

Hooge parameter

1/f

-1

SG/G (10 Hz )

10-5

10-9

(e)

H

(a)

SG/G2 (10-7Hz-1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

10-6

CNTs Si based 1D, 2D and 3D systems

Si Nanowire -doped Si Bulk Si Si:P-W2

-7

1e-7

10 -1.0

1D Si:P Wires

Si:P-W1 -0.5

0.0

0.5

1.0

10-8

10-6

10-4

10-2

10-0

Hooge parameter

Vg (V)

102

H

FIG. 2: Ultra-low noise in 1D Si:P wires. (a) The power spectral density of the conductance fluctuations, SG /G2 as a function of frequency f , at 4.2 K for wire W1 at different gate voltages. (b) f SG /G2 as a function of frequency f , at 4.2 K for wire W1 at different gate voltages. The Hooge parameter γH as a function of gate voltage for (c) wire W1 and (d) wire W2 at 4.2 K. (e) Comparison of the noise magnitude in terms of Hooge parameter γH for various (1D) systems.

13


Nano Letters

(b)

0.9

10

-6

W1, 4.2K

4.2K

ITRS 2020, W1 ITRS 2020, W2

0.6 10

-7

2

0.3

! Vg " #( V )

2

G (e /h)

(a)

0.0 80

-6

40 10

-8

(dG/dVg)2 (a.u.)

2 2 < G < /G

10

10

-8

10

-9

2

W1, 4.2K

W1 W2 10

-10

-0.75

-0.50

-0.25

0 W1, 4.2K

0.0

0.50

0.75

Vg= -0.55V

G

2

Vg (V)

0.25

-4

Charge traps e

Vg 2

(c)

(d) -0.3

G (10 e /h)

10-10 -0.6

0.00

Vg (V)

SiO2 240

260

280

Vg (V)

W1, 4.2K

G (e /h)

1D wire

Vg= -0.47V

2

Si substrate

Vg 10-3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 14 of 16

240

280

320

Time (s)

FIG. 3: Random Telegraphic signals (RTS) and noise due to charge traps. (a) The normalized variance ⟨δG2 ⟩/⟨G2 ⟩ =

∫

SG /G2 df as a function of gate voltage Vg for Wire W1 at

4.2 K (bottom panel). The axis on the right shows the dependence of square of transconductance (dG/dVg )2 on Vg . The top panel shows the G vs Vg curve within the same gate voltage range. (b) The variance of gate voltage fluctuations, ⟨δVg2 ⟩ for wires W1 and W2 at 4.2 K calculated using the method described in text. The dashed lines represent the ITRS requirements for noise in CMOS transistors for year 2020. (c) Schematic showing the exchange of charge among traps at the Si/SiO2 interface which causes the conductance fluctuations. (d) The time series of conductance fluctuation at 4.2 K for wire W1 at gate voltages −0.55 V (top) and −0.47 V (bottom) and the corresponding gate fluctuations caused is illustrated on the coulomb blockade peak (schematic) on the right.

14


0.001

3

0.4

Cts Vg

(e) 0

Cg 2 0.0 1

20

-0.4 2

G (e2/h)

(d)

Top gate

0.075

Vg

Cg

Cts

6

8

10

0

0

0

(f)

0.025

10

20

-3.6

6 4

-4.0 D2 2

4

6

8

10

Sweep No.

2

30

40

Peak shift (mV)

8

-2

C tg

4

Sweep No.

Dot D2 (top gate)

8

Count

Vtg Vts

2

SiO2

G (10 e /h)

D1

(b)

Dot D1 (in-plane gate)

40

Count

Vts

2

Plunger gate

G (e2/h)

(c)

Quantum Dot of P atoms Drain

-3

Source

Vg (V)

(a)

Vtg (V)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

G (10 e /h)

Page 15 of 16

4

0

0

10

20

30

40

Peak shift (mV)

FIG. 4: Comparison of conductance fluctuations in epitaxial in-plane gated quantum dot and surface gated quantum dot formed on a low temperature oxide. Schematic of quantum dot device (a) D1 showing the source, drain and in-plane epitaxial plunger gate and (b) D2 showing a surface gate on a low temperature oxide grown on the top epitaxial Si. The right panel shows the schematics of the relevant capacitances arising due to surface trap charging events. Vg and Vtg are the in-plane and top gate voltage respectively which couple to the quantum dot via capacitances Cg and Ctg respectively. Vts is the fluctuating voltage due to surface trap charging events which is coupled to the quantum dot via capacitance Cts . (b) A 2D map of the Coulomb blockade oscillations as a function of gate voltage (in-plane gate for D1 and top gate for D2) and sweep number for quantum dot (c) D1 and (d) D2 at 4.2 K. A single gate voltage scan is shown on the left. A histogram of the horizontal shift in the position of Coulomb blockade peaks ∆Vg for successive gate voltage sweeps for quantum dot (e) D1 and (f) D2.

15


Nano Letters Page 16 of 16

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