Uniform Self-rectifying Resistive Switching Behavior via Preformed

From the electroforming-free behavior, it can be assumed that such CPs present ..... Cell with CMOS Logic Compatible Process IEEE Int. Electron Device...
0 downloads 0 Views 5MB Size
Download PDF
Research Article www.acsami.org

Uniform Self-rectifying Resistive Switching Behavior via Preformed Conducting Paths in a Vertical-type Ta2O5/HfO2−x Structure with a Sub-μm2 Cell Area Jung Ho Yoon, Sijung Yoo, Seul Ji Song, Kyung Jean Yoon, Dae Eun Kwon, Young Jae Kwon, Tae Hyung Park, Hye Jin Kim, Xing Long Shao, Yumin Kim, and Cheol Seong Hwang* Department of Materials Science and Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul 151-744, Republic of Korea ABSTRACT: To replace or succeed the present NAND flash memory, resistive switching random access memory (ReRAM) should be implemented in the verticaltype crossbar array configuration. The ReRAM cell must have a highly reproducible resistive switching (RS) performance and an electroforming-free, self-rectifying, lowpower-consumption, multilevel-switching, and easy fabrication process with a deep subμm2 cell area. In this work, a Pt/Ta2O5/HfO2−x/TiN RS memory cell fabricated in the form of a vertical-type structure was presented as a feasible contender to meet the above requirements. While the fundamental RS characteristics of this material based on the electron trapping/detrapping mechanisms have been reported elsewhere, the influence of the cell scaling size to 0.34 μm2 on the RS performance by adopting the vertical integration scheme was carefully examined in this work. The smaller cell area provided much better switching uniformity while all the other benefits of this specific material system were preserved. Using the overstressing technique, the nature of RS through the localized conducting path was further examined, which elucidated the fundamental difference between the present material system and the general ionic-motion-related bipolar RS mechanism. KEYWORDS: self-rectification, resistive random access memory, electroforming-free, vertical integration structure, low power consumption, uniform switching

■

INTRODUCTION The resistance switching random access memory (ReRAM) in the vertical-type three-dimensional (3D) crossbar array (CBA) configuration is attracting a great deal of attention as one of the most promising next-generation nonvolatile memory (NVM) devices that can replace or succeed the current vertical-type NAND flash memory.1−5 While ReRAM has been extensively studied in the past two decades, there are several critical problems that remain unsolved from the points of view of integration and materials. The problems related with the 3D integration of ReRAM were extensively reviewed in a recent review article.6 From the point of view of materials, a feasible ReRAM cell must fulfill the requirements of electroformingfree, low variability in resistive switching (RS) at a very low operation current level (6500 μm2), where the resistance value of the low resistance state (LRS) was independent of the device area, suggesting the spatially localized switching mechanism of eBRS. Therefore, verifying the functionality of this material system with a crossbar-type geometry and a 3D vertical-type structure with a much smaller electrode area is another crucial task for this material to be considered a possible candidate for the next Received: May 11, 2016 Accepted: June 27, 2016

A

DOI: 10.1021/acsami.6b05657 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Research Article

ACS Applied Materials & Interfaces NVM. As the two functional layers were grown via ALD, the 3D compatibility is expected to be excellent, but experimental proof of this is necessary. In this work, eBRS memory cells composed of Pt/Ta2O5/ HfO2/TiN stacked layers were fabricated with the configuration of a planar crossbar-type structure with an ∼4 μm2 cell size and a vertical-type structure with an ∼0.34 μm2 cell size. To alleviate the cross-talk effect in the planar CBA and vertical-type structure, a 1xN configuration was adopted. These types of CBA and vertical structure samples showed highly uniform RS performances, electroforming-free behavior that does not cause switching parameter variability, over 103 self-rectifying functionality, and low current switching (below 10 nA) and multilevel switching behaviors, which are compatible with the previous results from larger-area devices.13 There are certain discrepancies, however, especially in the area-dependent LRS resistance, which needs additional attention from this material. The additional contribution of this work to a more precise understanding of the aforementioned material system can be found in the elucidation of the experiment conditions where the normal eBRS performance was seriously and permanently disturbed. This behavior was ascribed to the complete disruption of the local conduction path (CP) formed during the device fabrication, which could be further confirmed through conductive atomic force microscopy (CAFM). This work will contribute to the development of ReRAM based on the aforementioned eBRS mechanism.

■

EXPERIMENTAL PROCEDURE

Figure 1. (a) Low-magnification cross-sectional TEM image showing the overall structure of the deposited HfO2 layer on the etched BE and SiO2 layers. (b) Zoomed-in HRTEM image of the Pt(TE)/Ta2O5/ HfO2/TiN(BE) structure.

The standard photolithography technique composed of liftoff processes for Pt TE and TiN BE was used for the planar CBA and vertical-type sample fabrication, where the line width was fixed at 2 μm. For fabricating the vertical-type structure, 25 nm thick SiO2/50 nm thick TiN/100 nm thick SiO2 layers were deposited on a Si wafer, using the plasma-enhanced chemical vapor deposition system (STS, 310PC) for the SiO2 layers, and DC magnetron reactive sputtering (AMAT, ENDURA 5500) for the TiN layer. Then, the stacked layers were etched into a line shape using reactive-ion etching (Oxford Instruments, RIE 80 plus) with CF4 and O2 gas, where the line width was 2 μm. Because of the relatively low selectivity and mask erosion during the dry etching step, a significantly slanted etching profile was achieved, as shown in Figure 1a, which shows the cross-sectional transmission electron microscopy (TEM) image of one side of the vertical device after the HfO2 layer deposition. In this case, the exposed area of the TiN film on the side walls of this line structure played the role of a BE. After removing the photoresist mask, 10 nm thick HfO2 and 10 nm thick Ta2O5 layers were sequentially deposited via ALD and PEALD. ALD of the HfO2 film was performed using Hf[N(CH3)(C2H5)]4 and O3 as the Hf precursor and oxygen source, respectively, at a 280 °C substrate temperature using a traveling-waver type ALD reactor. The PEALD Ta2O5 layer was performed in another shower-head-type ALD reactor using Ta(NtBu)(NEt2)2Cp as a Ta precursor, where tBu, Et, and Cp represent the tertiary-butoxy, ethoxy, and cyclopentadienyl groups, respectively, and H2O-activated plasma (300 W) as an oxygen source, at a 200 °C substrate temperature. The details of the ALD of HfO2 and Ta2O5 were reported elsewhere.13 Then, another line-shaped photomask was formed in a transverse direction to the BE layer, and a 50 nm thick Pt layer was deposited via electron beam evaporation (Maestech, ZZS550-2/D), and was lifted off to form the TE, which finalized the device fabrication. The width of the TE was 2 μm. A planar CBA cell with a 4 μm2 area was also fabricated, adopting an identical TiN BE and an identical HfO2/ Ta2O5/Pt TE, where the line widths of the BE and TE were both 2 μm. The cross-section of the Pt/Ta2O5/HfO2−x/TiN sample was observed using high-resolution TEM (HRTEM, JEOL, JEM-2100F). CAFM (JSPM-5200) in contact mode biased with +5 V was used for

correlating the morphology and local electric conduction properties of the HfO2 film on the TiN BE. 5 V was a just enough voltage to achieve the local current flow but not to alter the local conductivity even after the repeated CAFM scan. The RS behaviors of the fabricated planar and vertical cells were measured using an HP4155A semiconductor parameter analyzer, in the voltage sweep mode, and bias was applied to the TE while the BE was grounded.

■

RESULTS AND DISCUSSION Figure 1a shows the low-magnification cross-section TEM image to present the overall structure of the vertical device, where the slanted dry etching profile was identified, which resulted in the 85 nm length of the device along that direction. Therefore, the electrode area of the vertical device was 0.34 μm2 (85 nm (inclined plane) × 2 μm (width of top electrode) × 2 (two inclined planes per device)). Figure 1b shows the zoomed-in HRTEM image of the Pt(TE)/Ta2O5/HfO2/ TiN(BE) structure, where each thin-film layer was well distinguishable, and the Pt TE, amorphous Ta2O5, crystallized HfO2−x, and TiN BE from top to bottom could be recognized. The HfO2/TiN interface is also clearly defined, but a small amount of amorphous material can be observed, which could be the TiOxNy material that is consistent with the previous report for a planar device.13 The thickness of TiN BE appears much thinner than the initial 50 nm, but it was due to the fact that the TEM picture was taken at the edge of the memory cell where the slanted etching profile resulted in the thinner TiN thickness. The self-rectifying RS I−V curves up to 130 cycles are included in Figure 2a, where a compliance current (Icc) of 10 B

DOI: 10.1021/acsami.6b05657 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Research Article

ACS Applied Materials & Interfaces

Figure 2. (a) Resistive switching I−V curves and (inset figure of (a)) on/off current and F/R ratio of the vertical Pt/Ta2O5/HfO2/TiN cell as a function of the absolute voltage. (b) Endurance property up to ∼103 times using DC measurement. (c) Retention data of the LRS and HRS at room temperature and 125 °C up to 104 s (measured at 8 V) of the vertical cell. (d) Icc dependency at LRS of the vertical cell. (e) Multilevel cell switching performance and inset shows the standard deviation value of the planar and vertical cells. (f) I−V switching curves from 15 independent cells demonstrating the uniform cell-to-cell performance.

resistance state (HRS). The dielectric layer thickness, stacking sequence, and electric-field distribution by the appropriate dielectric constant distribution were optimized for such operation in this structure. It was further elucidated that the trap sites are located at localized positions, preferentially along the grain boundaries of the HfO2 layer, making the switching spatially localized. The inset figure in Figure 2a shows the resistance ratio between HRS and LRS and the forward/reverse rectification ratio (F/R ratio) as a function of the absolute voltage, which was derived from the I−V curves in Figure 2a. The maximum resistance (HRS/LRS) and the F/R rectification ratio of ∼2 × 103 were achieved, while the power consumption of this RS system was very low. In fact, these HRS/LRS and F/R ratio values would have been even higher if the real off-state current were measured because the detected current level of HRS was limited (overestimated) by the detection limit of the apparatus (∼10−12 A). Figure 2b shows the endurance property read at 8 V, where the switching was performed by DC I−V sweep. The HRS/LRS ratio was maintained at ∼103 up to 103 switching cycles, and the distributions of the resistance values of both states were highly uniform. The data retention of the LRS (Icc = 50 nA) and HRS was tested by measuring the current under the read voltage application (8 V) at room temperature and at 125 °C up to 104 s, as shown in Figure 2c. Both the HRS and the LRS states stably retained their current values at room temperature, but the HRS current slightly increased after ∼102 at 125 °C. A sufficiently high resistance ratio was maintained up to ∼104 s, however, even after the degradation. This type of degradation in the retention performance at 125 °C for the case of HRS could be understood from the hypothesis that some electrons are transported from the TiN electrode to the empty deep traps in the HfO2 layer. Figure 2d demonstrates the Icc dependency of LRS achieved by setting Icc from 500 pA to 50 nA during set switching operation. The LRS

nA was used to prevent the breakdown of the device. The general switching sequences are shown by the numbers included in Figure 2a: the I−V curves of the pristine state (curve 1, open square symbol); the on-state (curve 2), which was induced by the first voltage sweep up to +15 V with an Icc of 10 nA; the resetting curve (curve 3), where the voltage swept down to −10 V; and the off-state (curve 4), which was induced by the previous voltage sweep into the negative voltage direction. The almost identical shapes of the set curves (curve 1) to the curves from the pristine and off-states (curves 3 and 4) reveal that this sample shows electroforming-free RS behavior. Also, this unique shape of the I−V curves is almost identical to the previous result obtained from the same material system with the planar-type, large-cell-area (>6500 μm2) sample.13 These results imply that the same switching mechanism dominates the whole RS behavior in this material system even down to the 0.34 μm2 cell area. The detailed switching mechanism according to these sweep sequences was discussed in detail elsewhere,13 but a short summary is given below. Among the two dielectric layers, the HfO2 works as the resistance switching layer by trapping and detrapping electrons at the deep trap sites (1.0 eV trap depth) while the Ta2O5 remains intact during the whole switching cycle and creates a high Schottky barrier with a high-work-function Pt to constitute the rectifying functionality. The HfO2/TiN interface constitutes a quasi-Ohmic contact, making the electron injection and subsequent carrier trapping fluent under the sufficiently high positive-bias application to the Pt TE (set step). When the traps are filled with electrons, further carrier transport was not interfered with by the presence of traps, changing the system to LRS. Under a sufficiently large value of negative bias, the trapped electrons were detrapped by draining them off to the TiN while the electron injection from the Pt TE was sufficiently suppressed by the high Schottky barrier at the Pt/Ta2O5 interface; as such, the system switches back to the high C

DOI: 10.1021/acsami.6b05657 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Research Article

ACS Applied Materials & Interfaces resistances were read at 8 V, and the HRS resistance was ∼1013 Ω. The LRS resistance had an almost linear relationship with Icc, as can be seen from the best-linear-fitted graph (red dashed line). The uniform distribution of LRS was slightly degraded for the smaller Icc values, as can be understood from the larger standard error, which is due to the relatively large statistical variation of carrier trapping with a lower Icc. Figure 2e demonstrates a multilevel switching performance obtained by changing Icc from 1 to 10 nA during the set switching of the planar and vertical cells. The resistance values at each state were obtained by repeated (50-time) switching, and were read at 8 V. The distribution of the resistance values of the LRS in the vertical cell structure was extremely narrow even at the Icc of 1 nA, suggesting that highly uniform low current switching is possible, while the planar cell with a larger area showed a certainly worse distribution. The quantitative data for the standard deviations for the two types of devices are shown in inset of Figure 2e, which again confirms that the standard deviation was much lower at a smaller-area device. While the possibility that the geometric differences (i.e., planar vs vertical) can influence the switching uniformity cannot be completely disregarded, the main reason for such discrepancy must be the ∼12-fold different electrode areas. The area-dependent resistance values of these two devices (2- to 3-fold increase in resistance with an ∼12-fold area decrease) are certainly different from the almost completely area-independent results for the much-larger-area devices. This means that there is a high chance of involving a notably high conducting path(s) in largearea cases, making their LRS resistance area-independent. For such submicron area cases, however, the chance of involving notably high conducting spots decreases, and more uniform current conduction occurs. Nevertheless, the still smaller variation in LRS resistance compared with the degree of variation in the electrode area suggests that the current flow is mediated by the local CPs. Such considerations were further examined in the following experiments. Figure 2f shows the switching I−V curves from the 15 cells confirming the high cellto-cell uniformity. Although the possibility that the cell area can be slightly varied during the cell fabrication process, mostly due to the relatively uncontrolled etching profile, cannot be completely excluded, the resistive switching behavior from each cell was highly uniform. Figure 3a shows the schematic image showing the electron conduction paths at LRS in this material system, which was reproduced from ref 13, where the CPs are most likely located at the grain boundaries (GBs). From the electroforming-free behavior, it can be assumed that such CPs present from the asfabricated state and are not generated by electrical stress. This model is further supported by the following experiments. Excessive electrical stress was applied to the vertical device to determine if there could be any permanent change in the I−V curves from the change in the status of the CPs, as shown in Figure 3b. The switching sequences are shown by the numbers included in Figure 3b: the I−V curves of the pristine state (curve 1, black line); the on-state (curve 2, red line), which was induced by the first voltage sweep up to +17 V with an Icc of 10 nA; and 15 V, to which the device was again swept to switch it to LRS, but with no Icc setting, after resetting the device by sweeping the voltage down to −10 V (not shown here) (curve 3, blue line). In this case, the I−V curve was almost identical to curve 1 up to the current value of 10 nA, but when the current value became higher than ∼50 nA, the current became unstable at even higher voltages, as shown in Figure 3c. There were

Figure 3. (a) Schematic image of the electron conduction paths at LRS in the proposed material system. (b) Electrical overstressing measurement by conducting the set process without Icc. (c) Zoomedin I−V curves showing abrupt current drop and jump (CP rupture and rejuvenation). (d) Even more excessively high voltage stress up to 30 and 40 V, causing the partial and complete disruption of the CPs.

several abrupt current drop and recover cases, as represented by the numbers 1, 2, and 3. Such an unstable I−V behavior can be ascribed to the competition between the CP rupture by the excessive Joule heating at the high voltages and their rejuvenation through further electron trapping. The temporary current decrease under this highly positive-bias region was certainly different from the normal reset in the negative-bias region, as can be understood from the subsequent I−V sweeps. After the occurrence of this unstable I−V behavior, the subsequent I−V sweep (curve 4, purple line) showed a much lower current than the previous LRS current despite the fact that the reset voltage (negative voltage) had not been applied. The zoomed-in I−V curve of the portion of the pink background in Figure 3b is appended in Figure 3c, where the 4th sweep curve (purple curve in Figure 3b and red dotted data in Figure 3c) shows an almost coincident current level to the final current values of the previous sweep (blue triangle in Figure 3b and black square data in Figure 3c). This means that some portion of the CPs was actually disrupted by such an excessive I−V sweep, even though the bias polarity was consistent with the set switching. When the reset process (curve 5, green line in Figure 3b) was subsequently performed, the device switched back to its HRS, as can be understood from the low current value in the positive-bias region (curve 6, yellow line in Figure 3b). In fact, however, it showed a varied I−V character compared with the previous HRS; the current level at the lower-voltage region slightly increased, which may reflect the damage effect of the non-CP area under the previous serious I−V stress condition, whereas the current in the highvoltage region was slightly lower, which reflected the (partly) disrupted CPs. Curve 6 also corresponds to the set curve with an Icc of 10 nA. The subsequent I−V sweep showed that the device was again switched to LRS, but with lower conductance (curve 7, orange line in Figure 3b). These sets of experiments indicated that the excessive current flow in the highly set bias region actually permanently disrupted some part of the original D

DOI: 10.1021/acsami.6b05657 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Research Article

ACS Applied Materials & Interfaces

Figure 4. (a) Reproduced I−V curve of the red triangle symbol in Figure 3(d) with four specific regions, and (inset figure of (a)) maximum current of the CBA and vertical cells during the set process. (b) Schematic images of the probable model for interpreting the four regions in (a).

current level is dependent on the cell area in this area range. The total LRS current (Itotal) of the device can be expressed by eq 1.

CPs. Such behavior was further confirmed by the experimental results shown in Figure 3d. In this case, another pristine ReRAM cell from the vertical device was taken, and it was stressed up to 30 V without setting the Icc (black closed circle symbol). As expected, the device was initially in HRS and was switched to LRS at ∼13 V, and the current became unstable when the current level became higher than ∼1 μA, and eventually decreased to ∼10 nA at 30 V. The subsequent I−V sweep showed that the device was indeed switched to LRS but with much lower conductance, and the eventual conductance level was consistent with the final status of the device during the previous sweep. Then, the device was switched back to HRS by the subsequent I−V sweep into the negative-bias region (data not shown), and was again stressed with positive bias, this time up to 40 V. The device was indeed switched back to HRS as can be understood from the low current level in the low-voltage region (< ∼13 V) of the red closed-triangle symbol data in Figure 3d. As for the previous case, the device showed an unstable I−V behavior in the voltage region from ∼13 to ∼25 V, and the current value substantially decreased at the voltages > ∼30 V. Such excessively high voltage stress appeared to have completely destroyed the CPs, and the current level became almost identical to the HRS, as can be understood from the subsequent I−V sweep represented by the open-triangle symbol data. When this significant current drop occurred, no further RS was possible, suggesting that the CPs had been completely destroyed and could not be electrically rejuvenated in the material system. The probable model for interpreting these results is presented in Figure 4, where the graph in Figure 4a is the reproduction of the red triangle symbol curve in Figure 3d for the sake of convenience. In addition, the inset figure in Figure 4a, which shows the maximum current level after the set operation of the planar CBA cell with 4 μm2 and the verticaltype cell with 0.34 μm2, demonstrates that the maximum

Itotal = Ileak + ICP(n)

(ICP(n) ∼ n × ICP)

(1)

In eq 1, Itotal is composed of Ileak and ICP(n), where Ileak is the leakage current of the oxide layer, which can be assumed to be invariant during all the RS sequences, and ICP(n) is the current that flowed through the CPs and is a function of the number (n) of the trap-filled CPs among the total N CPs present. Therefore, the fluent eBRS in this device can be ascribed to the variation of ICP(n). As the set switching is understood as the filling of the traps with the injected electrons along each CP, HRS (or the pristine state) is understood as the state where there are no (or there is a very small number of) CPs with filled traps (region ① in Figure 4a and panel ① in Figure 4b). At the set moment, most of the CPs are filled with the injected electrons from the TiN BE, which is represented by region ② in Figure 4a and panel ② in Figure 4b. During the application of the high-voltage stress, some of the filled CPs were disrupted by the excessive Joule heating effect, which was accompanied by the negative differential resistance effect (region ③ in Figure 4a and panel ③ in Figure 4b). When almost all the CPs were disrupted, the device came to show a current almost equivalent to HRS, and no further set switching was possible (region ④ in Figure 4a and panel ④ in Figure 4b). As the electrode area increased, N also increased, and the current level of LRS thus increased, as shown by the representative I−V curves of the planar and vertical cells shown in the upper-left inset figure in Figure 4a. It must be concurrently noted, however, that the CPs do not have identical electrical properties, and as such, the electrode area dependency was lower than the linear relationship. When the electrode area becomes very large, the possibility of involving nonuniform CPs increases, and only E

DOI: 10.1021/acsami.6b05657 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Research Article

ACS Applied Materials & Interfaces

Figure 5. (a) Topographic AFM image of the HfO2 (5 nm)/TiN layer and (b) the corresponding local current image. (c) Overlapped topographic and current images and (d) profile of the topographic and current images.

probable that these local spots constitute the CPs in the fabricated devices.

several highly conducting CPs dominate the total conductance, which resulted in the almost no area dependency.13 As such electroforming-free behavior in the RS performance of this device was considered related to the preformed CPs in the HfO2 layer, CAFM was conducted on the surface of the 5 nm thick HfO2 on the TiN electrode before the Ta2O5 layer was deposited. The 10 nm thick HfO2 layer, which was used in the ReRAM devices, was too insulating to be examined via CAFM. While the possibility that the 5 and 10 nm thick HfO2 films could have different microstructures cannot be completely excluded, the memory cell composed of 5 nm thick HfO2 film showed similar electrical properties in ref 13, and thus, examining 5 nm thick HfO2 film by CAFM could be relevant to the present work. In this CAFM work, the focus was placed on the relative locations of the topological feature and the local conducting spots. Figure 5a shows the topographic images of the HfO2/TiN layer, and Figure 5b shows the corresponding local current images. Panels (c) and (d) in Figure 5show the overlapped image and the profiles of the topographic and current images along the arrows shown in panels (a) and (b) in Figure 5. The high current paths are consistent with the locally recessed region of the film. The 5 nm thick film might not have been well crystallized. As such, the recessed region could not be assigned to the GBs, but it is highly probable that these regions would develop into GBs in the thicker films. This is consistent with the results of the previous detailed CAFM study on the crystallized and amorphous HfO2 films.14 Therefore, it is highly

■

CONCLUSION It was concluded that the scaling down of the cell area and the fabrication of the device in the form of a vertical structure did not adversely affect the highly promising and reproducible selfrectifying RS performance in the Pt/Ta2O5/HfO2/TiN structure. Even with lower power consumption, extremely uniform low-current multilevel switching was achieved when the device area was 0.34 μm2. By applying excessive voltage stress to the vertical device, the presence of CPs was confirmed, which must be formed during the device fabrication step and not by the electrical stress. While the permanent disruption of the CPs by the excessive electrical stress was not optimal for the ReRAM operation, such a problem may not occur in actual operation because such excessive stress will not be used. Besides, such behavior implies a critical merit of this type of ReRAM device over other electric-field- or flown-charge-driven RS material systems, where sufficient electrical stress is the prerequisite to inducing a stable RS. In such cases, the electrical stress is the critical ingredient for initiating the RS (electroforming), but it also implies that the electric field inevitably influences the stability and reproducibility of memory devices by modifying the configuration of the ionic defect channel. In this case, on the contrary, the CPs were originally formed through a certain chemical method during the device fabrication and were supposed to be independent of the F

DOI: 10.1021/acsami.6b05657 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Research Article

ACS Applied Materials & Interfaces

(14) Yoon, J. W.; Yoon, J. H.; Lee, J. H.; Hwang, C. S. Impedance Spectroscopic Analysis on Effects of Partial Oxidation of TiN Bottom Electrode and Microstructure of Amorphous and Crystalline HfO2 Thin Films on Their Bipolar Resistive Switching. Nanoscale 2014, 6, 6668−6678.

electrical stress during the device operation. Therefore, as long as the operation conditions are appropriately selected, this device will be fundamentally immune to the variability and nonuniformity during the operation. As the area-dependent data imply, such merit will be further strengthened when the device area is further decreased.

■

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Notes

The authors declare no competing financial interest.

■

ACKNOWLEDGMENTS This work was supported by the Global Research Laboratory Program (No. NRF-2012K1A1A2040157) of the Ministry of Science, ICT, and Future Planning, and by a grant from the National Research Foundation of Korea (NRF) (No. NRF2014R1A2A1A10052979) of the Republic of Korea.

■

REFERENCES

(1) Baek, I. G.; Park, C. J.; Ju, H.; Seong, D. J.; Ahn, H. S.; Kim, J. H.; Yang, M. K.; Song, S. H.; Kim, E. M.; Park, S. O.; Park, C. H.; Song, C. W.; Jeong, G. T.; Choi, S.; Kang, H. K.; Chung, C. Realization of Vertical Resistive Memory (VRRAM) Using Cost Effective 3D Process. IEEE Int. Electron Devices Meet. 2011, 31.8.1−31.8.4. (2) Wang, C.; Tsai, Y.; Lin, K.; Chang, M.; King, Y.; Lin, C.; Sheu, S.; Chen, Y.; Lee, H.; Chen, F. T.; Tsai, M. Three-dimensional 4F2 ReRAM Cell with CMOS Logic Compatible Process. IEEE Int. Electron Devices Meet. 2010, 58, 2466−2472. (3) Cha, E.; Woo, J.; Lee, D.; Lee, S.; Song, J.; Koo, Y.; Lee, J.; Park, C. G.; Yang, M. Y.; Kamiya, K.; Shiraishi, K.; Magyari-Köpe, B.; Nishi, Y.; Hwang, H. Nanoscale (∼10nm) 3D Vertical ReRAM and NbO2 Threshold Selector with TiN Electrode. IEEE Int. Electron Devices Meet. 2013, 10.5.1−10.5.4. (4) Yoon, H. S.; Baek, I.-G.; Zhao, J.; Sim, H.; Park, M. Y.; Lee, H.; Oh, G.-H.; Shin, J. C.; Yeo, I.-S.; Chung, U.-I. Vertical Cross-point Resistance Change Memory for Ultra-high Density Non-volatile Memory Applications. Symp. VLSI Technol. 2009, 26−27. (5) Woo, J.; Lee, D.; Cha, E.; Lee, S.; Park, S.; Hwang, H. Vertically Stacked ReRAM Composed of a Bidirectional Selector and CB-RAM for Cross-Point Array Applications. IEEE Electron Device Lett. 2013, 34, 1512−1514. (6) Seok, J. Y.; Song, S. J.; Yoon, J. H.; Yoon, K. J.; Park, T. H.; Kwon, D. E.; Lim, H.; Kim, G. H.; Jeong, D. S.; Hwang, C. S. A Review of Three-Dimensional Resistive Switching CrossBar Array Memories from the Integration and Materials Property Points of View. Adv. Funct. Mater. 2014, 24, 5316−5339. (7) Akinaga, H.; Shima, H. Resistive Random Access Memory (ReRAM) Based on Metal Oxides. Proc. IEEE 2010, 98, 2237−2251. (8) Kim, K. M.; Jeong, D. S.; Hwang, C. S. Nanofilamentary Resistive Switching in Binary Oxide System; a review on the present status and outlook. Nanotechnology 2011, 22, 254002. (9) Sawa, A. Resistive Switching in Transition Metal Oxides. Mater. Today 2008, 11, 28−36. (10) Di Ventra, M.; Pershin, Y. V. Memory Materials: a Unifying Description. Mater. Today 2011, 14, 584−591. (11) Waser, R.; Dittmann, R.; Staikov, G.; Szot, K. Redox-Based Resistive Switching Memories − Nanoionic Mechanisms, Prospects, and Challenges. Adv. Mater. 2009, 21, 2632−2663. (12) Yang, J. J.; Strukov, D. B.; Stewart, D. R. Memristive Devices for Computing. Nat. Nanotechnol. 2013, 8, 13−24. (13) Yoon, J. H.; Song, S. J.; Yoo, I.; Seok, J. Y.; Yoon, K. J.; Kwon, D. E.; Park, T. H.; Hwang, C. S. Highly Uniform, Electroforming-Free, and Self-Rectifying Resistive Memory in the Pt/Ta2O5/HfO2‑x/TiN Structure. Adv. Funct. Mater. 2014, 24, 5086−5095. G

DOI: 10.1021/acsami.6b05657 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX