Unit Processes in the Manufacture of Integrated Circuits - American

1 Unit Processes in the Manufacture of Integrated Circuits Pieter Stroeve

Downloaded by 92.222.17.136 on May 29, 2018 | https://pubs.acs.org Publication Date: October 2, 1985 | doi: 10.1021/bk-1985-0290.ch001

Chemical Engineering Department, University of California, Davis, CA 95616

The fabrication of integrated circuits is very complex. The intricacy of a particular process can be understood by considering the individual unit processes used to make the product. Key unit processes are consistently used in the manufacture of integrated circuits. An improved understanding of the basic physical and chemical fundamentals of each process will help the manufacturing engineer in controlling the uniformity of the product or to design new processes.

The microelectronic revolution i s the term u t i l i z e d for the phenomena of manufacturing large numbers of e l e c t r o n i c components on t h i n s i l i c o n chips and the u t i l i z a t i o n of these chips in sophist i c a t e d e l e c t r o n i c devices. The push for miniaturization came i n part because of economic needs to produce c i r c u i t s at much lower cost and at lower power requirements, the development of small e l e c t r o n i c devices, and the need to produce high speed e l e c t r o n i c computers. The microelectronic revolution began with the invention of the t r a n s i s t o r in the l a t e 1940 s and has grown to a m u l t i - b i l l i o n d o l l a r industry today. The growth of the industry i s t r u l y amazing considerina that the f i r s t integrated c i r c u i t s were marketed i n early 1960 s . At that time, integrated c i r c u i t s were "small-scale" i n the sense that about 10 components would be present per single chip. In the mid to the end of the 1960*s medium-scale integrated c i r c u i t s were b u i l d containing up to 1024 components per c i r c u i t , or a IK b i t c i r c u i t . In the 1970*s l a r g e scale c i r c u i t s were b u i l t and i n the 1980 s we now speak of very large scale integrated c i r c u i t s (VLSI). Presently, c i r c u i t s are b u i l t with 262,144 components per c i r c u i t or 262K, which i s equal to 2 components on a single c h i p . In the near future, 1M b i t chips w i l l be a standard product. This number i s staggering ?

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0097-6156/85/ 0290-0001 $06.00/ 0 © 1985 American Chemical Society

Stroeve; Integrated Circuits: Chemical and Physical Processing ACS Symposium Series; American Chemical Society: Washington, DC, 1985.


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C H E M I C A L A N D PHYSICAL PROCESSING O F INTEGRATED CIRCUITS

considering that a chip i s approximately 0.5 by 0.5 cm. Because of the larger number of components, the cost per component i s a small f r a c t i o n of a penny (O.Oljzf), and the basic cost per chip continues to decrease even though the number of components per chip have increased. The design of 262K and 1M b i t chips i s a very complicated process. Computer-aided design techniques are now used to perform many of the time-consuming tasks such as the r e l a t i v e placement of t r a n s i s t o r s , r e s i s t o r s and diodes, and the design of interconnect i o n s . Large computer programs and data bases are required to perform such design c a l c u l a t i o n s . The computer-aided design techniques can be used to v e r i f y that the design conforms to the constraints imposed by the integrated c i r c u i t f a b r i c a t i o n process. The manufacture of integrated c i r c u i t s involve a series of l i t h o g r a p h i c , deposition, and etching steps to fabricate patterned l a y e r s . This process i s often c a l l e d planar processing or planar technology. The manufacture of t h i n f i l m products does not only apply to the making of integrated c i r c u i t s but also magnetic bubble memories, t h i n f i l m recording heads, tapes and d i s k s . The p h y s i c a l and chemical processes c a r r i e d out involve heat and mass t r a n s f e r , momentum t r a n s f e r , surface phenomena, high temperature chemistry, r a d i a t i o n , e t c . Although the material discussed i n t h i s book focuses on the manufacture and fundamentals of integrated c i r c u i t s , many of the basics are applicable to the f a b r i c a t i o n of other thin f i l m devices. Planar Technology Wafer processing i s often c a l l e d planar processing or planar technology because small and t h i n planar structures are b u i l t on thin wafers (~ 500 ym t h i c k ) of u l t r a pure s i l i c o n or germanium or any other suitable semi-conductor m a t e r i a l . The thin wafers are cut from a rod of pure m a t e r i a l , which i s a single c r y s t a l , and then polished. The structures b u i l t on the surface of the wafer are e l e c t r i c a l components such as r e s i s t o r s , capacitors, diodes, junct i o n t r a n s i s t o r s , MOSFET t r a n s i s t o r s , e t c . Each wafer contains 200 to 500 chips, with each chip i d e n t i c a l to the others. In any wafer fabrication process, the surface region of the wafer undergoes a number of processing steps involving changes i n chemical composition and physical s t a t e , as well as the c o n t r o l l e d deposition of material on the wafer's surface. T y p i c a l l y , the thickness of the layers of material may be from 0.1 ym to 1 ym t h i c k while the width and length of the c h a r a c t e r i s t i c features within the l a y e r s , which define the dimensions of each e l e c t r i c a l component, are a few microns. For 1 Megabit RAMs the dimensions are now less than 1.7 ym. The control of the processing steps must be extremely precise i n order to make a uniform product from chip to chip. A simple example of the manufacture of a component


1. S T R O E V E

The Manufacture of Integrated Circuits

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i s the capacitor. A capaqitor can be made by l o c a l l y o x i d i z i n g the semiconductor substrate, which i s s i l i c o n here, to s i l i c o n dioxide. Whereas s i l i c o n i s a semiconductor, s i l i c o n dioxide i s an excellent i n s u l a t o r . I f the thin layer of Si02 separates a conductor, such as a metal contact, from the semiconductor, then a capacitor i s formed. E l e c t r i c a l contact to the semiconductor material can be made i n a variety of ways, e . g . , by etching an opening i n the s i l i c o n dioxide and providing a metal contact there. Transistors are more complex i n structure than capacitors and depend on the p a r t i c u l a r design of the t r a n s i s t o r . Figure 1 shows a cross-section of a bipolar npn t r a n s i s t o r which uses s i l i con dioxide as an i s o l a t o r to separate i t from other e l e c t r i c a l components on the wafer's surface. There are, of course, a variety of ways to i s o l a t e e l e c t r i c a l components so that the variety of d i f f e r e n t designs of components i s numerous. As a consequence, the f a b r i c a t i o n processes are also very d i f f e r e n t . Unit Processes i n Fabrication In any wafer f a b r i c a t i o n process, the surface region of the wafer undergoes a large number of l i t h o g r a p h i c , etching, deposition and other physical and chemical processes. The complexity of a process for a given type of chip i s impressive. In the t r a i n i n g of process engineers, i t makes l i t t l e sense to study the whole manufacturing process for each type of product, since any manufact u r i n g process can be divided into a s e r i e s of steps or unit processes. The basic p r i n c i p l e s of each unit process are for the most part independent of the material or the c h a r a c t e r i s t i c s of the system i n which the process i s c a r r i e d out. In the understanding of an integrated c i r c u i t manufacturing process, each unit process used to manufacture the product can be studied i n d i v i d u a l l y . In chemical engineering processes, the unit processes are often c a l l e d "unit operations". T r a d i t i o n a l l y , i n chemical engineering, the r e s t r i c t i o n to the d e f i n i t i o n of unit operations i s that the changes induced i n the material are mainly physical (1). In the manufacture of integrated c i r c u i t s , many of the unit processes involve mainly chemical changes so perhaps the term unit processes i s more appropriate here. The important types of unit processes common to the manufacture of integrated c i r c u i t s are l i s t e d i n Table I. Not included are the unit processes used to manufacture masks, or the unit processes used to produce some of the materials necessary i n the manufacturing process, such as the important unit processes of f i l t r a t i o n of a i r and water p u r i f i c a t i o n . The unit processes l i s t e d may be subdivided. For example, i n the unit process, "implantation", either d i f f u s i o n and ion implantation can be used. Under the term, "dry etching", we can f i n d unit processes such as gas etching, plasma etching, and react i v e ion m i l l i n g . Further, some overlap of the categories l i s t e d i n Table 1 does e x i s t .


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Collector

Emitter

Base

Figure 1. Example of a bipolar npn t r a n s i s t o r . The figure shows a cross section of the s i l i c o n wafer. Symbols are: AL, aluminum; S i , s i l i c o n ; SiO^, s i l i c o n dioxide; and n and p, the doped regions of the s i l i c o n .


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Table I. 1.

Single Crystal Processess a) b) c) d) e)


3.

6.

wet etching dry etching

Assembly and Packaging a) b) c) d) e)

2.

S i l i c a purification c r y s t a l l i z a t i o n from melt melt doping zone r e f i n i n g s l i c i n g and polishing

Etching and Cleaning Processes a)

5.

Categories of Unit Processes

testing scribing dicing lead attachment encapsulation

Imaging Processes a) b) c) d)

4.

coating baking exposure development

Deposition and Growth Processes a) b) c) d) e) f) g) h)

oxidation epitaxy implantation evaporation sputtering lift-off plasma deposition chemical vapor deposition

Miscellaneous a)

Laser-annealing

I t i s i n s t r u c t i v e to consider an example of the manufacture of a t y p i c a l component such as the MOS (metal-oxidide-semiconductor) t r a n s i s t o r . Figure 2 gives a broad outline of how a p-channel MOS t r a n s i s t o r i s manufactured. S t a r t i n g with a smooth and clean wafer of n-type s i l i c o n , the surface i s f i r s t oxidized by exposing the wafer to oxygen gas and/or water vapor at high temperatures (~1200°C). Usually a layer of s i l i c o n dioxide approximately 1 ym t h i c k i s grown. Another process that can be used i s chemical vapor deposition i n which s i l i c o n dioxide i s deposited from a reactive vapor phase. This l a t t e r process can be operated at a considerably lower temperature than that required for thermal oxidat i o n and i s often preferred. S i l i c o n oxidation phenomena are well-understood [2,3) and reaction conditions can be e a s i l y designed to obtain the appropriate s i l i c o n dioxide thickness. After the oxide layer has been grown, a t h i n layer of photores i s t i s applied to the wafer's surface. The photoresist i s a r a d i a t i o n - s e n s i t i v e polymeric s o l u t i o n . It contains a complex mixture of photo-sensitive molecules and solvents. The layer of photoresist must be very t h i n , of the order of two microns, and spin coating i s a process that i s used to obtain a uniform layer


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I e

)

diffusion

n~Si

a)

I oxidation

n-Si


2

f)

d r i v e - i n and oxidation

n-Si

bi_j

i b) \ "T •

n-Si

coating and soft-bake NIT photoresist * ' ? , " VV!"j " : ? " " ""si'O

1

?

11 v

9)

* — J — 2

photolithographic steps and gate oxide growth 4-

n-Si

c)

err~

I

exposure development and hard-bake

n-Si

^ photoresist IIIIHUI

iifiiiiiiiii

«*: * » t t * : « : **. * ' . » v ' *SiO2 n-Si

d)

etch and clean

h)

photolithographic steps, m e t a l l i z a t i o n , and l i f t - o f f Negate drain

l£i_J

Al

u O n-Si

n-Si

Figure 2. Schematic diagram of the f a b r i c a t i o n of a p-channel MOS transistor.


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of photoresist on the surface. In t h i s coating process a cont r o l l e d volume of photoresist i s placed on the center of the wafer after which the wafer i s spun at high speed (3000-8000 rpm) i n order to spread and thin the l i q u i d photoresist uniformly on the wafer. The f l u i d mechanics of the spin coating process i s complex and i s not f u l l y understood because of several f a c t o r s : the speed of the r o t a t i n g wafer i s ramped; the photoresist s o l u t i o n may be non-Newtonian; evaporation of solvent takes place simultaneously with the momentum transfer process. A review a r t i c l e on the problem has been given ( £ ) and mathematical models have appeared i n the l i t e r a t u r e (5). After spin coating the wafer i s baked to remove excess solvent from the photoresist. The baking conditions are mild (~ 90°C) and the process i s , therefore, c a l l e d soft-baking. The drying of the photoresist improves i t s photosensitivity to r a d i a t i o n , and i n creases adherence to the thin f i l m l a y e r . Next, the photoresist i s s e l e c t i v e l y exposed using an image pattern transfer technique. For example, i n proximity p r i n t i n g , a mask i s placed very near to the photoresist and exposed with u l t r a v i o l e t l i g h t through the non-opaque areas. There are many other exposure techniques such as o p t i c a l p r o j e c t i o n , electron beam w r i t i n g , and x-ray exposure. After exposure, the development process depends on the type of photoresist (6). For negative photoresist, the exposed areas have undergone polymerization. Unexposed areas can be dissolved i n the developer s o l u t i o n . Although some components are s i m i l a r , p o s i t i v e r e s i s t s are d i f f e r e n t from negative r e s i s t s i n the chemistry of the r e s i s t and developer, and the r e s i s t response to exposure. For p o s i t i v e photoresist, the exposed areas become soluble i n the developer s o l u t i o n . After development, the pattern i s cleaned by a spray rinse and then the wafer i s hard-baked. The baking temperatures can be around 200°C causing the photoresist to harden and adhere firmly to the surface of the substrate. The l i t h o graphic steps of spin coating the photoresist, soft-baking, exposure, and development, are always necessary as the f i r s t step i n transferring the c i r c u i t pattern from the mask to the wafer. I n s u f f i c i e n t information on these processes i s available i n the open l i t e r a t u r e because the composition of photoresists are proprietary. Photoresist manufacturers usually supply guidelines to set processing conditions (2)- After development, the s i l i c o n dioxide that i s not covered by photoresist can now be etched away by either a wet etching or dry etching process. In wet etching, a reactive solution causes d i s s o l u t i o n of the unprotected s i l i c o n dioxide l a y e r . Wet etching involves a moving-boundary phenomenon, and i n recent years new mathematical models for t h i s type of problem have given a better i n s i g h t into the physics of the process (8). In dry etching a plasma gas reacts with the s i l i c o n dioxide and the products are vaporized at vacuum conditions. Dry etching with plasmas i s used extensively i n processing, but considerable research i s s t i l l i n progress to understand the detailed chemistry and process parameters ( £ ) .


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The etching process r e s u l t s i n removal of the s i l i c o n dioxide i n the selected areas defined, for example, by the clear or opaque areas i n the mask o u t l i n i n g the c i r c u i t pattern, so that the s i l i con i s exposed. After removal of the photoresist by a cleaning or s t r i p p i n g process, the exposed areas of the s i l i c o n can be doped with phosboron or other dopants to change the semicondutor from n-type to p-type i n the openings of s i l i c o n dioxide (for the example shown i n Figure 2 ) . High temperature d i f f u s i o n or ion-implantat i o n can be used as the unit processes to dope the surface areas. Diffusion of impurities into s o l i d s i s well-understood (10). Ion implantation i s rapidly becoming a mature unit process (11). The advantage of t h i s process i s that i t i s c a r r i e d out at considerably lower temperatures than the d i f f u s i o n process although some thermal annealing may be required. Further d r i v e - i n of the purity and oxidation of the s i l i c o n can be achieved by heating the wafer i n the presence of oxygen gas and/or water vapor. Additional photolithographic steps s i m i l a r to those discussed e a r l i e r are necessary to reopen the s i l i c o n dioxide covering source and drain areas above the p-type regions and to create a very t h i n s i l i c o n - d i o x i d e layer below the gate area. The next step involves deposition of a metal such as aluminum to form the contacts for the source, gate and d r a i n . F i n a l l y , an interconnect i o n pattern i s defined to connect the t r a n s i s t o r with other e l e c t r i c a l components on the surface. The t r a n s i s t o r s are now f i n i s h e d and the wafers proceed to other processing operations. Process Flow-Sheet The process described i n the previous section can be shown as a flow-sheet as depicted i n Figure 3. The figure shows the sequent i a l nature of each of the unit processes with the r e p e t i t i o n of the photolithographic or imaging steps involving coating, baking, exposure and development. Flow-sheets for other devices would be quite s i m i l a r to Figure 3 i n that s i m i l a r unit processes would be employed. The p a r t i c u l a r sequence of operations may d i f f e r . Further, i n any manufacturing process there i s usually a choice of several unit processes that can be used to produce a p a r t i c u l a r product. For example, etching can be c a r r i e d out by a wet etching or dry etching process. As far as deposition and growth processes are concerned, the unit processes i n epitaxy, plasma deposition and chemical vapor deposition are extensively used to deposit other layers such as s i l i c o n n i t r i d e and p o l y s i l i c o n . The process flow-sheet does not show the unit processes i n preparing the wafer, nor the f i n a l assembly and packaging processes. With higher and higher density chips, the assembly and packaging may prove to be a bottleneck. The choice of a part i c u l a r unit process depends on a variety of factors including experience i n using the process and economics.


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Oxidation

77K?

Manufacture of Integrated Circuits

Photoresist Coating

SoftBake

—>

Exposure

Develop

>

Metallizat i o n Si L i f t - off

Implantation

f

Hard Bake

Figure 3. Process flow-sheet for the MOS t r a n s i s t o r depicted in Figure 2. Direction of arrows allows for the r e p e t i t i o n of several lithographic processes.


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Fundamentals of Unit Processes An understanding of the fundamental physical and chemical processes occurring i n each unit process i s e s s e n t i a l i n order that process engineers can control the t o t a l process to insure high y i e l d s and consistent q u a l i t y of the product. In the unit processes, the basic fundamentals of transport phenomena, chemical r e a c t i o n , adsorption, phase t r a n s i t i o n , thermodynamics, e t c . must be understood i n order to be able to predict what w i l l happen to the product i f process conditions or materials are changed. For example, the soft-baking of negative photoresist i s a process of coupled mass and heat transfer occurring i n a s o l i d i n which excess solvent must be removed. As the solvent evaporates, the process may change from heat transfer control to mass transfer control due to changes i n the physical properties of the f i l m . Diffusion of solvent i n polymer films i s a complex phenomenon which i s not yet f u l l y understood. In f a c t , the fundamental chemical and physical phenomena i n many of the unit processes currently used i n the manufacture of integrated c i r c u i t s are s t i l l under intensive i n v e s t i g a t i o n by engineers, p h y s i c i s t , chemists and material s c i e n t i s t s . Besides an understanding of the basic fundamental phenomena occurring i n unit processes, the process engineer needs a s o l i d back-ground i n material science, s o l i d state physics and device physics. Process materials for device manufacture are becoming more exotic with the use of III-V and II-VI compound semiconduct o r s . S l i g h t changes i n process conditions can change the e l e c t r i c a l components' c h a r a c t e r i s t i c s d r a s t i c a l l y f o r such m a t e r i a l s . The consequence of a l l of t h i s i s that the engineer or s c i e n t i s t working i n the f a b r i c a t i o n of integrated c i r c u i t s w i l l e i t h e r have a m u l t i d i s c i p l i n a r y background or w i l l work i n an i n t e r d i s c i p l i n a r y group of p r o f e s s i o n a l s . Since some of the unit processes are not yet f u l l y exploited considerable research i s required to further increase our knowledge about the fundamental phenomena occurring i n such processes. Since the f a b r i c a t i o n of t h i n f i l m devices has become of i n t e r d i s c i p l i n a r y nature, the question arises on how research i n t h i s area can be most e f f e c t i v e l y communicated to and between professionals with d i f f e r e n t educational backgrounds? Are there unifying structures by which the knowledge on the fundamentals of unit processes can be transmitted to the d i f f e r e n t d i s c i p l i n e s i n the best possible way? Conclusion The f a b r i c a t i o n of integrated c i r c u i t s can be divided i n a s e r i e s of i n d i v i d u a l unit processes u t i l i z e d i n the manufacturing process. To control these unit processes the fundamental physical and chemical phenomena need to be f u l l y understood. The present technology f o r making integrated c i r c u i t s i s v e r s a t i l e , but much remains to be done to f u l l y e x p l o i t some of the unit processes and to develop new processes to produce cheaper and e l e c t r o n i c a l l y superior chips for future a p p l i c a t i o n s .


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Literature Cited


1.

Foust A.S.; Wenzel, L . A . ; Clump, C.W.; Maus, L.; Anderson, L.B. "Principles of Unit Operations", p.4, John Wiley and Sons, New York, 1960. 2. Colglaser, R.A. "Microelectronics: Processing and Device Design", John Wiley and Sons, New York, 1980. 3. Ghandi, S.K. "VLSI Fabrication Principles. Silicon and Gallium Arsenide", Wiley-Interscience, New York, 1983. 4. Washo, B.D. IBM J. Res. Develop., 1977, 21, 190. 5. Flack, W.W.; Soong, D.S.; Bell, A . T . ; Hess, D.W. J . Appl. Phys. 1984, 56, 1199. 6. DeForest, W.S., "Photoresist: Materials and Processes", McGraw-Hill Book Co., New York, 1975. 7. E l l i o t , D.J. "Integrated Circuit Fabrication Technology", McGraw-Hill Book Co., New York, 1982. 8. Kuiken, H.K. Proc. R. Soc. Lond., 1984, A392, 199. 9. Flamm, D . L . ; Donnelly, V.M.; Plasma Chem. and Plasma Process., 1981, 1, 317. 10. Grove, A.S.; Roder, A . ; Sah, C.T. J. Appl. Phys., 1965, 36, 802. 11. Stone, J.L.; Plunkett, J . C . In "Impurity Processes in Silicon", Wang, F.F.Y. Ed.; North-Holland Publ. Co.: Amsterdam, 1981; Ch.2. RECEIVED June 27, 1985


Unit Processes in the Manufacture of Integrated Circuits - American

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