Article pubs.acs.org/cm
Using Hydrogen To Expand the Inherent Substrate Selectivity Window During Tungsten Atomic Layer Deposition Berç Kalanyan, Paul C. Lemaire, Sarah E. Atanasov, Mariah J. Ritz, and Gregory N. Parsons* North Carolina State University, Department of Chemical and Biomolecular Engineering, Raleigh, North Carolina 27695, United States ABSTRACT: Area-selective thin film deposition is expected to be important in achieving sub-10 nm semiconductor devices, enabling feature patterning, alignment to underlying structures, and edge definition. Atomic layer deposition (ALD) offers advantages over common chemical vapor deposition methods, such as precise thickness control and excellent conformality. Furthermore, several ALD processes show inherent propensity for substrate-dependent nucleation. For example, tungsten ALD using SiH4 (or Si2H6) and WF6 is more energetically favorable on Si than on SiO2, but selectivity is often lost after several ALD cycles. We show that modifying the W ALD process chemistry can decrease the W nucleation rate on SiO2, thereby expanding the ALD “selectivity window”. Specifically, we find that adding H2 during the WF6 dose step helps passivate SiO2 against W nucleation without modifying W growth on silicon. Surface characterization confirms that H2 promotes fluorine passivation of SiO2, likely through surface reactions with HF produced in the gas phase. This passivation affords at least 10 additional W ALD cycles, corresponding to ∼6 nm of additional W growth, before substantial nucleation occurs on SiO2. We show that reactant modification also reduces undesirable nucleation due to substrate proximity or loading effects in patterned film growth. Further understanding of ALD reaction chemistry and film nucleation will lead to improved selective metal and dielectric film deposition, enabling ALD bottom-up patterning.
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INTRODUCTION Currently, integrated circuits utilize patterned lines and features that are 14 nm or less, and developers are working on designs at or less than 10 nm. Lithography at these dimensions is challenging because it requires extreme UV illumination or resolution enhancement techniques such as multipatterning, which involves two or more separate lithography and etching steps to create a single pattern layer.1,2 Moreover, critical challenges exist in areas such as overlay and edge placement error, that is, the difference between the designed and actual feature placement, which can significantly reduce functional device yield. Researchers are also exploring several nextgeneration lithography technologies, including nanoimprinting and directed self-assembly of block copolymers.1,3 These approaches offer new opportunities for nanoscale patterning but also create challenges in feature alignment and registry. Thin film deposition by chemical vapor deposition (CVD) or atomic layer deposition (ALD) are enabling processes for semiconductor device manufacturing, in which reactions lead to a uniform “blanket” coating that is then patterned by lithography. The ALD processes use sequential self-limiting surface reactions to form conformal and uniform films on receptive substrates,4 and for several materials, the process is sufficiently robust, reliable, and scalable to meet the highvolume manufacturing demands of advanced logic and memory devices. Using the precision afforded by ALD reaction chemistry, researchers are exploring ways to control ALD nucleation reactions as a means to chemically guide pattern formation. The overall goal of ALD-enabled nanopatterning is © XXXX American Chemical Society
to use innate chemical differences across a surface to grow nanoscale features by selective-area deposition, where material is only deposited in predetermined regions. Although selective-area thin film CVD5−19 and ALD20−27 are widely studied, extended process time or cycle numbers generally lead to nucleation on all surfaces. Recent work on selective CVD of cobalt has been implemented for copper encapsulation in electronic interconnects,19 where up to 7 nm of Co can be deposited on Cu without appreciable deposition on the neighboring dielectric. Many high-temperature (>600 °C) substrate-selective epitaxial growth processes are known,28−30 but semiconductor device fabrication is often limited to
