Vertical Charge Transfer and Lateral Transport in Graphene

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Vertical charge transfer and lateral transport in graphene/germanium heterostructures Alireza Kazemi, Sam Vaziri, Jorge Daniel Aguirre Morales, Sebastien Fregonese, Francesca Cavallo, Marziyeh Zamiri, Noel Mayur Dawson, Kateryna Artyushkova, Ying Bing Jiang, Steven R. J. Brueck, and Sanjay Krishna ACS Appl. Mater. Interfaces, Just Accepted Manuscript • Publication Date (Web): 20 Apr 2017 Downloaded from http://pubs.acs.org on April 21, 2017

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ACS Applied Materials & Interfaces

Vertical charge transfer and lateral transport in graphene/germanium heterostructures Alireza Kazemi1, 4, Sam Vaziri 2, Jorge Daniel Aguirre Morales3, Sébastien Frégonèse3, Francesca Cavallo4, Marziyeh Zamiri5, Noel Dawson4, Kateryna Artyushkova,6, Ying Bing Jiang7, Steven J. R Brueck4, and Sanjay Krishna 1,4 * 1

Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH,

United States. 2Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA. 3Université Bordeaux 1, CNRS, UMR 5218, 33405 Talence, France. 4Center for High Technology Materials, University of New Mexico, Albuquerque, NM, United States. University of Wisconsin-Madison, Madison, WS, United States. 6Department of Chemical and Nuclear Engineering, University of New Mexico Albuquerque, NM, United States. 7Center for MicroEngineered Materials, University of New Mexico, Albuquerque, NM, United States. KEYWORDS. Graphene, germanium, lateral transport, charge transfer, mixed-dimensional van der Waals heterostructures.

ABSTRACT. Heterostructures consisting of two-dimensional (2D) materials and conventional semiconductors have attracted a lot of attention due to their application in novel device concepts. In this work, we investigated the lateral transport characteristics of graphene/germanium heterostructures and compared it with the transport properties of graphene on SiO2. The

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heterostructures were fabricated by transferring a single layer graphene (Gr) onto lightly doped germanium (Ge) (100) substrate. The field effect measurements revealed a shift in the Dirac voltage of Gr on Ge substrates compared to the Gr on SiO2. Transfer length model (TLM) measurements show a significant difference in the sheet resistance of Gr on Ge comparing to the Gr on SiO2. The results from electrical and structural characterizations suggest that a charge transfer in the order of 1012 cm-2 occurs between Gr and Ge resulting in a doping effect in the graphene sheet. A compact electrostatic model extracted the key electronic properties of the Gr/Ge interface. This study provides valuable insights on the electronic properties of Gr on Ge, which are vital to develop novel devices based on the mixed two- and three-dimensional structures.

INTRODUCTION Recently, heterostructures based on a combination of 2D and conventional materials, known as mixed-dimensional van der Waals (vdW) heterostructures1, have attracted a lot of attention due to their promising electronic and photonic properties2-5. For instance, graphene (Gr) as a 2Dmaterial can be integrated with conventional semiconductors such as Silicon6-8, germanium (Ge)5, 9-17

and other semiconductors such as Gallium Nitride18-22, Silicon Carbide23-24 and Zinc Oxide25

to form 2D/3D heterostructures. The well-established semiconductor technology and the remarkable electronic transport properties of Gr make these hybrid materials potential candidates for developing next-generation optoelectronic devices. These heterostructures have recently been investigated for high-speed photodetection5, 26, light emitting devices 27-28 and photovoltaics 2, 29. Interestingly, Ge as a substrate has recently shown tremendous potential in Gr synthesis10-11, 13, 15, 30-31

, and Gr/Ge heterostructure has proven useful for analog electronics17 and infrared (IR)

detection5.


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Despite the increasing body of literature on Gr/Ge, its physical and electronic properties are poorly characterized, and lateral transport in this material system is not well-understood. To date, Cavallo et al.17 have provided the only reported values of mobility and carrier concentration of Gr supported by a Ge substrate. As shown in Ref. 17, four probes and Hall measurements require complicated modeling to extract mobility and carrier concentration. Characterization of the topgated field-effect transistors (FETs) is an alternative route to investigate lateral transport in Gr/Ge. The fundamental challenge in this configuration is to minimize the effect of the gate dielectric on transport in the 2D material. We eliminated the effect of gate dielectric/Gr interface by using a back-gated FET configuration based on Gr/Ge/SiO2. Our study includes fabrication of Gr/Ge heterostructure, and systematic analysis of its interface properties by means of atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and electron energy-loss spectroscopy (EELS). In addition, Gr/Ge-FETs and transfer length model (TLM) structures were fabricated to study the electronic properties of the interface. We also developed a theoretical model to extract the carrier mobilities and concentrations from the electrical data. RESULTS AND DISCUSSION In order to form a Gr/Ge heterojunction and fabricate the field effect and TLM test structures, we released and transferred a 100 nm thin Ge film from a germanium on insulator (GOI) wafer to a 285 nm SiO2/p+Si substrate as illustrated in Figure 1 (see Methods). The Ge transfer step was needed as the thick 420 nm SiO2 layer and the lightly doped underlying Si substrate in the GOI are unsuitable for the field effect characterization. The Ge Nanomembrane (NM) was released through selective etching of the SiO2 layer in the GOI wafer and then transferred to the new substrate in DI Water (Figure 2 (b, c)). After defining Ge mesas, we performed PMMA-assisted transfer 32 of


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single layer Gr to the Ge/SiO2/p+Si and SiO2/p+Si (Figure 1d). Following the Gr transfer, we removed PMMA through a solvent soak and vacuum annealing. The Gr/Ge/SiO2/p+Si sample was then processed into back-gated FETs by depositing source and drain electrodes through standard lithography followed by electron beam evaporation and lift off (Figure 1e). The highly doped Si substrate and the 285 nm thermally grown SiO2 layers serve as the gate electrode and dielectric, respectively. Three types of field effect devices were investigated in this work namely Gr/SiO2/p+Si (or Gr-FET), Gr/Ge/SiO2/p+Si (or Gr/Ge-FET) and Ge/SiO2/p+Si (or Ge-FET). Prior to the Gr transfer, we inspected the surface roughness of Ge/SiO2/p+Si via AFM and compared that to the surface roughness of SiO2/p+Si wafer (see Methods). The optical micrograph and close-up image of the Ge NM are shown in Figures 2 (a, b). Figures 2 (c-d) are AFM images of the SiO2/p+Si and Ge/SiO2/p+Si substrates, respectively. Figures S1(a-d) presents the corresponding height profiles and histograms evaluated from a statistical analysis of the AFM images. The AFM analysis shows relatively smooth surfaces for the SiO2 wafer with root mean squared (RMS) roughness of 0.19 nm (Figures 2c). However, the AFM profile for the Ge NM surface showed random wrinkle features presumably generated during the release and transfer process, as shown in Figure 2d. The RMS roughness for the Ge NM was found to be 0.64 nm suggesting that film has undergone considerable morphological changes during the transfer step. We will address the potential effects of surface roughness on the transport properties of Gr/Ge devices after describing our theoretical model. The presence and quality of the transferred Gr was confirmed using Raman spectroscopy (see Methods). The Raman spectrum acquired from Gr on SiO2 (Fig. 3a, black line) shows a G band centered at 1583 cm−1 and a symmetric 2D band at 2686 cm−1, consistent with the previous reports33-34. For the Gr/Ge sample (Fig. 3a, red line), the G band was found to be red-shifted to


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1578 cm−1 and the 2D band was blue-shifted to about 2693 cm−1 (see Supporting Information). The full width at half maximum (FWHM) of 2D peak for the Gr/SiO2 and Gr/Ge samples were found to be 38.3 cm−1 and 37.1 cm−1, respectively, which are lower than 40 cm−1 and ensures that the Gr films are monolayer34. Additionally, the intensity ratio of 𝐼2D/𝐼G which is sensitive to doping35 were found to be 1.41 and 1.06 for the Gr/SiO2 and Gr/Ge samples, respectively. One should note that the characteristic peaks of Ge substrate lie at wavenumbers shorter than 600 cm-1 and thus not interfering with the Gr peaks. For both samples, a low-intensity D band was observed at 1346 cm−1. The intensity of the Gr/Ge bands were found to be lower than Gr/SiO2 bands potentially due to higher spectral background from the Ge film36. It has been suggested that the charge doping or rippling on Gr cause the inhomogeneous charge distribution 37-38, which in turn, lead to variations of Raman features. To study the interface properties of Gr/Ge, we analyzed the channel of Gr/Ge-FETs with X-ray photoelectron spectroscopy (XPS) (see Methods). Figure 3b shows the C 1s core-level XPS spectra, which reveals a strong Gr band centered at ~284 eV. The chemical states identified as non-graphitic C in Figure. 3b are attributed to functional groups of the PMMA molecules39, and suggest that some of the polymer residue is still present on the Gr film. Figure 3c shows the same spectra in the Ge 2p regions which features an elemental-Ge peak centered at ∼1218 eV, and two additional modes centered at ~1219 eV and ~1221 eV, which correspond to germanium dioxide (GeO2) and germanium suboxide (GeOx), respectively. The identified oxides have natively formed on the Ge surface when they were exposed to ambient after the Ge transfer step. Finally, TEM was utilized to further investigate the Gr/Ge interface and to estimate the thickness of the GeOx/GeO2 layers (see Methods). A cross-sectional TEM image of the Gr/Ge-FET is shown in Figure 3e. To better identify the existing layers, we acquired the oxygen and carbon maps of the


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stack via electron energy loss spectroscopy (see Methods). The EELS analysis revealed that a Ge oxide interface is formed between the single layer Gr and the Ge NM (Figure 3f). The presence of Gr was also verified as illustrated in Figures 3d. A high resolution (HR) TEM profile of the sample is shown in Figure 3g, where the crystalline Ge layer can be identified. One should note the single layer graphene does not provide enough phase contrast to be observed in the high resolution image. The GeO2/GeOx film is estimated to be ~8 nm thick from Fig. 3g. We characterize the electronic properties of the heterostructure by testing the fabricated Gr and Gr/Ge-FETs. Figure 4a shows an optical micrograph of the processed devices. It is worth noting that our fabrication scheme enables a comparison between the field effect transport characteristics of Ge, Gr/Ge and Gr on the same SiO2/p+Si substrate (see Figures. 1e and 4a). Figure 4b compares typical characteristics of the three field effect devices at the constant Vds of 1 V. The Gr-FET (black dots in Figure 4b) exhibits a p-type characteristic with a typical on-current of 22 µA/µm and the VDirac located at Vg=63±8 V. It has experimentally shown that degassed (or pristine) Gr on SiO2 behave as an n-type system40, but p-type behavior has been observed with chemical charge transfer from gaseous dopants in air41 and also polymer residues left on the transferred Gr film4244

. Since our electrical measurements were performed in vacuum condition (10-6 Torr), the p-type

doping of Gr on SiO2 is considered to be attributed to the residual polymers on the Gr sheet. The Ge-FET showed a p-channel characteristic with the cut-off mode at Vg=25±4 V and the on-current of 2.3 µA/µm (blue dots in Figure 4b). The reverse field effect conductivity on Ge substrates (i.e., n-type field effect on p-type Ge and vice versa) has already been reported and is ascribed to the surface potential effect across the Ge surface45. The Gr/Ge device, delivered a current of 8 µA/µm and the VDirac shifted to 3±4 V (red dots in Figure 4b). We also found that the conduction asymmetry for the Gr/Ge channel is less pronounced when compared to the Gr/SiO2 channel where


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the hole conduction is more suppressed. This may be the result of more balanced carrier injection from the Gr/Ge under the metal contacts46. The transfer characteristics of the representative Gr, Gr/Ge, and Ge devices at different Vds and Vg steps are shown in the Figure S3. To facilitate the field effect analysis, the on- and off-state current values as well as the corresponding on/off current ratios were extracted for a series of tested devices (Figures 4 (c-e)). As it is shown in Figure 4c, the devices with the Gr channel exhibit higher on-state current when compared to the Ge channels which may originate from the higher conductivity of Gr with respect to the Ge NMs. Furthermore, the higher on-state level in the Gr-FETs with respect to the Gr/GeFETs can be attributed to the difference in the Gr doping and effective electrostatic gate control. Despite the low on-state current in the Ge-FETs, the corresponding on/off current ratio is more than 400 times greater than those for Gr/Ge-FETs (Fig. 4d). The higher on/off current ratio may suggest that unlike the Gr channels with the zero band gap, the Ge channel can be effectively switched-off at higher positive gate voltages. Therefore, a comparison between the on- and offstate current levels, as well as the on/off current ratio, implies that in the Gr/Ge devices the source to drain current, predominantly, flows in the Gr channel. Dirac voltage (VDirac) is another key parameter that can reveal the changes in the carrier concentration of the channel. The shift of VDirac corresponds to the shift of the Fermi level with respect to the Dirac point in the energy-momentum band diagram of Gr47. Figure 4f compares the extracted values of VDirac for the studied devices. The narrow distribution of Dirac voltages in the measured devices reflects excellent reproducibility across different devices. The VDirac in the reference Gr/SiO2 sample is at 63 V. Interestingly, compared to the reference Gr device, the Dirac voltage of the Gr/Ge device shifted to 3±4 V suggesting a change in the doping level in the Gr on Ge NM film. Since both Gr and Gr/Ge-FETs were subjected to the same processing steps and


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characterized in the same condition, this doping effect mainly originates from the different structure and electronic properties of the Gr/Ge and Gr/SiO2 interface. To obtain further insight into the charge transport of the Gr/Ge interface, the sheet resistance of the Gr on Ge NM extracted by means of transfer length model (TLM) measurement and compared to the one for Gr on SiO2 (see Methods and Figures S4 and S5). Figure 5a shows the total resistances extracted from the TLM measurements as a function of length along with the extracted sheet resistances under zero gate bias. The sheet resistance for the Gr on SiO2 is ∼1180 Ω/sq which compares favourably with other studies48. Interestingly, we extracted a relatively large sheet resistance of ∼3100 Ω/sq for Gr on the Ge NM. The extracted sheet resistance (Rs), contact resistance (Rc), contact resistivity (ρc), and transfer length (LT) for the studied samplesare listed in Table 1. The contact resistance of Gr/Ge was found to be larger than the one for the Gr/SiO2 sample. Interestingly, both contact resistivity values are comparable/lower with respect to the previous reports49. Moreover, the transfer length (TL) of the Gr on Ge under floating gate voltage was, approximately, the same as that for the Gr on SiO2 and compares favourably with the previously reported results50. The higher sheet resistance of the Gr on Ge is in-line with the findings from the field effect measurements. As shown in Figure 5b, at Vg=0 V and Vds =1 V, the Gr/Ge-FETs delivered a smaller current comparing to the Gr-FETs. This is a result of Dirac voltage shift towards 0 V which corresponds to the upward Fermi level shift to the vicinity of the Dirac point. This upward shift of the Fermi level translates to the introduction of excess electrons to the Gr channel on Ge. In the following, we discuss the mechanism of this charge introduction which is interface charge doping from the Ge NM. Previous studies show that the Fermi level shift in Gr is induced by electrostatic doping51 and interface charge doping52-55. In order to confirm the interface charge doping, one should realize


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the characteristics of the Ge substrate and Gr/Ge interface. Both XPS and EELS analysis established the presence of Ge oxide at the interface of Gr/Ge. Several studies suggest that the Ge oxide contains surface states residing within the Ge energy gap 56-58. The surface states (in the form of donor-like and acceptor-like trap states)59-61 are believed to facilitate charge interchange between the semiconductor space-charge region and the states lying in the oxide layer17, 57. Based on this argument and the obtained results, we posit that the Ge oxide layer plays a critical role in the lateral charge transport of Gr on the Ge substrate. The key charge transfer process in the Gr/GeFETs is, schematically, illustrated by qualitative band diagrams in Figure 6. The energy band diagrams of Gr-FETs are shown in three modes of operation in Figures 6 (a-c). Under the assumption that the Gr/SiO2 is p-doped in equilibrium (which is verified by the field effect measurements), the Fermi levels in p+Si and Gr are lined up as shown in Figure 6a. The p-type conductance of the device is strongly increased under negative Vg (Figure 6b). However, in positive Vg, n-doping is electrostatically induced in the channel (Figure 6c). For the Gr/Ge-FET, in a thermal equilibrium condition after the Gr/Ge contact has occurred, electrons can be efficiently injected from the Ge to Gr through the donor-like states residing on the Ge surface, leaving a positive surface charge behind. At the same time, electrons residing in the bulk of Ge occupy the acceptor-like states at the Ge surface which results in band-bending in Ge as the Fermi levels of Gr and Ge line up across the interface. The Fermi level of Gr rises from the Dirac point towards that of the Ge. Therefore, in equilibrium, it is expected that the Fermi level in the Gr on Ge will be at a higher level (but still below the Dirac point) compared with Gr/SiO2 which is confirmed by the experimental results shown in Figure 4b. On the contrary, when a negative Vg is applied to the Gr/Ge-FET (Figure 6e), the induced electric field in the Ge layer gives rise to an electron accumulation at the Ge/Ge oxide interface (leading to a negative slope in the Ge energy bands)


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which further facilitate the charge transfer into the Gr layer. This electric field direction changes under positive Vg which leads to a positive slope in the Ge energy bands which potentially inverses the direction of the electron transfer. Overall, since the Gr film has received electrons from Ge in equilibrium, the Fermi level is still expected to be at a higher level compared with Gr/SiO 2 as is illustrated in Figure 6f. A similar gate-assisted charge injection has been demonstrated between Gr and bulk MoS2, where the band offset (the energy separation between the Gr charge neutrality point and the MoS2 conduction band edge) has been compensated by increasing the Gr chemical potential, and the electrostatic band bending of the MoS2 conduction band

62

. In the Gr/Ge

heterostructure, the charge transfer between Gr and Ge is believed to be facilitated by the trap states in the intermediate Ge oxide layer. It must be noted that the interface states are expected to also affect vertical current transport across Gr/Ge interface (i.e., the Schottky barrier and ideality factor). A systematic studying of Gr/Ge Schottky junction could provide a foresight on the effects of trap states on the vertical current transport across the Gr/Ge heterostructure. In order to extract the key electronic parameters of the back-gated Gr/Ge-FETs, an electrostatic description is necessary to compute the charge in the Gr layer. Combining the density of states of Gr with the Fermi approach for the carrier distribution63, the charge density in a metal-insulatorgraphene (MIG) capacitor can be approximated as  e2  QSH  x   e    v f 



2

 VCH  x  VCH  x   N F   

(Eq. 1)

with ћ the reduced Planck constant, vf the Fermi velocity, e the electronic charge, and VCH(x) the channel potential along channel length and NF is the doping. For metal-insulator-germaniumgraphene (MIGeG) structure, the charge evaluation requires a specific approach with an equivalent


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circuit shown in Figure 7a. V(x) describes the channel potential variation due to the source-drain voltage. The charge in the Ge layer can be described as QGE=CGEVGE+ ΔQinv, where CGE is the capacitance of the Ge insulating layer, VGE is the voltage drop across the Ge layer and ΔQinv is the additive charge due to the inversion layer of the metal oxide semiconductor stack. In this model, we assume that the Ge film is not biased by the source and drain contacts which was validated by the field effect measurements. The potential variation in the Gr/Ge channel can be derived by applying the Kirchhoff ’s law to the equivalent circuit in Figure 7a (see supporting information). By introducing the channel potential (Eq. S2) within the charge density (Eq. 1) and using the driftdiffusion equation, the source-drain current in the back gated Gr/Ge-FET will be given by (Eq. 2)

VDSi

I D  µW



QSH dV

0

Lµ

VDSi

 0

1 dV vsat

where µ is the mobility, W is the width of the graphene sheet, L is the channel length, and νSAT is the saturation velocity in the Gr layer. Sentaurus TCAD simulator64 was used to extract the carrier density in the Ge inversion layer which is later used to calculate the channel potential. The experimental IV characteristics of the Ge-FET fitted with the model curves (Figure S6) used to extract the carrier densities in the Ge inversion layer as a function of gate voltage (Figure S7). As expected, a linear approximation of the charge is sufficient to evaluate the charge in the Ge layer. Based on the calculation, the inversion layer capacitance is found to be Cinv=135 µF/m2. Using the derived equation for the channel potential (Eq. S2) and using the extracted Cinv, the channel potential variations were calculated for Gr- and Gr/Ge-FETs (Figure 7b). We found that the channel modulation in Gr- and Gr/Ge-FETs are in the


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same order of magnitude despite the presences of the Ge layer which is the result of a comparable equivalent-oxide-thickness (EOT=285 nm for MIG and EOT=309 nm for the MIGeG structure). Considering the inversion layer, only a small decrease in the channel potential modulation was observed. By fitting the experimental transfer characteristics (Figure 7 (c, d)) and considering the contact access resistance extracted from TLM structures, we extracted the carrier mobilities. For the Gr-FET, the electron and hole mobilities were found to be 297 cm2V−1S−1 and 803 cm2V−1S−1, respectively. For the Gr/Ge-FET, the mobilities were evaluated with and without considering the charge in the inversion layer. Assuming an inversion layer is formed in the Ge NM, the electron and hole mobilities were found to be 240 cm2V−1S−1 and 340 cm2V−1S−1, respectively. We attribute the low carrier mobility estimated in the Gr/Ge devices to carrier scattering resulting from high Ge surface roughness, wrinkling of the transferred Ge, and charge impurities at the Gr/Ge interface. Finally, using the extracted EOTs and the Dirac voltage shift, the difference in the charge carrier density between the Gr/SiO2 and Gr/Ge samples were calculated (see supporting information). Considering the structural difference of the samples and the same measurement condition, the calculated charge carrier densities suggest a charge transfer in the order of 1012 cm-2 at the Gr/Ge junction. While our simple electrostatic modeling was developed to extract the key electronic properties of the Gr/Ge device by fitting the experimental data, a theoretical calculation based on molecular dynamics and density functional theory will be useful to study the band arrangement of the heterostructure, trap state density as well as charge density below the conduction band edge in Ge. CONCLUSION In summary, we investigated the charge transport in a graphene-germanium heterostructures. Based on detailed analysis, the Dirac voltage shift and larger sheet resistance in the Gr/Ge


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heterojunction are attributed to a vertical charge transfer from the Ge membranes to the single layer graphene. Our observations of G band frequency down shift in the Raman study also support the surface charge doping of the Gr on Ge substrate and are in-line with the reported result65. The former effect is evidenced by identifying the GeOx/GeO2 film between the Gr and Ge which has already been shown to have charge transfer characteristics. Our insights enable a better understanding of transport through Gr semiconductor heterojunction. The integration of Gr with Ge can also open up possibilities for light-sensing, light-harvesting and analog electronics. For instance, the rectifying behavior in the Gr/Ge Schottky junction can be utilized for photodetectors with a wide range of spectral response. Conventional Gr phototransistors have relatively poor responsivity owing to weak optical absorption of the single layer material66. However, Gr/Ge heterojunction photodiodes can overcome this limitation by having a greater optical absorption at the junction. Such photodetectors can also be inherently faster as the excited photocarriers can be accelerated out of the junction depletion region by the built-in electric field, resulting in highfrequency operation under zero bias. Additionally, the Gr/Ge Schottky junction can be useful for solar cells applications. Strategies such as Ge passivation, antireflective coatings and chemical doping of Gr can be implemented to maximize the work function difference and carrier collection efficiencies. Ge micropillar arrays can be integrated with Gr to increase the Gr/Ge contact area and consequently improve the carrier collection. The ability to effectively control the carrier concentration in the Gr film with a semiconducting substrate creates a system in which the conductivity can be very high, through both a high mobility and a high carrier concentration which can be useful for analog electronics, enabling fast transistors with high gains. MATERIALS AND METHODS Device Fabrication: (Field Effect Transistors): The Gr/Ge-FETs were fabricated using standard photolithography. A positive tone photoresist (AZ 4330) was spin coated on a 1×1 cm2 germanium on insulator (GOI) wafer followed by standard photolithography to create hole arrays in the PR film with 5 µm hole size and 100 µm pitch. Next, an anisotropic ICP dry etching


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(BCL3 flow 30 sccm; RF1 power, 90 W; pressure, 2.5 mTorr) was performed for 15 min to create etchant access holes in the Ge and SiO2 layers through the patterned PR layer. Next, the SiO2 in the GOI wafer was wet etched (hydrofluoric acid (HF): H2O 1:2) on a shaker with speed 120 rpm for 4 h to releases the top Ge film as a nanomembrane (NM). The released Ge NM (nominal thickness of 100 nm and area of 50 mm2) is then transferred in water onto a new 100 mm2. SiO2/p+Si substrate. The transferred NM is annealed at 90 °C for 10 min to evaporate any water. The post-bake also speeds up the Ge oxide grow which leads to a strong bond at the interface between the Ge and SiO2. The Ge NM was subsequently defined into Ge mesas with an area of 0.03 mm2 through another photolithography step. PMMA-assisted technique was used to transfer a single layer graphene from polycrystalline copper (Cu) film to the new substrate. First, graphene at the bottom side for the Cu foil is removed by oxygen (O2) plasma etching. Next, a PMMA film (950 PMMA A4) was spin coated on the top side of Gr/Cu at 3000 rpm for 30 sec. The Cu film is then etched away by a 22 h soak in a solution (hydrochloric acid (HCl) 100 mL, DI water 10 mL, and Iron (III) Chloride 3 mg). Once the Cu is removed, PMMA/Gr is transferred onto the transferred Ge/SiO 2/p+Si following a series of cleaning with DI water. The host substrates were pretreated as the following: 5 min soak in acetone, 5 min soak in IPA, followed by 10 min soak in sonicated DI water at 95° C. A post-bake at 100 C for 2 min is performed to enhance the adhesion between Transferred Ge/SiO2/p+Si and graphene. The Gr/SiO2/P+Si is then left in acetone for 30 min to remove the PPMA film followed by vacuum annealing at 400 C in argon flow for 1 h to remove the PMMA residue. To make a better back-gate contact, after removing the native oxide on the silicon substrate by dipping in buffer oxide etch (BOE) solution (6:1 volume ratio of 40% NH 4F in water to 49% HF in water) while covering the sample surface with PR, a 100 nm-thick Au film was sputtered onto the p+Si substrate. The source and drain electrodes were subsequently made using another photolithography step followed by electron-beam evaporation of Ti/Au (5 nm/95 nm). Next, graphene channels were defined with photolithography (AZ 5206 dilution of 1:2 with AZ thinner) and O 2 plasma etching. The channel length (L) and Width (W) of the transistors are 60 µm. The resistivity of the p+Si substrate used for sample is < 0.001 Ω·cm. The resistivity of the Ge NM is < 0.4 Ω·cm. The FET was undergone rapid thermal annealing (RTA) at 250° C in forming gas flow for 2 min. It is worth noting that the lithography step carried out to isolate devices and define graphene channels is the main cause of residual photoresist in graphene. We used a so called ‘pipette blasting’ technique to remove the hardened PR (AZ 5206) after etching the graphene film by O2 plasma. The samples were placed in AZ KWIK Strip Remover heated to 95° C and a pipette already filled with the solvent used to flush several times to remove the PR residues. This technique was proved to be very efficient in removing the hardened PR while leaving the graphene in the channel intact. (Transfer Line Model samples): The TLM structures were made on Gr/SiO2/p+Si, and Gr/Ge/SiO2/p+Si using standard photolithography and metal deposition (figure S4). In short, after opening the windows in the photoresist layer (AZ 5214-IR), 9 nm/95 nm of Ti/Au was evaporated by electron beam deposition and patterned by lift-off process. For TLM samples with Gr/Ge channels, before the graphene transfer and metallization, the Ge films were processed into 6 µm × 100 µm strips and after the graphene transfer, the graphene channel was confined to the area of the Ge membrane. A second lithography step and oxygen plasma etching were used to pattern the graphene channel. The sacrificial photoresist mask (AZ 5206 E, diluted 1:2 with DI Water) used to protect the graphene channel region during the etch process was removed by soak the samples in AZ KWIK Strip Remover heated to 95 °C by means of pipette blasting technique already explained. In order to improve the graphene-metal contact, all samples were annealed for 2 min in a rapid thermal annealer with forming gas (5% H2 in N2) flow. The graphene channel width was 6 µm and the channel lengths (transfer lengths) varied between 3 and 24 µm. Device characterization: (Electrical Characterizations): The electronic properties of Gr/Ge field effect devices and TLM structures were characterized by a JANIS ST-500 micro-manipulated probe station under vacuum (10−5 Torr) to eliminate/reduce the hole doping effects due to absorption of oxygen and water molecules at the graphene surface. The probe station was equipped with a Scientific Instruments M9700 temperature controller, and the measurements were carried out with a Keithley 2400 source measure unit (SMU) and Keithley 238 high-current SMU. Channels with graphene coverage were identified by the resistance reading. The electrical characterizations for graphene transferred to Ge membranes were performed within 48 h after the transfer to ensure the GeOx growth. (Transfer Line Model Analysis): Transfer line model (TLM) is used here to extract the sheet resistance of graphene on different substrate along with the contact resistance. By calculating the total resistance of graphene channel as 𝑅𝑇 = 𝑅𝑠 (𝐿⁄𝑊) × 𝐿 + 2𝑅𝑐 where 𝑅𝑠 the sheet resistance of graphene is, L and W are the TLM channel length and width, respectively, and 𝑅𝑐 is the contact resistance. By linearly fitting 𝑅𝑇 of samples with different channel lengths, 2𝑅𝑐 and 𝑅𝑠 ⁄𝑊 can be measured from the intercept and slope simultaneously. Since 𝑅𝑐 clearly depends on the pad size, the specific contact resistance ρc = Rc·W normalized to the contact width was also evaluated. (Transmission Electron Microscopy): Cross-sectional TEM samples were prepared in a FEI Q3D ESEM/FIB dual-beam system with Ga as the ion source. TEM characterization was carried out in a JEOL 2010F high resolution TEM/Scanning-TEM with field emission e-beam accelerated at 200kV. Elemental mapping was acquired in TEM mode with Gatan Image Filter (GIF). (Atomic Force Microscopy) The AFM measurement was performed on an Asylum MFP-3D system in tapping mode. NSC15 cantilevers with a tip radius of 8nm and a spring constant of around 40N/m were purchased from Mikromasch. (FIB and TEM): Vertical slices of Gr/Ge-FET were cut out using focused ion beam (FIB), and ware placed on a TEM grid to be investigated for the stacking interface quality. The Ge film is about 100 nm thick. (Raman Spectroscopy): The Raman experiment was carried out in room temperature by focusing a 532 nm excitation light (output of laser diode) through a dry objective with numerical aperture 0.95. The scattered light was collected using the same objective and is directed to a CCD spectrometer (Princeton instruments, IsoPlane). (X-Ray Photoelectron Spectroscopy): XPS measurements were performed using a Kratos Axis Ultra DLD X-ray photoelectron spectrometer using a monochromatic Al Kα source operating at 225W. Samples were analysed at normal take-off angle. Survey and high resolution Ge 2p, C1s, O1s, Si 2p and Ge 3d spectra were acquired at 80 and 20 eV pass energy, respectively. No charge compensation was necessary . The data obtained are average of 3 different areas per sample. Data analysis and quantification were performed using the CasaXPS software. A Shirley background


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was used for Ge 2p, Si 2p and Ge 3d spectra, while linear background was used for the other photoelectron lines. Quantification utilized sensitivity factors that were provided by the manufacturer. A 70% Gaussian / 30% Lorentzian (GL (30)) line shape was used for the curve-fits of all spectra. Carbon was fitted using asymmetric Gaussian/Lorentzian shape for graphitic peak and symmetrical GL for the other peaks.


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FIGURES:

Figure 1 Schematic representation of the Ge transfer from germanium on insulator (GOI) to SiO2/p+Si. (a) A germanium on insulator (GOI) substrate is used for the processing (b) First, the GOI is covered with a patterned photoresist (PR) followed by an anisotropic dry etching of the Ge and SiO2 through the patterned PR layer. Next, the SiO2 is etched to releases the top Ge film. (c) The released Ge is then transferred in water onto a new SiO2/p+Si substrate. (d) The Ge film is subsequently defined into Ge mesas and a single layer graphene is transferred to Ge/SiO2/p+Si and SiO2/p+Si. (e) The graphene film is then confined to the Ge mesas through another lithography step, and source, drain and gate contacts are deposited through another photolithography steps.


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Figure 2 (a) Optical micrograph of the transferred Ge (or Ge nanomembrane (NM)) on 285 nm SiO2/p+Si. (b) Close-view image of the Ge NM. (c-d) AFM images and the corresponding RMS roughness values evaluated from statistical analysis of the AFM images for SiO2/p+Si and Ge NM on SiO2/p+Si substrate before the Gr transfer.


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Figure 3 (a) Raman spectra of Gr/SiO2 and Gr/Ge (b, c) X-Ray photoelectron spectroscopy (XPS) spectra in the C 1s and Ge 2p regions acquired from the Gr/Ge-FET channel. (e) Cross-sectional TEM image of the Gr/Ge interface. (d-f) The carbon and oxygen EELS maps acquired from the TEM image (g) High resolution cross-sectional TEM image of the Gr/Ge interface.


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Figure 4 (a) Top-view optical micrograph of the fabricated FETs. (b) Linear scale source-drain current (Id) versus gate voltage (Vg) recorded at constant source-drain voltages (Vds = 1V) obtained in vacuum (10−6 Torr) and room temperature. (c-f). The key transport parameters of the Gr-, Gr/Ge, and Ge-FETs extracted from a series of tested devices.


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Figure 5 (a) Total resistance extracted from the TLM measurements as a function of TLM length for Gr on SiO2 and Ge under Vds=1 V and Vg=0. The extracted sheet resistances are also shown. The inset shows optical micrographs of the TLM structures on Gr/SiO2 and Gr/Ge strip. (b) The distribution of Id at Vds=1 V and Vg=0 for a series of tested Gr/SiO2 (or Gr-FET) and Gr/transferred Ge (or Gr/Ge-FET) devices.

Table 1. Measured values of Rs, Rc, along with the derived values of ρc and LT normalized to the contact width. Gr/SiO2 Gr/Ge

Rs [KΩ/sq.] 0.12 0.31

Rc [Ω] 47 73

ρc [Ω.µm] 378 584

LT [µm] 0.17 0.19


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Figure 6 Energy band diagram configurations of Gr and Gr/Ge FETs at different modes of operation (Drawn to scale on the energy axis, not to scale on the length axis). The energy band diagrams of Gr-FETs shown at (a) equilibrium where the Gr film is assumed to be p-doped. (b) Vg>0 where the p-type conductance of the Gr channel is strongly increased. (c) Vg0 where the induced electric field in the Ge layer gives rise to an electron accumulation at the Ge/Ge oxide interface leading to a negative slope in the Ge energy bands. (f) Vg

Vertical Charge Transfer and Lateral Transport in Graphene

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