Letter pubs.acs.org/NanoLett
Vertical versus Lateral Two-Dimensional Heterostructures: On the Topic of Atomically Abrupt p/n-Junctions Ruiping Zhou,*,†,‡ Vaibhav Ostwal,†,‡ and Joerg Appenzeller†,‡ †
Birck Nanotechnology Center and ‡Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, United States S Supporting Information *
ABSTRACT: The key appeal of two-dimensional (2D) materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene for electronic applications certainly lies in their atomically thin nature that offers opportunities for devices beyond conventional transistors. It is also this property that makes them naturally suited for a type of integration that is not possible with any three-dimensional (3D) material, that is, forming heterostructures by stacking dissimilar 2D materials together. Recently, a number of research groups have reported on the formation of atomically sharp p/n-junctions in various 2D heterostructures that show strong diode-type rectification. In this article, we will show that truly vertical heterostructures do exhibit much smaller rectification ratios and that the reported results on atomically sharp p/n-junctions can be readily understood within the framework of the gate and drain voltage response of Schottky barriers that are involved in the lateral transport. KEYWORDS: Vertical transport, TMD, BP, heterostructure, Schottky barrier
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the actual vertical stack, lateral gated portions of the respective 2D layers are involved in current transport. For p/n-junctions to then dominate, the lateral resistance contributions of these segments must be ignorable if compared with the vertical p−n junction. However, as we will show here for heterostructures from MoS2/BP and MoS2/WSe2, (1) there exists only a rather small gate voltage window within which the vertical transport dominates device characteristics for the lateral/vertical layout employed in references10,11,13,14 and (2) the strong rectifying behavior observed is likely to be largely associated with the drain voltage polarity-dependent response of the respective gated Schottky barriers at the source and drain of the device structures, and not the heterointerface, as long as a planar device layout is employed. Note that while we are not arguing here about “all in-plane” devices with the heterostructure lying in the same plane as described in many epitaxially grown materials,12,17,20 our discussion about the impact of gated Schotty barriers on the device characteristics as presented below holds true even in these structures. We will make the argument by showing that lateral/vertical device structures fabricated in our lab show indeed the same device characteristics as reported before, while on the other hand “truly’ vertical diode structures from the same materials fabricated by us do not show the expected strong rectification. In this context, it is worth noting that while one might argue that a vertical structure with metal contacts on top and below
ince the discovery of semiconducting behavior of transition metal-dichalcogenides (TMDs) and black phosphorus (BP) at atomic layer thicknesses,1−9 the scientific community has explored various electronic and optoelectronic properties of this fascinating new class of two-dimensional (2D) materials. More recently, researchers started to study various heterostructures from stacked 2D materials to investigate the interplay between dissimilar layers with a particular focus on the electrical properties of the newly formed van der Waals heterointerfaces.10−18 Electrical transport measurements on MoS2/WSe2,10,14 MoS2/BP,11 MoSe2/WSe2,13 and p-MoS2/n-MoS219 vertically stacked layer systems involving both monolayers (MLs) and/or few layers (FLs) consistently show p/n diode-type characteristics with strong rectification ranging from 102 up to 105. The common notion is that atomically abrupt p/n-junctions that form at the heterointerface are responsible for at least some of this rectifying behavior.10,11,14 In other words, current flow through these structures is interpreted to be dominated by vertical transport from one layer to the other. While the concept of atomically sharp p/n-junctions is still under debate in the community, the idea of an atomically sharp p/n-junction implies that carrier depletion does not occur in the vertical direction, as typically observed for lateral structures. This in turn results in an abrupt vertical band structure profile from n to p, an interpretation that we will challenge in this article as the cause for the observed current rectification. Carefully evaluating the device layout in all of the above cited articles,10,11,13,14 one notices that source and drain contacts are always arranged in a planar architecture, that is, in series with © XXXX American Chemical Society
Received: April 12, 2017 Revised: July 11, 2017
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Figure 1. (a) Graphic representation of the fabrication process flow for the vertical devices: Step 1, BP flake is peeled onto a gold pad, which is deposited on a 90 nm SiO2/p++ Si substrate. Step 2, an HSQ mask is created by e-beam lithography, serving as an isolation layer, leaving an opening to the BP flake. Step 3, MoS2 is transferred and the supporting film is dissolved. Step 4, top electrode is deposited in the opening region and across the isolation layer. (b) Cross section view of a vertical device. A Ti electrode serves as the drain and the gold pad serves as the source in this 2 terminal device.
actual size of the opening as well as the HSQ and MoS2 flake thickness are all critical parameters that need to be carefully adjusted for the successful fabrication of the vertical diode. In fact, if the opening is too small or the flake too thick we frequently observed that the top flake would not make contact to the bottom because “sagging” of the MoS2 flake would be incomplete. Similarly, a too high HSQ layer that improves the electrical isolation can prevent proper contact formation. Typically, MoS2 thicknesses below 15 nm and openings in the 1 to 5 μm2 range were found to be adequate. Figure 1b shows the cross section of our device schematically. (For a set of optical images illustrating the process flow, see Figure S1 in Supporting Information.) Characteristics of three vertical heterostructure diodes are displayed in Figure 2. Various flake thicknesses have been carefully investigated and none of them showed any substantial rectification as apparent from the plots (see rectification ratio (RR) values in the table). Note that currents are not normalized by the contact area because very similar layouts were employed. While the general trend of higher current levels in devices with a smaller total flake thickness holds true (compare device #1 to #3), stacks that contain very thin layers of BP showed smaller than expected currents due to an almost twice as large bandgap of BP for a 5 nm thick flake if compared with the 15 and 27 nm thick BP flakes.21 The electrical I−V plots of all devices occur very similar in shape to gate leakage characteristics in conventional field-effect transistors with direct tunneling and Fowler Nordheim tunneling dominating depending on the electric field.22,23 Note that the achieved current densities are much higher than previously reported values,24,25 confirming that high quality interfaces have been created for all our devices. As we will argue next, the discrepancy between our data and previous reports lies in fact in the lateral transport
the 2D stack, as described in Figure 1, is distinctly different from a lateral/vertical layout as employed by refs 10, 11, 13, and 14, the absence of a depletion layer as assumed to prevail in an abrupt p/n junction should still dominate the true vertical transport. Furthermore, we will guide the reader through a detailed analysis of the impact of the drain voltage on the lateral/vertical device characteristics that explains the observed strong rectification as a contact effect. We will also argue that in a truly vertical structure, rectification can even be achieved without employing a 2D heterointerface if dissimilar contact metals are used to create a different Fermi level line-up for the two electrodes. To implement a truly vertical structure with a 2D heterointerface and with no in-plane segments that are involved in current transport, devices were fabricated as shown in Figure 1a: First (step 1), a BP flake was mechanically exfoliated onto the surface of a predefined gold metal pad, where gold is chosen as the bottom contact to avoid formation of an oxide layer between the exposed bottom electrode and the TMD stack. Next (step 2), an isolation layer of 70 nm hydrogen silsesquioxane (HSQ) is patterned by electron beam (ebeam) lithography, leaving an opening on top of the BP flake. This HSQ thickness ensures proper electrical isolation. In step 3, a MoS2 flake is dry-transferred onto the opening using poly(methyl methacrylate)/poly(vinyl alcohol) (PMMA/PVA) as the supporting film. After dissolving the PMMA film, in step 4 a top-electrode of 100 nm titanium is defined by e-beam writing and metal deposition. The bottom gold pad and the top electrode form the two terminals of the vertical diode, whose dimensions in the transport direction are defined by the sum of the flakes’ thicknesses. While gating is unavailable in this device layout, lateral transport is entirely eliminated. Note that the B
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Figure 2. Log-scale IDS−VDS curves from three vertical BP/MoS2 heterostructures. The left inset shows a linear plot of device 1. The right inset displays an optical image of the actual device before the top electrode is deposited. Note that the isolation layer is not visible in this graph; for more details refer to Figure S1 in Supporting Information. The table summarizes the thicknesses of the various flakes and their RR calculated from IDS(VDS = −2 V)/IDS(VDS = +2 V). The contact area for device 1 and device 3 is 1.9 μm × 1.9 μm each and the contact area for device 2 is 1.2 μm × 1.4 μm.
segments that exist for all previously reported devices. Note that the picture of a “depletion-free” p/n-junction should have given rise to rectification in our true vertical design as described in the previous reports, because the heterointerface is in series with the metal-to-TMD contact interfaces. To verify the critical importance of the lateral device segments, we have fabricated devices that are similar in layout to what was previously published.10,11,13,14 In detail, the fabrication of the devices proceeds as follows: First, a MoS2 flake is exfoliated onto a SiO2/Si substrate. Then BP is dry transferred on top of MoS2, overlapping only with a portion of the MoS2 flake. The dry transfer approach used here is identical to the one described above for the vertical devices. After transfer of the top layer, four electrodes are ebeam patterned and nickel (Ni) contacts of 70 nm are deposited by e-beam evaporator. The readily fabricated device is schematically illustrated in Figure 3a. A and B denote electrodes contacting the MoS2 flake; C and D are electrodes attached to the BP flake. The “green” and “blue” current (IDS) versus gate voltage (VGS) characteristics in Figure 3b obtained for a drain voltage of VDS = −3 V are as expected for a MoS2 and BP channel, respectively. Note that all IDS versus VGS measurements are performed employing a “pulse method” in which a set of gate and drain voltages is applied, the current through the device is read and subsequently the applied voltages are removed for three seconds before the next data point is acquired. This approach has been successfully used by us previously to eliminate hysteresis effects due to charging of the substrate.26 Measuring between contacts B and C results in the “red solid” device characteristics. Interestingly, when assuming that a simple series resistance combination of the MoS2 and the BP transistor response describes the transport from A to D, the “dash-dotted red” line is obtained from the measured green and blue data sets. The agreement between the two red curves is rather apparent and implies that the individual transistor characteristics from MoS2 and BP dominate the transport through the heterostructure for almost all gate voltages! In other words, for example, for −7 V < VGS < +50 V (gate range S3) the resistance of the BP device is much larger than the interfacial resistance between MoS2 and BP, whereas for −50 V < VGS < −30 V (gate range S1) it is the off-state of
Figure 3. (a) Schematic 3D, cross section, and optical images of a lateral device under investigation. A and B denote electrodes on the MoS2 flake; C and D are contacts to BP. (b) Transfer plots of MoS2 (green, between A and B), BP (blue, between C and D), and MoS2 to BP (red, between B and C). The red dashed line is the result of combining the experimental results from MoS2 (A−B) and BP (C−D) in a series resistance arrangement.
the MoS2 device that defines the total resistance. Only in the gate voltage range S2 one may argue that the interfacial resistance dominates transport from B to C, a statement that is strongly entangled with the choice of drain voltage as will be explained in the following. To be clear, the comparison between the two red curves does not imply that MoS2 or BP devices are dominated by scattering inside the respective gated channel. In fact, both devices behave a Schottky barrier transistors as previously discussed by us,27 where gated source/drain contact regions determine the actual device characteristics. In the gate voltage range S2, BP allows for hole transport through the valence band (operation is in the p-branch), while MoS2 only permits electron transport through the conduction band. In this gate voltage window, for a VDS of −3 V, transport through the structure occurs by band-to-band tunneling.28,29 Although this statement seems to imply that at least for a certain gate voltage range the p/n-junction dominates the transport, we will argue next that the gate voltage range for which the interfacial resistance dominates changes with the drain voltage and thus does not allow attributing the rectification of device characteristics as a function of VDS at any fixed gate voltage to the interfacial resistance. C
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At any given gate voltage, it is the difference in current levels between the solid red and red dashed lines that determines the rectification behavior of the device. Not the interface but the drain voltage-dependent Schottky barrier response gives rise to the apparent strong rectification in devices with lateral transport segments. Figure 5 makes this point very apparent by illustrating the interplay between gate and drain voltages in an orthogonal fashion. To illustrate the universality of our interpretation, we intentionally picked another device with a layout similar to what was shown in Figure 3a, but with BP exfoliated on the substrate first and then MoS2 is transferred on top. Figure 5a shows measurements through the entire heterostructure (from contact B to C) again for two drain voltages similar to Figure 4a. Figure 5b illustrates the corresponding rectification ratio between a drain voltage of +3 V and −3 V with four distinct gate voltages marked. The clear nonmonotonic dependence is a result of the drain induced “shift” between the two red IDS−VGS curves in Figure 5a. A large ∼104 rectification ratio is found when one of the two red curves exhibits its current minimum. The same high rectification ratio can also be directly measured in an IDS− VDS configuration as shown in Figure 5c,d. Note that in the case of Figure 5c, the drain voltage sweep occurs under discrete gate voltage conditions (nonpulse type). This results unavoidably in some charging of the substrate that causes a certain amount of hysteresis that cannot be avoided for 90 nm thick silicon dioxide films as used in this study. While the actual gate voltage values at which certain rectification ratios occur are not the same between Figure 5 panels b and d, the trends and rectification ratios (RR)-values are identical, that is, a monotonic increase from RR = 10 to 104 occurs when scanning from VGS = −50 V toward more positive gate voltages, followed by a decrease of RR from 104 to 1 and a subsequent increase of RR. In total, six lateral MoS2/BP devices were carefully characterized in this work, all exhibiting identical features with some variations in the actual rectification values. Although both types of overlaps, (i) BP on top of MoS2 as in Figure 3a and (ii) MoS2 on top of BP, were explored, there is no apparent difference between (i) and (ii). All of the above is in agreement with the discussion of the gate and drain voltagedependent response of Schottky barrier devices as emphasized above. In particular, it can be noted that our lateral devices exhibit similarly high rectification ratios as reported previously, indicating that our device’s quality is on par with other groups’ publications, while our truly vertical devices show dramatically reduced RR-values as reported here for the first time. To prove that the above discussion is valid for other material combinations, lateral heterostructure devices of the type shown in Figure 3a were also built from MoS2/WSe2. Device characteristics showed similar dependencies as discussed in the last section, that is, a drain voltage dependent shift of the WSe2 IDS−VGS characteristics is mainly responsible for the high rectification of about 105 obtained in these lateral heterostructures. A comparison of the rectification ratios obtained from output and transfer characteristics is shown in Figure S3 of the Supporting Information. After having established that truly vertical 2D heterostructures do not show the same degree of rectification as their lateral counterparts due to the absence of the interplay between gate and drain, we will discuss next the key ingredient responsible for the rectification in vertical TMD devices by evaluating devices that consist of MoS2 flakes sandwiched between the gold and the titanium electrodes. The sample
To appreciate the entangled, or simultaneous, impact of the gate and the drain, Figure 4 shows device characteristics as a
Figure 4. (a) Transfer curves of MoS2 (A−B), BP (C−D), MoS2 to BP (B−C) at different VDS (−3 V and +3V). Solid lines are for −3 V, dashed lines are for +3 V. (b) Experimental results of BP demonstrating the shift of the transfer curves under different VDS, measured on a 20 nm SiO2 substrate.
function of gate voltage for discrete drain voltages. Figure 4a shows the same device as in Figure 3 for positive and negative VDS, while Figure 4b illustrates the drain voltage impact in detail for a BP-only device on a silicon/silicon dioxide substrate with 20 nm SiO2. Note that a thinner gate dielectric is chosen here to ensure a more detailed evaluation of the drain voltage dependence. The key is the strong dependence of the current minimum on the applied drain voltage. As has been discussed by us in detail before,30 hole injection stemming from the source for negative drain voltages is independent of the actual drain voltage value in the subthreshold region of the device (the gate voltage regime between −6 and −3 V), while electron injection for negative drain voltages and positive gate voltages (the gate voltage regime between 0 V and +10 V) occurs from the drain and is thus strongly VDS-dependent. The situation is exactly reversed for positive drain voltages as apparent from the dashed lines in Figure 4b. It is this particular drain voltage dependence of the injection through the Schottky barriers that is responsible for the rectification observed in devices that include laterally gated portions in the transport! A complete analysis of a BP-only device in terms of rectification behavior is shown in Figure S2 of the Supporting Information. With this discussion for a simple BP device in place, the apparent shift between the two red curves in Figure 4a for the heterostructure can be readily understood. Note that the minimum current levels in the red curves, which reflect measurements across the entire heterostructure, occur exactly at the minimum current level points of the BP segment (blue). D
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Figure 5. (a) Transfer curves for another device with a layout as illustrated in Figure 3a. RR1 to RR4 indicate rectification ratios taken at four different gate voltages. RR is defined by IDS(VDS = +3 V)/IDS(VDS = −3 V). (b) Plot of the rectification ratio (derived from transfer curves) versus gate voltage. RR1 to RR4 are marked by black circles in the plot, each corresponding to one particular gate voltage in (a). (c) Output curves of the same heterostructure under four gate voltages. RR′1 to RR′4 are ratios derived from IDS(VDS = +3 V)/IDS(VDS = -3 V). (d) Plot of the rectification ratio (derived from output curves) versus gate voltage. RR′1 to RR′4 are marked by colored circles on the plot, each corresponding to a particular output curve in (c).
inset of Figure 6. With Ti having a smaller work function than Au, higher current densities are thus achievable for negative VDS if the flake is not too thin. In fact, the observed trend with flake thickness as displayed in Figure 6 implies that direct tunneling through sufficiently thin flakes can ultimately “wash out” the rectification that is observable for the thicker flakes. Note that when combining thin layers of MoS2 as in Figure 2 with thick layers of BP (to create a thick stack), no asymmetry is observed. The key lies in the fact that thick BP flakes exhibit very small band gaps of only around 300−400 meV as we experimentally verified before.22 Because of this, the additional BP layer in essence does not impact the vertical transport and does not cause any asymmetry in the IDS−VDS characteristics. A more detailed analysis will be necessary to unambiguously identify the quantitative dependences in the IDS−VDS characteristics of vertical devices in the future. In conclusion, we have shown through a careful analysis of our lateral/vertical devices and comparison with previously reported data that rectification in lateral/vertical heterostructures is likely a contact effect in many instances and not related to atomically abrupt p/n-junctions. It is in fact the interaction between the gate and the drain that gives rise to rectification ratios as high as 104 in MoS2/BP structures and beyond 105 for the MoS2/WSe2 system. We further substantiated this finding by analyzing truly vertical devices where we did not observe any strong rectification, which should have been expected based on the picture of a depletion free p/n-junction between stacked 2D layers. Moreover, we have provided initial evidence for the impact of the metal contact workfunction on the rectification in vertical TMD diodes, showing that for sufficiently thick MoS2 flakes rectification ratios of around 25 are achievable. Furthermore, we believe that carefully designing the doping
fabrication employed is otherwise identical to the one described above including the critical isolation layer. Figure 6 shows three
Figure 6. Current density versus VDS for three vertical MoS2 devices of different thickness. The rectification ratios are shown on the legend. As the thickness increases, the ratio becomes larger.
exemplary truly vertical MoS2 devices with flake thicknesses of 8, 18, and 23 nm. While the rectification ratio is close to unity for the thinnest flake in agreement with our observations in Figure 2, thick flakes can exhibit even in a truly vertical device structure appreciable rectification ratios. It is the difference in the injection from a large or small work function metal contact into the conduction or valence band (whichever gives rise to the smaller barrier) that is responsible for the different current levels at positive and negative drain voltages. For example, in the cases displayed in Figure 6, a positive VDS that is applied to the titanium electrode results in electron injection from the Aucontact. On the other side, negative VDS-values imply electron injection from the Ti-contact as schematically illustrated in the E
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profile of a vertical TMD stack may indeed result in p/njunctions on a much smaller length scale than typically achievable in lateral structures. Methods. Dry Transfer of the Second 2D Flake. During the fabrication of vertical heterostructures, a dry transfer method was employed using PVA and PMMA as a double stack film. First, PVA was spun onto the silicon/silicon dioxide substrate at 3000 rpm, followed by a 5 min bake at 75 °C. Next, PMMA is spun onto the PVA layer using the same speed and baking conditions. After formation of the double layer stack, flakes that were intended for transfer were mechanically exfoliated onto the PMMA side of the stack. The PVA/ PMMA/2D-flake stack was next peeled off the substrate and aligned under a microscope relative to the actual sample that consists at this stage of the Au electrode, a first 2D flake and an isolation layer with a hole. By applying some pressure while simultaneously heating the substrate to around 110 °C, the flake attached to the PVA/PMMA stack is transferred onto the actual sample. Last, the PVA and PMMA films are dissolved in water and acetone solutions, respectively, leaving the transferred flake in the target zone. HSQ as an Isolation Layer. HSQ (4%), a negative e-beam resist, was spun at 6000 rpm onto flakes located on top of the Au electrodes. This resulted in HSQ film thicknesses of about 70 nm. Electron beam lithography is used to pattern a hole into the HSQ that allows for access of the underlying flake. Next, a second 2D film can be exfoliated on top of the hole followed by the top electrode formation or the top electrode is directly defined on top of the first flake.
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ASSOCIATED CONTENT
S Supporting Information *
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.7b01547. Device fabrication pictures of vertical heterostructure, and detailed measurement characteristics on lateral BP device as well as lateral MoS2−WSe2 heterostructure (PDF)
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. ORCID
Ruiping Zhou: 0000-0002-9531-7304 Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS This work was in part supported by FAME, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
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REFERENCES
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