Vertically Stacked and Self-Encapsulated van der Waals

Subscriber access provided by FLORIDA INTL UNIV

Article

Vertically Stacked and Self-Encapsulated van der Waals Heterojunction Diodes Using Two-Dimensional Layered Semiconductors Jinshui Miao, Zhihao Xu, Li Qing, Arthur Bowman, Suoming Zhang, Weida Hu, Zhixian Zhou, and Chuan Wang ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.7b05755 • Publication Date (Web): 19 Sep 2017 Downloaded from http://pubs.acs.org on September 19, 2017

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a free service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are accessible to all readers and citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

ACS Nano is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Vertically Stacked and Self-Encapsulated van der Waals Heterojunction Diodes Using Two-Dimensional Layered Semiconductors Jinshui Miao,† Zhihao Xu, † Qing Li,‡ Arthur Bowman,§ Suoming Zhang,† Weida Hu,‡ Zhixian Zhou,§ Chuan Wang*,†, †

⊥

Electrical and Computer Engineering, Michigan State University, East Lansing,

Michigan 48824, United States §

Department of Physics and Astronomy, Wayne State University, Detroit, Michigan

48201, United States ‡

State Key Laboratory of Infrared Physics, Shanghai Institute of Technical Physics,

Chinese Academy of Sciences, 500 Yutian Road, Shanghai 200083, China ⊥

Electrical & Systems Engineering, Washington University in St. Louis, St. Louis,

Missouri 63130, United States *

Corresponding author: [email protected]

Abstract: Van der Waals heterojunctions using 2D semiconducting materials could overcome the defect issues included by lattice mismatch in conventional epitaxially-grown heterojunctions with bulk materials and could enable a much wider palette for choice of materials and more sophisticated device design. Such 2D heterojunction devices are of great interest for important functional devices such as diodes, bipolar junction transistors, light-emitting diodes, and photodetectors. In this paper, we demonstrate a truly vertical p-n heterojunction diode built from 2D semiconductors (MoS2 and BP) and compare its performance against conventional lateral 2D heterojunction devices (partially overlapped 2D heterostructures). Both vertical and lateral p-n heterostructure diodes exhibit strong rectification ratio even with no gate voltage applied. More importantly, the results show that the vertical diode delivers 70 times higher current density under forward bias than a conventional lateral device design and the improved device performance can be attributed 1 ACS Paragon Plus Environment

ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 24

to the complete elimination of series resistance. Low-temperature measurements and TCAD simulations are used to determine the barrier height at the junctions. Moreover, the vertical device structure allows certain ambiently unstable 2D semiconductors to be fully encapsulated by the materials on top, preventing the material from degradation. This work demonstrates the potential of using the vertically stacked 2D semiconductors for future nanoelectronic and optoelectronic devices with optimal performance.

Keywords:

2D

semiconductor,

heterostructure,

p-n

encapsulation

2 ACS Paragon Plus Environment

junction

diode,

vertical,

Page 3 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Figures for Table of Contents


ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

As an alternative to silicon, layered two-dimensional (2D) materials with atomically smooth surface such as graphene,1,

2

transition metal dichalcogenides (TMDs),3-5 and

black phosphorus (BP)6, 7 are of considerable interest for nanoelectronic applications. Monolayer or few-layer TMDs and BP have been widely studied as potential channel materials for beyond-silicon electronics as they both offer decent bandgap and carrier mobility.6,

8-10

For example, MoS2 based n-type transistors exhibit very high on/off

current ratios and excellent current saturation characteristics even for very small channel length.9,

11

Very well-behaved p-type transistors based on BP with room-temperature

field-effect mobility of up to 1000 cm2/V·s and high current density have also been demonstrated.6,

12, 13

Other functional devices built from MoS2 or BP, such as

photodetectors,14-16 digital inverters,17-19 memory devices,20-22 and chemical sensors23-25 have also been demonstrated to be superior to their conventional counterparts. Semiconductor p-n junction is one of the fundamental building blocks for many important devices, such as bipolar junction transistors, light-emitting diodes, photodiodes, and solar cells, etc.26 In conventional p-n heterojunctions, lattice mismatches may result in defects when epitaxially growing an n-type semiconductor on another p-type semiconductor.27 However, by using layered 2D semiconductor materials, atomically sharp van der Waals p-n heterojunctions without defect issues can be easily achieved by assembling dissimilar 2D materials together.28 Recently, a number of researchers have reported various 2D material heterostructures including BP/MoS2,29, 30 WSe2/MoS2,31-34 graphene/WSe2,35,

36

WSe2/SnSe2,37 and graphene/MoS2,38-40 etc. Electrical transport

measurements on those 2D heterostructure p-n junction devices consistently show diode-like rectifying behaviors with high rectification ratio. Others also reported quasi-vertically integrated heterostructures of 2D materials for p-n diodes, photodetectors, and inverters.41-43 However, by carefully evaluating the device structure in all previously reported work, one can see that the devices are rarely truly vertical. Those heterojunctions are not strictly vertically stacked together because there is always a lateral 2D material 4 ACS Paragon Plus Environment

Page 4 of 24

Page 5 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

channel outside the overlapped heterojunction region that is also involved in the current transport between the source/drain electrodes. Since the lateral region may contribute to very significant series resistance, it will greatly reduce the device output current. This is especially true when no gate voltage is applied. Moreover, for some sensitive 2D materials such as BP that are unstable in ambient conditions, a lateral heterostructure will have part of the material exposed and the device will inevitably degrade rapidly in ambient conditions.44 In this study, we report a device structure for achieving truly vertical 2D van der Waals p-n heterojunction diode using BP and MoS2. Our design completely eliminates the series resistance that is ubiquitous in conventional lateral 2D heterostructues, which enables us to achieve up to 70 fold improvement in device forward current density. Furthermore, the vertical device design allows sensitive 2D materials that are susceptible to degradation under ambient conditions such as BP to be fully encapsulated by another chemically stable 2D material on top. Experimental results confirm that the vertical BP/MoS2 heterojunction diodes demonstrated in this work can preserve its electrical characteristics even after being stored in ambient for extended periods of time. Such vertical 2D van der Waals heterostructure could be a viable approach for achieving high performance 2D semiconductor devices including photodetectors and heterojunction bipolar transistors.

RESULTS AND DISCUSSION The fabrication procedure for the vertically stacked BP/MoS2 p-n junction diode is schematically illustrated in Figure 1a. In brief, e-beam lithography (EBL) was used to pattern a square opening (4×4 µm2 or 5×5 µm2) on a SiO2/p+-Si wafer with a 50-nm-thick SiO2 dielectric layer. Buffered oxide etch solution (NH3F: HF (6:1)) was subsequently used to etch away the entire SiO2 layer inside the opening, leaving behind a square trench on the wafer. A 50-nm-thick Au film deposited by thermal evaporation was used to fill the 5 ACS Paragon Plus Environment

ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

square trench followed by lift-off to form the bottom electrode (Figure 1a (i)). The Au electrode and the heavily doped p+-Si substrate form very good Ohmic contact, as confirmed by the linear I-V relationship with very small resistance (57 Ω) as shown in Figure S1. Few-layer p-type BP flake was then transferred onto the as-fabricated Au/p+-Si bottom electrode (Figure 1a (ii)). To achieve p-n junction diode, an n-type MoS2 flake was dry-transferred onto the BP flake using polydimethylsiloxane (PDMS) as the supporting substrate. The MoS2 flake fully covers the BP (Figure 1a (iii)) and due to van der Waals interactions, BP/MoS2 heterojunctions can be formed at the overlapped regions. Finally, the top electrode was patterned onto the MoS2 flake by EBL and thermal evaporation of 50-nm-thick Au film (Figure 1a (iv)). In such a device, the current can flow between the bottom Au/p+-Si electrode and the top Au electrode through the semiconducting BP/MoS2 heterostructure (Figure 1a (v)). Figure 1b shows the optical microscope images of a representative vertical BP/MoS2 p-n junction diode after each fabrication step. The total active cross-sectional area of the device is determined by the overlapping area, which is just the size of the bottom electrode (4×4 µm2 or 5×5 µm2). One advantage of such truly vertical device structure is that it allows the material that might be susceptible to degradation under ambient condition to be fully encapsulated. Specifically for the device in this work, the BP surface which is known to degrade rapidly in air is fully sealed by the MoS2 layer and Au electrode on top. Figure 1c and d compare the ambient stability of vertically and laterally stacked BP/MoS2 p-n junction diodes. For the vertical p-n diode, no degradation was observed after 7 days of ambient exposure because the BP flake was fully sealed by the few-layer MoS2 flake (Figure 1c). In contrast, for a lateral p-n diode, the unprotected part of the BP flake underwent significant degradation after being stored in ambient condition for merely 2 days (Figure 1d). One can see that the few-layer MoS2 can effectively protect sensitive BP material from ambient degradation. Figure 1e presents the Raman spectra of MoS2, BP, and BP/MoS2 heterostructure. The observed Raman-active modes of MoS2 (green line) and 6 ACS Paragon Plus Environment

Page 6 of 24

Page 7 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

BP (blue line) are consistent with previously reported work.7, 45 The peaks from both MoS2 and BP can be observed in the BP/MoS2 overlap region (red line) indicating good film quality in the heterostructure after adhesive tape exfoliation and PDMS dry-transfer. Electrical measurements were carried out under ambient conditions and at room temperature to compare the vertically stacked devices with different channel materials BP, MoS2, and BP/MoS2 heterostructure (Figure 2). We first compare the output characteristics of the three types of vertical devices with no external gate voltage applied. The current is normalized by the area of the bottom electrode to obtain the current density. In order to achieve decent current density without gate voltage, relatively thick MoS2 or BP flakes (> 10 nm) were used as the channel materials. Since the MoS2 or BP film thickness is larger than the out-of-plane screening length of ~ 10 nm, in this scenario, carriers still exist along the vertical channel even without gate voltage. Thicker MoS2 or BP films also offer the benefit of higher carrier mobility, which is a crucial factor for un-gated vertical devices. Additionally, thicker MoS2 film can better prevent the O2 and H2O in the air from diffusing into the BP layers. More importantly, if the thickness of MoS2 or BP film is too thin (e.g. less than 5 nm), the direct quantum tunneling between top and bottom electrodes will become dominant and degrade the rectifying characteristics of the BP/MoS2 p-n diodes. Figure 2a shows the optical microscopy image, atomic force microscopy (AFM) characterization, and I-V characteristic of a representative Au-BP-Au vertical device. The device exhibits an almost symmetric I-V behavior with a low Schottky barrier and a very high current density of up to 600 A/cm2 (corresponding to a current of ~ 140 µA) at a voltage of -1 V. Figure 2b presents similar characterization performed on a vertical Au-MoS2-Au device with a MoS2 flake thickness of ~ 24 nm. Similar to the BP device, the vertical MoS2 device exhibits slightly Schottky-like I-V behavior. The current density on the other hand is significantly smaller than the BP device, at around 25 A/cm2 (or ~ 6.5 µA) for a voltage bias of 1V, which is due to a combination of the lower carrier mobility in MoS2, a slightly larger Schottky 7 ACS Paragon Plus Environment

ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

barrier at the Au/MoS2 contact, and a relatively low carrier density in the MoS2 channel with no gate voltage is applied. Lastly, the Au-BP-MoS2-Au heterostructure device is characterized as shown in Figure 2c. One can see that the device I-V curve shows predominant current-rectifying behavior with a rectification ratio of ~ 28.5 and a forward current density of ~ 71 A/cm2. The Schottky barrier at the Au/MoS2 contact can be ruled out as the cause of the rectifying behavior because the forward current of the Au-BP-MoS2-Au hetero structure is measured when the Au/MoS2 Schottky junction is reversely biased. By comparing the three types of vertical devices, we can safely conclude that the introduction of BP/MoS2 heterostructure forms a heterojunction p-n diode. The schematic energy band diagrams for an ideal heterojunction diode at the BP/MoS2 interface are presented in Figure 2d. When no external voltage is applied, the p-n junction is in thermal equilibrium and the Fermi energy level is constant throughout the entire system, as shown in Figure 2d (i). Under forward bias, the potential barrier decreases leading to majority carriers (electrons) in MoS2 being injected into the BP side (Figure 2d (ii)). Under reverse bias, the potential barrier increases, preventing the electrons in MoS2 from being injected into the BP side. The minority carriers (electrons in BP and holes in MoS2) are extracted into the opposite side, resulting in reverse current. Since the concentrations of minority carriers are very low, the current under reverse bias is very small, resulting in the conventional diode-like rectifying I-V curve. The truly vertical 2D van der Waals heterojunction p-n diode demonstrated in this work has significant performance advantage compared with the lateral one widely reported in the literature. We have fabricated and compared the performance of both vertical and lateral BP/MoS2 p-n diodes. As shown in Figure 3a, while both types of devices clearly exhibit current rectifying behavior with rectification ratio of ~ 27 for the vertical diode and ~ 28 for the lateral one, the forward current density of the vertical diode is ~ 29.4 A/cm2 (red trace) which is much higher than the ~ 0.43 A/cm2 measured from the lateral device (blue trace). The results above can be explained by a simplified 8 ACS Paragon Plus Environment

Page 8 of 24

Page 9 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

model by considering the different components that govern the current transport in the p-n junction diode. As illustrated in Figure 3b, the total resistance of a BP/MoS2 heterojunction diode can be roughly divided into four parts, including: 1) the resistance of BP/MoS2 p-n junction at the interface (Rj); 2) the sheet resistances of BP (Rob) and MoS2 (Rom) in the overlapped junction region; 3) the series resistance of BP (Rsb) and MoS2 (Rsm) outside the overlapped region; and 4) the contact resistances of Au/BP (Rcb) and Au/MoS2 (Rcm). The junction resistance Rj of the p-n diode governs the rectifying characteristics observed in both types of devices. While the values of the sheet resistance Ro and contact resistance Rc components are likely similar in both the vertical and lateral diode devices, the contributions from the series resistance Rs component are drastically different. For a vertical BP/MoS2 p-n diode, the carriers only have to travel across a very thin channel of a < 30 nm with essentially no series resistance. In contrast, for a lateral BP/MoS2 diode, since no gate voltage is applied to modulate the carrier concentration, the series resistances through the relatively long (a few µm) BP (Rsb) and MoS2 (Rsm) layers are very significant. The fact that the vertical diode device exhibit ~ 70 fold improvement in forward current density compared to the lateral device indicates that the series resistance is the limiting factor for the device performance. Another important advantage of the vertical heterojunction diode structure is its ability to get the sensitive material protected from ambient degradation. In our BP/MoS2 p-n diode, the BP layer is intentionally placed at the bottom so that it can be fully encapsulated by the MoS2 and Au electrode on top. Figure 3c and d show the ambient stability study of vertical and lateral BP/MoS2 p-n junction diodes. The evolution of surface morphologies overtime for both vertical and lateral BP/MoS2 p-n diodes are presented in the Supporting Information. From both the AFM image (Supporting Information Figure S2) and electrical measurements (Figure 3c and Supporting Information Figure S4a), one can find that a vertical BP/MoS2 p-n diode could still preserve good electrical performance even after being stored in ambient conditions for 7 9 ACS Paragon Plus Environment

ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 10 of 24

days. In contrast, a lateral BP/MoS2 p-n diode whose BP layer is only partially covered by the MoS2 completely degraded and exhibited no current signal after being stored in ambient conditions for 2 days (Figure 3d and Supporting Information Figure S3 and S4b). On the basis of above experiments, one can conclude that the MoS2 layer in the vertical diode provides a sufficient barrier for moisture diffusion and effectively suppress device degradation. To further investigate the charge transport through the Au-BP-MoS2-Au vertically stacked p-n diodes, we have also carried out low temperature electrical studies. Figure 4a shows the output characteristics of a representative vertical diode measured at a low temperature of 180 K. The diode exhibits good current-rectifying characteristic with slightly improved rectification ratio of ~ 116. The diode ideality factor can be determined from a plot of the logarithmic output characteristics at the forward bias based on the following equation:26 = exp

− 1

Where I is the diode current, V is the applied voltage, Isat is reverse saturation current, n is the ideality factor, T is the temperature, q is elementary charge, and kB is the Boltzmann’s constant. For voltage greater than a few kBT (e.g. > 0.1 V), the “-1” term in the above equation can be ignored. Taking the logarithm of both sides of the equation gives the following equation: ln = ln +

When plotting the natural logarithm of the diode current versus the applied voltage based on the above equation, the slope gives q/nkBT, from which the ideality factor (n) for the vertical diode device in this work is extracted to be 1.32 (Figure 4b), indicating good interface qualities at the BP/MoS2 junction. The temperature dependent transport characteristics allow us to determine the potential barrier height across the vertical BP/MoS2 junction. Since the BP/MoS2 junction dominates the rectifying characteristics in the vertical p-n diodes (Figure 2c), we can 10 ACS Paragon Plus Environment

Page 11 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

approximately treat the heterojunction barrier as a Schottky barrier. The thermionic emission theory gives the relationship between the diode current and Schottky barrier height: = ∗ exp

− exp − 1 ! "

Where A is the area of the Schottky junction, A* is the effective Richardson constant, q is the elementary charge, kB is the Boltzmann constant, and T is the temperature.46 Quantitative analysis of the Schottky barrier height φB can be determined by investigating the temperature dependent diode current in the reverse bias saturation regime (exp(qVbias/ηidkBT) term ? >@ A B

CD E FGE

, where

>? HI >@ are the density of states and Eg is the band gap. Carrier transport is dominated by continuity equation: ∇ ∙ LK M;,< =

O;,< O

, where J is the current density, n and p are the

electron and hole density. The dominant current in BP/MoS2 p-n diode at low temperature is tunneling current which can be simulated using simplified band-to-band tunneling (BBT) model. Shockley-Read-Hall (SRH) and Auger recombination models were used to simulate the temperature-dependent generation-recombination (G-R) of minority carriers. In the simulation, the carrier concentration in BP and MoS2 increases with increasing temperature. The minority carrier lifetime of BP/MoS2 p-n diodes also increases with increasing temperature.

Conflict of Interest: The authors declare no competing financial interests.

Acknowledgements: This research project was funded by Michigan State University and National Natural Science Foundation of China (11734016). The device fabrication was done in the Keck Microfabrication Facility (KMF) of Michigan State University. The authors would like to thank Dr. Baokang Bi for helpful discussions regarding the fabrication process.

Supporting Information Available: Electrical characterization of the Au/p+-Si bottom electrode (S1); Optical microscope and AFM images of vertical BP/MoS2 heterojunction diodes (S2); Optical microscope and AFM images of lateral BP/MoS2 heterojunction 14 ACS Paragon Plus Environment

Page 15 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

diodes (S3); Linear scale I-V characteristics of vertical and lateral BP/MoS2 heterojunction p-n diodes (S4). This material is available free of charge via the Internet at http://pubs.acs.org.

REFERENCES 1. Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Zhang, Y.; Dubonos, S. V.; Grigorieva, I. V.; Firsov, A. A. Electric Field Effect in Atomically Thin Carbon Films. Science 2004, 306, 666-669. 2. Li, X.; Cai, W.; An, J.; Kim, S.; Nah, J.; Yang, D.; Piner, R.; Velamakanni, A.; Jung, I.; Tutuc, E.; Banerjee, S. K.; Colombo, L.; Ruoff, R. S. Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils. Science 2009, 324, 1312-1314. 3. Mak, K. F.; Lee, C.; Hone, J.; Shan, J.; Heinz, T. F. Atomically Thin MoS2: A New Direct-Gap Semiconductor. Phys. Rev. Lett. 2010, 105, 136805. 4. Fang, H.; Chuang, S.; Chang, T. C.; Takei, K.; Takahashi, T.; Javey, A. High-Performance Single Layered WSe2 p-FETs with Chemically Doped Contacts. Nano Lett 2012, 12, 3788-3792. 5. Wi, S.; Kim, H.; Chen, M.; Nam, H.; Guo, L. J.; Meyhofer, E.; Liang, X. Enhancement of Photovoltaic Response in Multilayer MoS2 Induced by Plasma Doping. ACS Nano 2014, 8, 5270-5281. 6. Li, L.; Yu, Y.; Ye, G. J.; Ge, Q.; Ou, X.; Wu, H.; Feng, D.; Chen, X. H.; Zhang, Y. Black Phosphorus Field-Effect Transistors. Nat. Nanotechnol. 2014, 9, 372-377. 7. Koenig, S. P.; Doganov, R. A.; Schmidt, H.; Castro Neto, A. H.; Özyilmaz, B. Electric Field Effect in Ultrathin Black Phosphorus. Appl. Phys. Lett. 2014, 104, 103106. 8. Desai, S. B.; Madhvapathy, S. R.; Sachid, A. B.; Llinas, J. P.; Wang, Q.; Ahn, G. H.; Pitner, G.; Kim, M. J.; Bokor, J.; Hu, C.; Wong, H.-S. P.; Javey, A. MoS2 Transistors with 1-Nanometer Gate Lengths. Science 2016, 354, 99-102. 15 ACS Paragon Plus Environment

ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

9. Radisavljevic, B.; Radenovic, A.; Brivio, J.; Giacometti, V.; Kis, A. Single-Layer MoS2 Transistors. Nat. Nanotechnol. 2011, 6, 147-150. 10. Xia, F.; Wang, H.; Jia, Y. Rediscovering Black Phosphorus as an Anisotropic Layered Material for Optoelectronics and Electronics. Nat. Commun. 2014, 5, 4458. 11. Das, S.; Chen, H. Y.; Penumatcha, A. V.; Appenzeller, J. High Performance Multilayer MoS2 Transistors with Scandium Contacts. Nano Lett 2013, 13, 100-105. 12. Li, L.; Engel, M.; Farmer, D. B.; Han, S.-J.; Wong, H.-S. P. High-Performance p-Type Black Phosphorus Transistor with Scandium Contact. ACS Nano 2016, 10, 4672-4677. 13. Miao, J.; Zhang, S.; Cai, L.; Scherr, M.; Wang, C. Ultrashort Channel Length Black Phosphorus Field-Effect Transistors. ACS Nano 2015, 9, 9236-9243. 14. Buscema, M.; Groenendijk, D. J.; Blanter, S. I.; Steele, G. A.; van der Zant, H. S.; Castellanos-Gomez, A. Fast and Broadband Photoresponse of Few-Layer Black Phosphorus Field-Effect Transistors. Nano Lett 2014, 14, 3347-3352. 15. Lopez-Sanchez, O.; Lembke, D.; Kayci, M.; Radenovic, A.; Kis, A. Ultrasensitive Photodetectors Based on Monolayer MoS2. Nat. Nanotechnol. 2013, 8, 497-501. 16. Miao, J.; Song, B.; Li, Q.; Cai, L.; Zhang, S.; Hu, W.; Dong, L.; Wang, C. Photothermal Effect Induced Negative Photoconductivity and High Responsivity in Flexible Black Phosphorus Transistors. ACS Nano 2017, 11, 6048-6056. 17. Liu, H.; Neal, A. T.; Zhu, Z.; Luo, Z.; Xu, X.; Tománek, D.; Ye, P. D. Phosphorene: An Unexplored 2D Semiconductor with a High Hole Mobility. ACS Nano 2014, 8, 4033-4041. 18. Wang, H.; Yu, L.; Lee, Y.-H.; Shi, Y.; Hsu, A.; Chin, M. L.; Li, L.-J.; Dubey, M.; Kong, J.; Palacios, T. Integrated Circuits Based on Bilayer MoS2 Transistors. Nano Lett 2012, 12, 4674-4680. 19. Radisavljevic, B.; Whitwick, M. B.; Kis, A. Integrated Circuits and Logic Operations Based on Single-Layer MoS2. ACS Nano 2011, 5, 9934-9938. 20. Lee, Y. T.; Kwon, H.; Kim, J. S.; Kim, H.-H.; Lee, Y. J.; Lim, J. A.; Song, Y.-W.; Yi, 16 ACS Paragon Plus Environment

Page 16 of 24

Page 17 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Y.; Choi, W.-K.; Hwang, D. K. Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P (VDF-TrFE) Polymer. ACS Nano 2015, 9, 10394-10401. 21. Bertolazzi, S.; Krasnozhon, D.; Kis, A. Nonvolatile Memory Cells Based on MoS2/Graphene Heterostructures. ACS Nano 2013, 7, 3246-3252. 22. Wang, J.; Zou, X.; Xiao, X.; Xu, L.; Wang, C.; Jiang, C.; Ho, J. C.; Wang, T.; Li, J.; Liao, L. Floating Gate Memory‐Based Monolayer MoS2 Transistor with Metal Nanocrystals Embedded in the Gate Dielectrics. Small 2015, 11, 208-213. 23. Miao, J.; Cai, L.; Zhang, S.; Nah, J.; Yeom, J.; Wang, C. Air-Stable Humidity Sensor Using Few-Layer Black Phosphorus. ACS Appl. Mater. Interfaces. 2017, 9, 10019-10026. 24. Perkins, F. K.; Friedman, A. L.; Cobas, E.; Campbell, P.; Jernigan, G.; Jonker, B. T. Chemical Vapor Sensing with Monolayer MoS2. Nano Lett 2013, 13, 668-673. 25. Cho, S. Y.; Lee, Y.; Koh, H. J.; Jung, H.; Kim, J. S.; Yoo, H. W.; Kim, J.; Jung, H. T. Superior Chemical Sensing Performance of Black Phosphorus: Comparison with MoS2 and Graphene. Adv. Mater. 2016, 28, 7020-7028. 26. Neamen, D. Semiconductor Physics and Devices. McGraw-Hill, Inc.: 2002. 27. Alivov, Y. I.; Özgür, Ü.; Doğan, S.; Johnstone, D.; Avrutin, V.; Onojima, N.; Liu, C.; Xie, J.; Fan, Q.; Morkoç, H. Photoresponse of n-ZnO/p-SiC Heterojunction Diodes Grown by Plasma-Assisted Molecular-Beam Epitaxy. Appl. Phys. Lett. 2005, 86, 241108. 28. Jariwala, D.; Marks, T. J.; Hersam, M. C. Mixed-Dimensional van der Waals Heterostructures. Nat. Mater. 2016, 16, 170-181. 29. Ye, L.; Li, H.; Chen, Z.; Xu, J. Near-Infrared Photodetector Based on MoS2/Black Phosphorus Heterojunction. ACS Photonics 2016, 3, 692-699. 30. Chen, P.; Xiang, J.; Yu, H.; Xie, G.; Wu, S.; Lu, X.; Wang, G.; Zhao, J.; Wen, F.; Liu, Z. Gate Tunable MoS2-Black Phosphorus Heterojunction Devices. 2D Materials 2015, 2, 034009. 31. Cheng, R.; Li, D.; Zhou, H.; Wang, C.; Yin, A.; Jiang, S.; Liu, Y.; Chen, Y.; Huang, Y.; 17 ACS Paragon Plus Environment

ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Duan, X. Electroluminescence and Photocurrent Generation from Atomically Sharp WSe2/MoS2 Heterojunction p-n Diodes. Nano Lett 2014, 14, 5590-5597. 32. Li, M.-Y.; Shi, Y.; Cheng, C.-C.; Lu, L.-S.; Lin, Y.-C.; Tang, H.-L.; Tsai, M.-L.; Chu, C.-W.; Wei, K.-H.; He, J.-H. Epitaxial Growth of a Monolayer WSe2-MoS2 Lateral pn Junction with an Atomically Sharp Interface. Science 2015, 349, 524-528. 33. Roy, T.; Tosun, M.; Cao, X.; Fang, H.; Lien, D.-H.; Zhao, P.; Chen, Y.-Z.; Chueh, Y.-L.; Guo, J.; Javey, A. Dual-Gated MoS2/WSe2 van der Waals Tunnel Diodes and Transistors. ACS Nano 2015, 9, 2071-2079. 34. Li, D.; Wi, S.; Chen, M.; Ryu, B.; Liang, X. Nanoimprint-Assisted Shear Exfoliation Plus Transfer Printing for Producing Transition Metal Dichalcogenide Heterostructures. J. Vac. Sci. Technol., B 2016, 34, 06KA01. 35. Lin, Y.-C.; Chang, C.-Y. S.; Ghosh, R. K.; Li, J.; Zhu, H.; Addou, R.; Diaconescu, B.; Ohta, T.; Peng, X.; Lu, N. Atomically Thin Heterostructures Based on Single-Layer Tungsten Diselenide and Graphene. Nano Lett 2014, 14, 6936-6941. 36. Gao, A.; Liu, E.; Long, M.; Zhou, W.; Wang, Y.; Xia, T.; Hu, W.; Wang, B.; Miao, F. Gate-Tunable Rectification Inversion and Photovoltaic Detection in Graphene/WSe2 Heterostructures. Appl. Phys. Lett. 2016, 108, 223501. 37. Roy, T.; Tosun, M.; Hettick, M.; Ahn, G. H.; Hu, C.; Javey, A. 2D-2D Tunneling Field-Effect Transistors Using WSe2/SnSe2 Heterostructures. Appl. Phys. Lett. 2016, 108, 083111. 38. Roy, K.; Padmanabhan, M.; Goswami, S.; Sai, T. P.; Ramalingam, G.; Raghavan, S.; Ghosh, A. Graphene-MoS2 Hybrid Structures for Multifunctional Photoresponsive Memory Devices. Nat. Nanotechnol. 2013, 8, 826-830. 39. Myoung, N.; Seo, K.; Lee, S. J.; Ihm, G. Large Current Modulation and Spin-Dependent Tunneling of Vertical Graphene/MoS2 Heterostructures. ACS Nano 2013, 7, 7021-7027. 40. Wi, S.; Chen, M.; Nam, H.; Liu, A. C.; Meyhofer, E.; Liang, X. High Blue-Near 18 ACS Paragon Plus Environment

Page 18 of 24

Page 19 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Ultraviolet

Photodiode

Response

of

Vertically

Stacked

Graphene-MoS2-Metal

Heterostructures. Appl. Phys. Lett. 2014, 104, 232103. 41. Deng, Y.; Luo, Z.; Conrad, N. J.; Liu, H.; Gong, Y.; Najmaei, S.; Ajayan, P. M.; Lou, J.; Xu, X.; Ye, P. D. Black Phosphorus-Monolayer MoS2 van der Waals Heterojunction p-n Diode. ACS Nano 2014, 8, 8292-8299. 42. Yu, W. J.; Liu, Y.; Zhou, H.; Yin, A.; Li, Z.; Huang, Y.; Duan, X. Highly Efficient Gate-Tunable Photocurrent Generation in Vertical Heterostructures of Layered Materials. Nat. Nanotechnol. 2013, 8, 952-958. 43. Yu, W. J.; Li, Z.; Zhou, H.; Chen, Y.; Wang, Y.; Huang, Y.; Duan, X. Vertically Stacked Multi-Heterostructures of Layered Materials for Logic Transistors and Complementary Inverters. Nat. Mater. 2013, 12, 246-252. 44. Wood, J. D.; Wells, S. A.; Jariwala, D.; Chen, K.-S.; Cho, E.; Sangwan, V. K.; Liu, X.; Lauhon, L. J.; Marks, T. J.; Hersam, M. C. Effective Passivation of Exfoliated Black Phosphorus Transistors against Ambient Degradation. Nano Lett 2014, 14, 6964-6970. 45. Lee, C.; Yan, H.; Brus, L. E.; Heinz, T. F.; Hone, J.; Ryu, S. Anomalous Lattice Vibrations of Single-and Few-Layer MoS2. ACS Nano 2010, 4, 2695-2700. 46. Yang, H.; Heo, J.; Park, S.; Song, H. J.; Seo, D. H.; Byun, K.-E.; Kim, P.; Yoo, I.; Chung, H.-J.; Kim, K. Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier. Science 2012, 336, 1140-1143. 47. Sze, S. M.; Ng, K. K. Physics of Semiconductor Devices. John wiley & sons: 2006.


ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Figure 1

Figure 1. Fabrication procedure and characterization of vertically and laterally stacked BP/MoS2 heterojunction p-n diodes. (a) Schematic diagrams illustrating the fabrication procedure of vertically stacked BP/MoS2 p-n diodes. (b) Optical microscope images showing a representative vertical BP/MoS2 p-n junction diode after each fabrication step. Scale bar: 10 µm. (c, d) Ambient stability study of (c) vertically and (d) laterally stacked BP/MoS2 diodes. The scale bar for panels c (i) and d (i) is 10 µm. The scale bar for panels c (ii), (iii) and d (ii) and (iii) is 5 µm. (e) Raman spectra of MoS2, BP, and BP/MoS2 heterostructure.


Page 20 of 24

Page 21 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Figure 2

Figure 2. Comparison of vertically stacked devices with BP, MoS2, and BP/MoS2 heterostructure. Optical microscope images, AFM images, and electrical characteristics of (a) Au-BP-Au, (b) Au-MoS2-Au, and (c) Au-BP-MoS2-Au vertically stacked devices. The scale bar for panels a (i), b (i), and c (i) is 10 µm. The scale bars for panels a (ii), b (ii), and c (ii) are 7 µm, 5 µm, and 5 µm, respectively. (d) Schematic energy band diagrams of the BP/MoS2 heterojunction with (i) zero bias, (ii) forward bias, and (iii) reverse bias.


ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Figure 3

Figure 3. Comparison of vertical and lateral BP/MoS2 heterostructure p-n junction diodes. (a) I-V curves of vertical and lateral BP/MoS2 p-n diodes. Inset: Semi-logarithmic scale plot of the same I-V curves. (b) Schematic diagram showing the simplified device model of the lateral and vertical BP/MoS2 p-n junction diodes, where Rj represents the junction resistance of the BP/MoS2 p-n junction; Rom and Rob correspond to the MoS2 and BP resistance in the overlap region; Rsm and Rsb represent the MoS2 and BP series resistance outside the overlap region; and Rcm and Rcb are the contact resistance between MoS2 or BP and the gold electrode. (c, d) Ambient stability study of (c) vertical and (d) lateral BP/MoS2 heterojunction p-n diodes. 22 ACS Paragon Plus Environment

Page 22 of 24

Page 23 of 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Figure 4

Figure 4. Temperature-dependent electrical characteristics of a vertical BP/MoS2 heterojunction diode. (a) I-V characteristic of a representative vertical BP/MoS2 p-n diode measured at a temperature of 180 K. The inset is its corresponding semi-logarithmic scale curve. (b) Device ideality factor determined from the slope of the semi-logarithmic graph of device forward-bias current. (c) Reverse bias I-V characteristics measured at different temperatures from 260 K to 100 K. (d) The ln(I/T2) versus q/kBT plot for extracting the potential barrier height at the BP/MoS2 junction.


ACS Nano

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 24 of 24

Figure 5

Figure 5. TCAD simulations of vertical BP/MoS2 heterojunction p-n diodes. (a) Simulated semi-logarithmic scale I-V characteristics of a vertical BP/MoS2 p-n diode. The inset shows its linear scale I-V curve. (b) The ln(I/T2) versus q/kBT plots for extracting

the

barrier

height

at

the

BP/MoS2

junction.

Inset:

Simulated

temperature-dependent I-V characteristics under reverse bias. (c) Simulated electric field contour plot for the vertical diode.


Vertically Stacked and Self-Encapsulated van der Waals

Recommend Documents