Dual-Gate Black Phosphorus Field-Effect Transistors with Hexagonal

Subscriber access provided by READING UNIV

Article

Dual-gate black phosphorus field-effect transistors with hexagonal boron nitride as dielectric and passivation layer Hyun-Soo Ra, A-Young Lee, Do-Hyun Kwak, Min-Hye Jeong, and Jong-Soo Lee ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b16809 • Publication Date (Web): 19 Dec 2017 Downloaded from http://pubs.acs.org on December 20, 2017

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a free service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are accessible to all readers and citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

ACS Applied Materials & Interfaces is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Applied Materials & Interfaces

Dual-gate black phosphorus field-effect transistors with hexagonal boron nitride as dielectric and passivation layer Hyun-Soo Raa†, A-Young Leea†, Do-Hyun Kwaka, Min-Hye Jeonga, Jong-Soo Leea* a

Department of Energy Science and Engineering, DGIST, Daegu, 42988, Republic of Korea

ABSTRACT Two-dimensional black phosphorus (BP) has attracted much attention recently because of its applicability in high-performance electronic and optoelectronic devices. BP field-effect transistors (FETs) with a tunable bandgap (0.3–1.5 eV) have demonstrated a high on-off current ratio and a high hole mobility with ambipolar behavior in global-gated devices. However, the local-gated BP FETs for integrated circuits have been reported with only p-type behavior and a low on-current compared with global-gated BP FETs. Furthermore, BP, which is not stable in air, forms sharp spikes on the surfaces when exposed to humid air. This phenomenon plays a role in accelerating the degradation of electrical properties of BP devices, which can occur even within a day. In this Letter, we first demonstrate the origin of transport limitations of local-gated BP FETs by comparing the transport properties of hexagonal boron nitride (h-BN)-based device architectures with those of a bottom-gated BP FET on a Si/SiO2 substrate. By using h-BN as passivation and dielectric layers, BP FETs with a low gate operation were fabricated with two different transistor geometries: top-gated and bottom-gated FETs. The highest mobility extracted from the global-gated BP FETs was 249 cm2V-1s-1 with a subthreshold swing of 848 mV dec-1.

ACS Paragon Plus Environment

1

ACS Applied Materials & Interfaces 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 24

KEYWORDS: Black phosphorus, h-BN, Dielectric layer, Aging effect, Global and Local Gate, Mobility, Subthreshold slope. 1. INTRODUCTION Black phosphorus (BP) is a novel 2D material with a tunable bandgap ranging from 0.3 eV (bulk) to 1.5 eV (monolayer) depending on the number of layers.1-7 Thin layers of BP nanosheets have a high hole mobility greater than 500 cm2 V-1 s-1 even at high frequencies (on the order of 12 GHz) along the armchair direction.8-9 A dual-gated BP FET based on an oxide dielectric layer (Al2O3) has been reported to exhibit good functionality as logic inverters.10-12 In addition, BP can be a good candidate for optoelectronics applications (infrared range) owing to their direct band structure, which has efficient photoresponse in all layers, even in bulk.13-17 However, exfoliated atomically thin BP nanosheets are not air-stable under ambient conditions. When BP nanosheets are exposed to air, sharp spikes related to P-O bonding are easily formed on their surface structures.6, 18-22 The spikes formed on the surfaces of BP can significantly degrade electron and hole mobility as well as the on-off current ratio owing to increase in band gap and Fermi-level shift induced by surface oxidation.18, 21, 23 To maintain the quality of BP, a number of recent studies have proposed various protective layers to improve its stability for device performances.18-19, 23-24 To improve the performance of BP FETs with high mobility, high switching speed, and lower applied gate bias, high-k dielectric oxide materials (HfO2, Al2O3, and ZrO2) have been normally reported as the dielectric and passivation layers in top-gate FET structures.11-12, 21, 25-33 However, BP devices encapsulated by high-k oxide materials are not suitable for flexible device applications owing to their weak mechanical bending duration. Critical problems have remained unsolved in BP nanosheets for high-quality, flexible, and reliable FET application. In general, local-gated BP FETs in the upper side of dual-gated FETs


2

Page 3 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


have been reported only with p-type behaviors and low on-off current modulation compared with global-gated BP FETs. 9-11, 25, 34 To understand the origin of the limitation on charge transfer, we compared the charge-transfer characteristics of global-gated BP FETs on Si/SiO2 substrates with those of a local-gated BP FET using h-BN as the dielectric layer.

2. EXPERIMENTAL SECTION 2.1 DFT Calculation: All geometric relaxations for our models were performed by density function theory (DFT) calculations. The van der waals interactions were considered by the vdWDF level with the optB88 exchange fuctional. Projector augmented wave (PAW) pseudopotentials as implemented in VASP were used for describing the interactions between ions and electrons, and the exchange-correlation energy of electrons was described by using the generalised gradient approximation (GGA) with the Perdew–Burke–Ernzerhof functionals (PBE). The Kohn–Sham orbitals were expanded on a plane-wave basis set with a cutoff energy of 400 eV. All atoms were fully relaxed until Hellmann–Feynman force was less than 0.01 eV / Å To integrate the Brillouin zone, 3×1×1 gamma-point mesh was used for hybrid models of BP/SiO2 (100) surface and BP/h-BN. 2.2 2D Materials Information: Single crystal Black Phosphorus (HQ graphene, CAS# 772314-0), h-BN (HQ graphene, CAS#10043-11-5) and MoS2 (SPI supplies, CAS# 1317-33-5) were exfoliated by 3M magic tape. We used large area exfoliation method which first maintain under 300 nm SiO2/Si attached with 3M tape at 100oC for 2min and detached 3M tape from SiO2/Si substrate during cooling down at room temperature. The number of 2D layers was distinguished through optical contrast by optical microscopy (Nikon eclipse LV100).


3


Page 4 of 24

2.3 Device Fabrication and Characterization Detailed the process of device fabrication and characterization were described in supporting informations. 2.4 AFM and Raman Spectroscopy: As exfoliated BP was cleaned into warm acetone and IPA (60oC, 5min) for removal of tape residue, respectively. Height of BP flake was measured by AFM (Parks systems, NX10). The BP sample was repeatedly measured for checking aging effect depending on the thickness exposed at air with humidity. The cross-section line profile of AFM mapping image demonstrated all-2D material thickness. A Raman spectrometer (Thermo scientific, NICOLET ALMECA XR) equipped with a 532-nm laser was used to demonstrate material’s Raman shift depending on the number of 2D layers. 1% of laser power intensity was used for excitation power because BP is very weak to high power laser.

3. RESULTS AND DISCUSSION As shown in Fig. 1, we first investigated the differences between the interface structures of BP/SiO2 and BP/h-BN through DFT calculations. In Fig. 1(a), the dangling bonds of oxygen atoms at the BP/SiO2 interface give rise to a P-O bonding, which can be attributed to the breakage of Si-O bonds by lattice mismatch in hybrid BP/SiO2. Zhu et al. reported the formation of phosphorus oxide at the interface between Al2O3 and BP at a deposition temperature of 200 °C.35 Moreover, the dangling bonds of oxygen atoms on the SiO2 (100) surface cause significant lattice strain in the BP structure. Surface degradation due to the formation of phosphorus oxide can result in severe variations in the electronic structure and charge transport of BP. In Fig. 1(b), however, BP nanosheets on h-BN still retain their original crystal structures regardless of a slight


4

Page 5 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


lattice strain after the hybridization of the two materials, maintaining an interlayer distance between BP and h-BN of 3.24 Å. The large interlayer spacing between BP and h-BN is due to weak interaction by the van der Waals forces, while the short P-O bonding length of 1.68 Å at the BP/SiO2 interface yields strong interaction in Fig. 1(a). In general, the process of charge transport and accumulation in FETs occurs at the interface between the gate dielectric and channel materials; therefore, the properties of these interfaces and the dielectric materials significantly influence on the characteristics of the FET device. As shown in Fig. 1(c), we compared the capacitance (10-3 F) between h-BN and SiO2 dielectric layers as a function of the dielectric-layer thickness to investigate efficient gating for optimal FET operation at a low gate voltage. The thickness of h-BN ranged from 0 nm to 300 nm for comparison with the thickness of SiO2 used in this study. 25, 36-41 The charge accumulations in FETs, which is the amount of induced charges per applied Vg, are mainly characterized by their gate dielectric capacitance (Cox) per unit area, Cox = εrε0/d, where ε0 is the permittivity in a vacuum and d is the thickness of the dielectric layer, and εr is the dielectric constant. The proper accumulation of charges in the FET channel can be controlled by either reducing the dielectriclayer thickness or using the dielectric materials with a higher εr. Although the dielectric constants of h-BN and SiO2 are similar at 3.9 and 3, the capacitance of the 30-nm-thick h-BN layer used in this study is significantly lower than those of a 300-nm-thick SiO2 dielectric layer, which corresponded with the compensation value γ of 0.769 in the inset plot. Therefore, thin h-BN can plays an important role as a dielectric layer in high performance BP FET devices that can operate at a low gate voltages. For a high-performance dual-gated BP FET, as schematically shown in Fig. 2(a), we designed a dual-gate BP FET with SiO2 and h-BN as dielectric layers, respectively, with the bottom part of


5


Page 6 of 24

the device having a global gate and the top part having a local gate. To realize a dual-gated BP FET, exfoliated thin BP layers of 10–20 nm thickness were transferred onto a Si substrate. First, a global-gated BP FET was fabricated at the bottom using electron-beam lithography (EBL). The surface of the BP FET was encapsulated with h-BN layer using a wet transfer method.17, 19, 24-25 As shown an optical image of the dual-gated BP FET in Fig. 2(b), local-gate electrodes were fabricated on the h-BN layer through a second EBL. Fig. 2(c) shows the global-gated BP FET fabricated on h-BN as a dielectric layer instead of SiO2 at the bottom part to confirm the role of h-BN in BP FETs. Finally, a global-gated BP FET completely covered with h-BN as the passivation layers were fabricated as shown in Fig. 2(d). The detailed fabrication method is explained in Fig. S1. The Raman spectra as shown in Fig. 2(e) are clearly demonstrated on the few layers of BP by comparing the intensity of Ag1 with the Si peak.13, 42 The Raman spectra of the BP covered with h-BN show an h-BN E2g peak as well as the typical Ag1, B2g, and Ag2 peaks observed in the BP crystal. Fig. S2 (a-c) shows the transfer curves of BP FET fabricated on the SiO2 dielectric layer without h-BN passivation layer measured as a function of gate bias ranging from -90VG to 90VG at a fixed drain-source(VDS) voltages of 0.1 to 0.3VDS. The transfer curves of ID-VG show typically ambipolar behavior, which shows a high hole mobility of 199 cm2V-1s-1 and a high onoff current ratio of 105. The hole mobility was calculated by the mobility equation µ = Lgm/(WCoxVD), where L is the channel length, W is the width of the active area, gm is the transconductance, Cox is the dielectric capacitance of 1.15 × 10-4 F m-2 in SiO2 (Cox = εrε0/d, ε0 = 3.9, d = 300 nm), and VDS = 0.3 V. As shown in Fig. 3 (a) and Fig. S2 (d-f), the BP FET encapsulated with h-BN achieves the enhanced electron conductivity, fewer charge traps, and a clear neutral valley due to the surface dielectric screening.19, 21, 24, 43 The output curves of the BP


6

Page 7 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


FET on SiO2 shown in Fig. 3(b) show an ohmic transfer behavior, which means the contact barriers between Ti/Au electrodes and BP nanosheets were not dominant for the operation of BP FET.1, 12, 44 In Fig. 3(c), the transfer curve of the local-gated BP FET measured from -3Vg to 3Vg shows only p-type behavior. The low-gate operation voltage of a FET requires a strong capacitive coupling between the channel and the gate dielectric as extracted from Fig. 1(c). Although the depletion current of the local-gated BP FET (10-10 A) was similar to that of the global-gated BP FET, the on-current of the local-gated BP FET was significantly degraded to 10-6 A compared to 10-5 A of the global-gated BP FET. The hole mobility extracted from the local-gated BP FET was 34.54 cm2V-1s-1. The degradation of charge transport in the local-gated BP FET was confirmed through the 8th iteration as summarized in Table S1. The degradation of charge transport in the local-gated FETs has been often reported in other 2-D FET devices using different types of the dielectric materials such as Al2O3 and h-BN.10-11, 25 The output curves of Fig. 3(d) also indicate that the asymmetric source-drain contact resistance was dominant in the local-gated BP FET. The positive sweep of VD from 0 to 0.3 VD shows linear behavior by ~1.7 µA at 0.3VD and -3 VTG, while the negative sweep of VD from 0 to -0.3 VD shows saturation behavior from a low drain voltage of -0.05 VD, which reaches ~0.12 µA at -0.3 VD as a function of -3 VTG. In the hole-enhanced gate modulation, the hole current was dominant at a positive drain voltage. Conversely, in the electron-enhanced gate modulation (inset output curve), the electron current was dominant at a negative drain voltage. Although we fabricated a balanced contact resistance electrodes in the local-gated architecture, the charge transport limitations in the transfer curve would not be solved, as clearly demonstrated in Fig. S3. To overcome the limitation of the local-gated FET, as depicted in Fig. 2(d), we fabricated a global-gated BP FET


7


Page 8 of 24

on h-BN. The transfer curve of Fig. 3(e) shows typically ambipolar behavior corresponding to that of the global-gated BP FET on SiO2. The hole mobility extracted from the global-gated BP FET on h-BN reached a high hole mobility of 181 cm2V-1s-1 and an on-off current ratio of 2 × 103. As shown in Fig. S4, the highest hole mobility was recorded at 249 cm2V-1s-1 in a thick BP FET with an on-off current ratio of 8 x 102. The two factors have a trade-off relationship depending on the BP thickness (Fig. S4).7, 12, 44 The applied gate bias in the global-gated BP FET with h-BN as a dielectric layer was dramatically decreased owing to the efficient gate capacitance of h-BN as extracted from Fig. 1(c). The output curves of this FET showed a perfectly linear dependence at both sides from -0.3 VD to 0.3 VD. This behavior is similar to that of the global-gated BP FET on SiO2. Therefore, the contact resistance between BP and electrodes (Ti/Au) was not dominant in FET operation. The gate leakage currents of all structures are summarized in Fig. S5. We also compared the subthreshold swing (S) of the devices extracted by dVG/d (log ID).25-26, 45 In general, large S values of >1 V per decade were expected from FETs with thick gate dielectric layers. We also observed from the global-gated BP FET fabricated on the SiO2 substrate with a high S value of 3789 mV per decade (Fig. 3(a)). However, the BP devices forming the interfaces with h-BN as shown in Fig. 3(c) and (e) show much steeper S values of 204 mV per decade for the local-gated device and 848 mV per decade for the globalgated device, respectively. The results are agree well with the improved interface quality between BP and h-BN substrates as we discussed in Fig. 1. Therefore, the significant mobility degradation in the local-gated devices was not originated from the contact problems between BP and electrodes, and formation of a high-quality dielectric-BP interfaces. To understand the limitation of charge transport in the local-gated architecture, we observed a cross-section TEM image of the local- and the global-gated FET structures prepared using a


8

Page 9 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


focused ion beam (FIB). In Fig. S6, the TEM images and mapping profiles show a clear stacking building blocks at each layers of devices. However, the step pulley of the source-drain top contact electrodes formed a void region of about 160-nm thickness on BP layers as shown in Fig. 4(a). Based on the TEM images, we drew a structural model in Fig. 4(b). The model consists of a contact, a void length on the BP surface, and a metal-insulator-semiconductor (MIS) region.46 The three types of regions have different channel resistances of BP, which results from a disproportion of an electric-field-induced from the local gate. The MIS area of BP has a controllable charge density by using the induced-electric-field via h-BN. Therefore, we can consider the BP channel of the MIS region with variable resistance, which is depicted in green color in Fig. 4(b). Another void region of BP is the non-vertical capacitance structure, which is not controllable by an induced electric field from the gate electrode. Furthermore, the BP channel of the contact area is cut off from the induced-electric-field. Therefore, the BP channels between the void and contact area are intrinsic, which implies a p-type rich semiconductor under the locally induced-electric-field. At following structural model, we assumed the intrinsic BP channel as a black colored resistance symbol in Fig. 4(b). The disproportion of charge density between the intrinsic and variable resistance could form band pinning by the charge diffusion. As a representative symbol of the barrier between semiconductors, we describe the interface phenomenon as the diode symbol at a boundary of a charge disproportion. Following this model, we designed the band alignment models with three different regions of the contact, void region, and MIS region to understand the mechanism of charge transfer. Fig. 4(c) shows the band alignment of pristine BP in the FET structure at 0 VG.12, 15, 26, 44 As the gate bias is applied to the MIS region, such as VG < 0 and VG > 0, we should consider a variable charge density in the channels depending on the three different regions. In particular, the contact


9


Page 10 of 24

and void regions have a high contact barrier of ФB-contact, such as intrinsic BP-Ti contact resistance, in the ranges of applied gate bias. Fig. 4(d) shows the band alignment for the electron transport channel at VG > 0. The BP channel between the contact void and MIS region has a barrier of ФB induced by band pinning effect, which corresponded with the Fermi-level dislocation among the BP channels. The formed ФB-electron could play the role of electron rectification in the local-gated BP FET. The only p-type transfer curve and output curve of Fig. 3(c)-(d) explicitly support this rectification mechanism. Table S1 summarizes the reproducible phenomenon in local-gated BP FET. Reversely, Fig. 4(e) demonstrated ФB-hole also exists at the Fermi-level dislocation boundary of the hole transport channel at VG < 0. The rectification phenomenon could occur in the opposite of the electron transport direction. The limitation of the maximum enhanced hole current in Fig. 3(c) corresponded with the rectification mechanism. Also, the contact area with disproportion charge density contributed the unbalance of charge-transfer direction. The asymmetric output curves in Fig. 3(d) corresponded with the prominently different channel resistance formed by ФB-electron and ФB-hole. The asymmetric behavior of output curves also clearly followed each different forward bias directions depending on the type of the major charge carriers in Fig. 3(d) and their inset. To prove the rectification mechanism, we systematically studied the FET performance of graphene and MoS2 fabricated on the SiO2 and h-BN as dielectric layers with the two different device architectures. First, we fabricated the dual-gated graphene FETs through h-BN transfer and the local-gate deposition as shown in Fig. 5(a). In the bottom-gated graphene device on the SiO2 layer, the transfer curve of graphene FETs was measured as a function of bottom gate bias


10

Page 11 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


from -90 to 90 VG at 0.1, 0.5 and 1 VD, respectively. Fig. 5(b) shows a clear ambipolar behavior and symmetry curves of the electron-hole side as the neutral point at 0 VG. The calculated electron and hole mobility is 2360 cm2 V-1s-1 and 2200 cm2 V-1s-1, respectively. On the other hand, Fig. 5(c) shows the local-gated graphene FET performance on the h-BN dielectric layer. The neutral point was shifted toward positive direction due to partial doping induced by residual oxygen exposure during the h-BN wet transfer process. However, the current rectification effect observed in the previous local-gated BP FET was hardly affected in graphene FET devices. The mobility of the local-gated graphene FET due to high capacitance effect of the thin h-BN layer (30 nm) was significantly increased as 4720 cm2 V-1s-1 and 4220 cm2 V-1s-1 for electron and hole, respectively, despite the lower applied gate voltages. We also fabricated a dual-gated MoS2 FET as shown in Fig. 5(d). In the global-gated MoS2 FET fabricated on the SiO2, the device demonstrated the n-type enhanced semiconductor characteristics as the positive gate bias was applied from 0 VG to 90VG. The calculated electron mobility is 17.5 cm2 V-1s-1, which was comparable with previously reported results. 47-50 However, the local-gated MoS2 FET on h-BN shows a significant current rectification effect. The current value (3.5 µA) measured at the local-gated MoS2 FET tends to decrease by almost one order of magnitude compared to the value (35 µA) measured at the global-gated MoS2 FET. The electron mobility of 17.5 cm2 V-1s-1 calculated in the global-gated FET was dramatically reduced to 9.2 cm2 V-1s-1 in the local-gated FET. As a result, the disadvantages of the local-gated FET system seems to predominate in semiconductors with band gaps. To overcome these limitations, selective contact doping and line contact methods should be studied in detail. Optimization of the dual-gated FETs and 2D stack FETs is an essential goal for real application. Finally, we tested the stability of BP FET with h-BN as passivation layer as shown in Fig. S7. The hole mobility of


11


Page 12 of 24

non-passivated BP FET on the SiO2 (red dots) was abruptly decreased to almost 99% as 0.43 cm2·V-1·s-1 within 4 days due to the degradation of active area by phosphoric acid. However, the hole mobility (green dots) of the BP FET passivated with h-BN was completely retained as long as one week without degradation of device characteristics.

4. CONCLUSIONS In summary, the global- and the local-gated device geometries were fabricated for observing the electrical properties of the BP FET on the SiO2 and h-BN dielectric layers. By using h-BN as passivation and dielectric layers, BP FETs with a low gate operation were fabricated with two different transistor geometries: top-gated and bottom-gated FETs. The highest hole mobility extracted from the global-gated BP FETs was 249 cm2V-1s-1 with a subthreshold swing of 848 mV dec-1. Based on the band alignment model, the limitation of the charge transport in the localgated geometry was originated from the induced unbalance charge due to screening out the effect of the applied gate bias in the void and contact region. The mobility of the h-BN-protected BP FET was completely retained as long as one week without changing device characteristics in air. The study of various architectures of 2D FET with h-BN will open avenues for flexible electronics as new-generation device application. ASSOCIATED CONTENT Supporting Information. This material is available free of charge via the Internet at http://pubs.acs.org.


12

Page 13 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Detailed device fabrication, Surface dielectric screening effect using h-BN, Schottky barrier study in local gate architecture, high on-off ratio BP device, stable gate leakage test, BP FET stability test, Cross sectional TEM mapping images.

AUTHOR INFORMATION Corresponding Author E-mail address : [email protected] ORCID Jong-Soo Lee : 0000-0002-3045-2206 †

Authors with equal contribution

ACKNOWLEDGEMENTS This work was supported by the Leading Foreign Research Institute Recruitment Program (Grant No. 2012K1A4A3053565) and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and future Planning (2017030044). We thank H. S. Jang and S. K. Jeon (CCRF DGIST) for discussions on the electron beam and photo-lithography system. Nano-device fabrication was performed at CCRF of DGIST.

REFERENCES 1.

Cai, Y.; Zhang, G.; Zhang, Y. W., Layer-dependent band alignment and work function

of few-layer phosphorene. Sci. Rep. 2014, 4, 6677.


13


2.

Page 14 of 24

Xia, F.; Wang, H.; Xiao, D.; Dubey, M.; Ramasubramaniam, A., Two-dimensional

material nanophotonics. Nat. Photonics 2014, 8 (12), 899-907. 3.

Wang, S.; Wang, X.; Warner, J. H., All Chemical Vapor Deposition Growth of MoS2:h-

BN Vertical van der Waals Heterostructures. ACS Nano 2015, 5, 5246-5254. 4.

Lin, J. D.; Han, C.; Wang, F.; Wang, R.; Xiang, D.; Qin, S.; Zhang, X.-A.; Wang, L.; Zhang,

H.; Wee, A. T. S.; Chen, W., Electron-Doping-Enhanced Trion Formation in Monolayer Molybdenum Disulfide Functionalized with Cesium Carbonate. ACS Nano 2014, 8 (5), 53235329. 5.

Liu, H.; Du, Y.; Deng, Y.; Ye, P. D., Semiconducting black phosphorus: synthesis,

transport properties and electronic applications. Chem. Soc. Rev. 2015, 44 (9), 2732-43. 6.

Castellanos-Gomez, A.; Vicarelli, L.; Prada, E.; Island, J. O.; Narasimha-Acharya, K. L.;

Blanter, S. I.; Groenendijk, D. J.; Buscema, M.; Steele, G. A.; Alvarez, J. V.; Zandbergen, H. W.; Palacios, J. J.; van der Zant, H. S. J., Isolation and characterization of few-layer black phosphorus. 2D Materials 2014, 1 (2), 025001. 7.

Li, L.; Yu, Y.; Ye, G. J.; Ge, Q.; Ou, X.; Wu, H.; Feng, D.; Chen, X. H.; Zhang, Y., Black

phosphorus field-effect transistors. Nat. Nanotechnol. 2014, 9 (5), 372-377. 8.

Chung, D. S.; Kim, Y. H.; Lee, J. S., Achieving high sensitivity in hybrid photodetectors

based on an organic single crystal and an inorganic nanocrystal array. Nanotechnology 2014, 25 (3), 035202. 9.

Wang, H.; Wang, X.; Xia, F.; Wang, L.; Jiang, H.; Xia, Q.; Chin, M. L.; Dubey, M.; Han, S.

J., Black phosphorus radio-frequency transistors. Nano lett. 2014, 14 (11), 6424-9. 10.

Kim, J. S.; Jeon, P. J.; Lee, J.; Choi, K.; Lee, H. S.; Cho, Y.; Lee, Y. T.; Hwang, D. K.; Im, S.,

Dual Gate Black Phosphorus Field Effect Transistors on Glass for NOR Logic and Organic Light Emitting Diode Switching. Nano lett. 2015. 11.

Lee, Y. T.; Kwon, H.; Kim, J. S.; Kim, H.-H.; Lee, Y. J.; Lim, J. A.; Song, Y.-W.; Yi, Y.; Choi,

W.-K.; Hwang, D. K.; Im, S., Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer. ACS Nano 2015, 9 (10), 10394-10401. 12.

Perello, D. J.; Chae, S. H.; Song, S.; Lee, Y. H., High-performance n-type black

phosphorus transistors with type control via thickness and contact-metal engineering. Nat.

Comm. 2015, 6, 7809. 13.

Favron, A.; Gaufres, E.; Fossard, F.; Phaneuf-L'Heureux, A. L.; Tang, N. Y.; Levesque, P.

L.; Loiseau, A.; Leonelli, R.; Francoeur, S.; Martel, R., Photooxidation and quantum confinement effects in exfoliated black phosphorus. Nat. Mater. 2015, 14 (8), 826-32.


14

Page 15 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


14.

Yuan, H.; Liu, X.; Afshinmanesh, F.; Li, W.; Xu, G.; Sun, J.; Lian, B.; Curto, A. G.; Ye, G.;

Hikita, Y.; Shen, Z.; Zhang, S. C.; Chen, X.; Brongersma, M.; Hwang, H. Y.; Cui, Y., Polarizationsensitive broadband photodetector using a black phosphorus vertical p-n junction. Nat.

Nanotechnol. 2015, 10 (8), 707-13. 15.

Buscema, M.; Groenendijk, D. J.; Blanter, S. I.; Steele, G. A.; van der Zant, H. S.;

Castellanos-Gomez, A., Fast and broadband photoresponse of few-layer black phosphorus field-effect transistors. Nano Lett. 2014, 14 (6), 3347-52. 16.

Buscema, M.; Island, J. O.; Groenendijk, D. J.; Blanter, S. I.; Steele, G. A.; van der Zant,

H. S.; Castellanos-Gomez, A., Photocurrent generation with two-dimensional van der Waals semiconductors. Chem. Soc. Rev. 2015, 44 (11), 3691-718. 17.

Youngblood, N.; Chen, C.; Koester, S. J.; Li, M., Waveguide-integrated black

phosphorus photodetector with high responsivity and low dark current. Nat. Photonics 2015,

9, 247-252. 18.

Wood, J. D.; Wells, S. A.; Jariwala, D.; Chen, K. S.; Cho, E.; Sangwan, V. K.; Liu, X.;

Lauhon, L. J.; Marks, T. J.; Hersam, M. C., Effective passivation of exfoliated black phosphorus transistors against ambient degradation. Nano lett. 2014, 14 (12), 6964-70. 19.

Doganov, R. A.; O'Farrell, E. C.; Koenig, S. P.; Yeo, Y.; Ziletti, A.; Carvalho, A.; Campbell,

D. K.; Coker, D. F.; Watanabe, K.; Taniguchi, T.; Castro Neto, A. H.; Ozyilmaz, B., Transport properties of pristine few-layer black phosphorus by van der Waals passivation in an inert atmosphere. Nat. Comm. 2015, 6, 6647. 20.

Pei, J.; Gai, X.; Yang, J.; Wang, X.; Yu, Z.; Choi, D. Y.; Luther-Davies, B.; Lu, Y., Producing

air-stable monolayers of phosphorene and their defect engineering. Nat. Comm. 2016, 7, 10450. 21.

Kim, J. S.; Liu, Y.; Zhu, W.; Kim, S.; Wu, D.; Tao, L.; Dodabalapur, A.; Lai, K.; Akinwande,

D., Toward air-stable multilayer phosphorene thin-films and transistors. Sci. Rep. 2015, 5, 8989. 22.

Yang, B.; Wan, B.; Zhou, Q.; Wang, Y.; Hu, W.; Lv, W.; Chen, Q.; Zeng, Z.; Wen, F.;

Xiang, J.; Yuan, S.; Wang, J.; Zhang, B.; Wang, W.; Zhang, J.; Xu, B.; Zhao, Z.; Tian, Y.; Liu, Z., Te-Doped Black Phosphorus Field-Effect Transistors. Adv. Mater. 2016, 28 (42), 9408-9415. 23.

Ryder, C. R.; Wood, J. D.; Wells, S. A.; Yang, Y.; Jariwala, D.; Marks, T. J.; Schatz, G. C.;

Hersam, M. C., Covalent functionalization and passivation of exfoliated black phosphorus via aryl diazonium chemistry. Nat. Chem. 2016, 8 (6), 597-602.


15


24.

Page 16 of 24

Chen, X.; Wu, Y.; Wu, Z.; Han, Y.; Xu, S.; Wang, L.; Ye, W.; Han, T.; He, Y.; Cai, Y.; Wang,

N., High-quality sandwiched black phosphorus heterostructure and its quantum oscillations.

Nat. Comm. 2015, 6, 7315. 25.

Avsar, A.; Vera-Marun, I. J.; Tan, J. Y.; Watanabe, K.; Taniguchi, T.; Castro Neto, A. H.;

Özyilmaz, B., Air-Stable Transport in Graphene-Contacted, Fully Encapsulated Ultrathin Black Phosphorus-Based Field-Effect Transistors. ACS Nano 2015, 9 (4), 4138-4145. 26.

Das, S.; Demarteau, M.; Roelofs, A., Ambipolar Phosphorene Field Effect Transistor.

ACS Nano 2014, 8 (11), 11730-11738. 27.

Illarionov, Y. Y.; Waltl, M.; Rzepa, G.; Kim, J. S.; Kim, S.; Dodabalapur, A.; Akinwande,

D.; Grasser, T., Long-Term Stability and Reliability of Black Phosphorus Field-Effect Transistors. ACS Nano 2016. 28.

Na, J.; Lee, Y. T.; Lim, J. A.; Hwang, D. K.; Kim, G.-T.; Choi, W. K.; Song, Y.-W., Few-

Layer Black Phosphorus Field-Effect Transistors with Reduced Current Fluctuation. ACS Nano 2014, 8 (11), 11753-11762. 29.

Radisavljevic, B.; Radenovic, A.; Brivio, J.; Giacometti, V.; Kis, A., Single-layer MoS2

transistors. Nat. Nanotechnol. 2011, 6 (3), 147-50. 30.

Chen, X.; Wu, Z.; Xu, S.; Wang, L.; Huang, R.; Han, Y.; Ye, W.; Xiong, W.; Han, T.; Long,

G.; Wang, Y.; He, Y.; Cai, Y.; Sheng, P.; Wang, N., Probing the electron states and metalinsulator transition mechanisms in molybdenum disulphide vertical heterostructures. Nat.

Comm. 2015, 6, 6088. 31.

Zhang, Y.; Ye, J.; Matsuhashi, Y.; Iwasa, Y., Ambipolar MoS2 thin flake transistors.

Nano Lett. 2012, 12 (3), 1136-40. 32.

Wang, H.; Yu, L.; Lee, Y. H.; Shi, Y.; Hsu, A.; Chin, M. L.; Li, L. J.; Dubey, M.; Kong, J.;

Palacios, T., Integrated circuits based on bilayer MoS2 transistors. Nano Lett. 2012, 12 (9), 4674-80. 33.

Movva, H. C. P.; Rai, A.; Kang, S.; Kim, K.; Fallahazad, B.; Taniguchi, T.; Watanabe, K.;

Tutuc, E.; Banerjee, S. K., High-Mobility Holes in Dual-Gated WSe2 Field-Effect Transistors.

ACS Nano 2015. 34.

Fang, H.; Chuang, S.; Chang, T. C.; Takei, K.; Takahashi, T.; Javey, A., High-performance

single layered WSe(2) p-FETs with chemically doped contacts. Nano lett. 2012, 12 (7), 378892. 35.

Zhu, H.; McDonnell, S.; Qin, X.; Azcatl, A.; Cheng, L.; Addou, R.; Kim, J.; Ye, P. D.;

Wallace, R. M., Al2O3 on Black Phosphorus by Atomic Layer Deposition: An in Situ Interface Study. ACS appl. mater. & inter. 2015, 7 (23), 13038-43.


16

Page 17 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


36.

Kim, S. M.; Hsu, A.; Park, M. H.; Chae, S. H.; Yun, S. J.; Lee, J. S.; Cho, D. H.; Fang, W.;

Lee, C.; Palacios, T.; Dresselhaus, M.; Kim, K. K.; Lee, Y. H.; Kong, J., Synthesis of large-area multilayer hexagonal boron nitride for high material performance. Nat. Comm. 2015, 6, 8662. 37.

Zou, X.; Huang, C. W.; Wang, L.; Yin, L. J.; Li, W.; Wang, J.; Wu, B.; Liu, Y.; Yao, Q.;

Jiang, C.; Wu, W. W.; He, L.; Chen, S.; Ho, J. C.; Liao, L., Dielectric Engineering of a Boron Nitride/Hafnium Oxide Heterostructure for High-Performance 2D Field Effect Transistors.

Adv. Mater. 2016, 28 (10), 2062-9. 38.

Roy, T.; Tosun, M.; Kang, J. S.; Sachid, A. B.; Desai, S. B.; Hettick, M.; Hu, C. C.; Javey,

A., Field-Effect Transistors Built from All Two-Dimensional Material Components. ACS Nano 2014, 8 (6), 6259-6264. 39.

Park, J.-H.; Park, J. C.; Yun, S. J.; Kim, H.; Luong, D. H.; Kim, S. M.; Choi, S. H.; Yang, W.;

Kong, J.; Kim, K. K.; Lee, Y. H., Large-Area Monolayer Hexagonal Boron Nitride on Pt Foil.

ACS Nano 2014, 8 (8), 8520-8528. 40.

Wang, L.; Meric, I.; Huang, P. Y.; Gao, Q.; Gao, Y.; Tran, H.; Taniguchi, T.; Watanabe, K.;

Campos, L. M.; Muller, D. A.; Guo, J.; Kim, P.; Hone, J.; Shepard, K. L.; Dean, C. R., OneDimensional Electrical Contact to a Two-Dimensional Material. Science 2013, 342 (6158), 614-617. 41.

Nicolas Petrone; Xu Cui; James Hone; Tarun Chari; Shepard, K., Flexible 2D FETs using

hBN dielectrics. IEEE 2015, 1981-1984. 42.

Tao, J.; Shen, W.; Wu, S.; Liu, L.; Feng, Z.; Wang, C.; Hu, C.; Yao, P.; Zhang, H.; Pang,

W.; Duan, X.; Liu, J.; Zhou, C.; Zhang, D., Mechanical and Electrical Anisotropy of Few-Layer Black Phosphorus. ACS Nano 2015. 43.

Besikci, C.; Bakir, A. T.; Tanatar, B., Dielectric screening effects on electron transport in

Ga0.51In0.49P/InxGa1−xAs/GaAs quantum wells. J. Appl. Phys. 2000, 88 (3), 1504-1510. 44.

Penumatcha, A. V.; Salazar, R. B.; Appenzeller, J., Analysing black phosphorus

transistors using an analytic Schottky barrier MOSFET model. Nat. Comm. 2015, 6, 8948. 45.

Doganov, R. A.; Koenig, S. P.; Yeo, Y.; Watanabe, K.; Taniguchi, T.; Özyilmaz, B.,

Transport properties of ultrathin black phosphorus on hexagonal boron nitride. Appl. Phys.

Lett. 2015, 106 (8), 083505. 46.

Allain, A.; Kang, J.; Banerjee, K.; Kis, A., Electrical contacts to two-dimensional

semiconductors. Nat. Mater. 2015, 14 (12), 1195-205.


17


47.

Page 18 of 24

Yu, S. H.; Lee, Y.; Jang, S. K.; Kang, J.; Jeon, J.; Lee, C.; Lee, J. Y.; Kim, H.; Hwang, E.;

Lee, S.; Cho, J. H., Dye-Sensitized MoS2 Photodetector with Enhanced Spectral Photoresponse. ACS Nano 2014, 8 (8), 8285-8291. 48.

Kwon, J.; Hong, Y. K.; Han, G.; Omkaram, I.; Choi, W.; Kim, S.; Yoon, Y., Giant

Photoamplification in Indirect-Bandgap Multilayer MoS2 Phototransistors with Local BottomGate Structures. Adv. Mater. 2015, 27 (13), 2224-30. 49.

Radisavljevic, B.; Kis, A., Mobility engineering and a metal-insulator transition in

monolayer MoS2. Nat. Mater. 2013, 12 (9), 815-20. 50.

Lopez-Sanchez, O.; Lembke, D.; Kayci, M.; Radenovic, A.; Kis, A., Ultrasensitive

photodetectors based on monolayer MoS2. Nat. Nanotechnol. 2013, 8 (7), 497-501.


18

Page 19 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 1. DFT-calculated interface structures of (a) BP/SiO2 (100) surface and (b) BP/h-BN. The black dashed lines show the repeated unit cells. (c) Capacitance comparison of h-BN and SiO2 depending on the thickness.


19


Page 20 of 24

Figure 2. (a) Schematic diagram of a local-gated BP FET with h-BN at the top side. (b) Optical microscope image of as-fabricated local-gated BP FET with source-drain and gate electrodes. (c) Schematic diagram of a global-gated BP FET with h-BN at the bottom side. (d) Optical microscope image of as-fabricated local-gated BP FET with source-drain and gate electrode. (e) Raman spectra of bulk BP without h-BN and a few layers of BP with an h-BN passivation layer.


20

Page 21 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 3. Transfer curves measured in the dual-sweep mode. (a) Typical transfer curves of hBN/BP structure depending on the drain bias in the global-gated architecture with SiO2. (b) Linear output curves with a discrete global gate bias from -90VG to 90VG. (c) Limited transfer curves depending on the drain bias in local-gated architecture with h-BN. (d) Non-linear output curves with a discrete local gate from -3VG to 3VG. Electron-enhanced output curves of the inset show the reverse tendency from the hole-enhanced region. (e) Improved transfer curves with a low gate bias operation from -8VG to 8VG in the h-BN/BP/h-BN structure in global-gated architecture with h-BN. (f) The behavior of linear output curves with discrete global gate bias from -8VG to 8VG.


21


Page 22 of 24

Figure 4. (a) Cross-section TEM image of FET well prepared by FIB in dual-gated architecture. (b) BP channel-resistance modeling based on the TEM image. This model consists of intrinsic, contact, and gate-induced channel resistance, which are marked by black, orange, and green, respectively. Band diagram of the local-gated BP FET at (c) VG = 0, (d) VG > 0, and (e) VG < 0 for understanding charge-density change of each segment in BP channel.


22

Page 23 of 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 5. Charge transport of Graphen and MoS2 fabricated for dual-gated FET. (a) and (d) show an optical image of graphene and MoS2 FET, respectively. (b), (e) Transfer curve of graphene and MoS2 FET via SiO2 as a function of global gate bias, and (c), (f) via h-BN as a function of local gate bias, respectively.


23


Page 24 of 24

Table of Contents Graphic


24

Dual-Gate Black Phosphorus Field-Effect Transistors with Hexagonal

Recommend Documents