Electrically Configurable Graphene Field-Effect Transistors with a

Apr 21, 2015 - KEYWORDS: Graphene, graded-potential gate, suppressed conductance, field-effect ..... Foundation of China (NSFC) (Grants 60911130231,...
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Letter pubs.acs.org/NanoLett

Electrically Configurable Graphene Field-Effect Transistors with a Graded-Potential Gate Xiaowei Wang,†,‡ Xingbin Jiang,†,‡ Ting Wang,†,‡ Jia Shi,†,‡ Mingju Liu,†,‡ Qibin Zeng,†,‡ Zhihai Cheng,†,‡ and Xiaohui Qiu*,†,‡ †

Key Laboratory of Standardization and Measurement for Nanotechnology, The Chinese Academy of Sciences, Beijing 100190, China National Center for Nanoscience and Technology, Beijing 100190, China

‡

S Supporting Information *

ABSTRACT: A device architecture for electrically configurable graphene field-effect transistor (GFET) using a graded-potential gate is present. The gating scheme enables a linearly varying electric field that modulates the electronic structure of graphene and causes a continuous shift of the Dirac points along the channel of GFET. This spatially varying electrostatic modulation produces a pseudobandgap observed as a suppressed conductance of graphene within a controllable energy range. By tuning the electrical gradient of the gate, a GFET device is reversibly transformed between ambipolar and n- and p-type unipolar characteristics. We further demonstrate an electrically programmable complementary inverter, showing the extensibility of the proposed architecture in constructing logic devices based on graphene and other Dirac materials. The electrical configurable GFET might be explored for novel functionalities in smart electronics. KEYWORDS: Graphene, graded-potential gate, suppressed conductance, field-effect transistor, electrically configurable devices

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doping to the graphene layer25 or Ti passivation top layer.26 To construct an IC, it would be desirable to have individual components of ambipolar and both n- and p-type FETs, which could be manufactured by processes compatible with the available technique. Here we report a device architecture for electrically controlled graphene field-effect transistor (GFET) with three distinct operation modes. The paradigm employed a gradedpotential top gate that continuously shifts the Dirac points along the graphene channel, resulting in a “pinch-off” region in the channel that suppresses the conductance of graphene within a controllable energy range. The n-type, p-type, and ambipolar transport characteristics were implemented by a single GFET, which enables the further construction of a complementary logic inverter. The tunable threshold voltage and electrically convertible transport behavior of the proposed GFET suggest a promising approach toward programmable logic devices based on graphene. A schematic of the device structure of graded-potential gate GFET (GPG−GFET) is shown in Figure 1a. The device configuration is similar to that of a double gate FET, consisting of a global back gate and a top gate. However, unlike the conventional metallic gate that maintains a uniform potential with respect to the bottom gate, the top gate of GPG−GFET is

raphene emerges as a promising electronic material because of its outstanding transport properties1−3 and thermal conductivity.4,5 Additional advantages of graphene, including its 2D nature and epitaxial growth on various substrates,6−8 also facilitate the fabrication of planar devices and integrated circuits using standard semiconductor process.9−11 In recent years, graphene-based prototype devices have been demonstrated with performance characteristics in comparison with or superior than those of the commercial counterparts.12−14 Moreover, the ambipolar conduction of graphene derived from its unique zero-bandgap electronic structure1,15 enables new device concepts, offering the flexibility for device engineering and introduction of novel functionality.16−18 The basic element in the design of a large-scale integrated circuit (IC) is the transistor. Digital IC typically comprises of complementary and paired p-type and n-type transistors to implement logic functions.19 Unlike conventional semiconductor materials, doping of graphene has been achieved by using electrostatic gates1,3,20 or charge transfer from adsorbants.21−23 Electrostatic gate allows local control of the energy bands in graphene by spatially manipulating carrier and transport characteristics.3,24 Alternatively, chemical doping that utilizes the charge transfer from molecular adsorbants is more effective to achieve one type of dominant charge carriers.23 However, in both cases the devices maintain the ambipolar characteristics because the doping processes only shift the Fermi level of graphene relative to the Dirac point.3,21,23 Up to date, the conversion of ambipolar to unipolar in GFET has only been demonstrated in a few studies through high level electron © XXXX American Chemical Society

Received: January 30, 2015 Revised: April 17, 2015

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DOI: 10.1021/acs.nanolett.5b00396 Nano Lett. XXXX, XXX, XXX−XXX

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Nano Letters RT = R C +

∫0

L

R ch(Vbg , VTG(x)) Δx

dx

(1)

where RC is the contact resistance and is approximately gate independent.29 Vbg is the back gate voltage and L is the total channel length. Rch(Vbg, VTG(x)) is the resistance element in graphene channel, including the resistance of p−n, p−p, and n−n interface. Given the moderate mobility of our GFET, which limits the electron mean free path to less than the typical characteristic length of graphene p−n junction, a diffusive model was used to calculate Rch(Vbg, VTG(x)) (see Supporting Information).30 Figure 2a gives the results at different top gate voltage polarities. The graded-potential gate should have a linear potential distribution across the top gate. For an applied voltage of ±3 V (on T1 or T2), we got VTG(x) = 3x/L or VTG(x) = −3x/L, respectively. Obviously, the type of transistor of GPG−GFET can be configured by switching the polarity of VTG(x). When a positive graded-potential was applied to the top gate, the device functioned as a unipolar n-type FET. On the other hand, the device operated as a p-type unipolar FET when the top gate applied with negative graded potential. The bipolar transport behaviors can be observed by setting the top gate potential to zero or a uniform value. As depicted in Figure 1, when the Fermi level is shifted into region I (III), the graphene channel is electrostatically doped to p (n)-type and the channel current is dominated by hole (electron) transport through p−p+ (n+−n) junctions. Thus, the device is at the ON state. In region II, “pinch-off” point forms in device channel and channel current is dominated by carrier transport through i−p junction, n−i−p junction or n−i junction. Owing to the reduced density of states (DOS) in the charge neutral point,31 the current reaches the minimum and the device is turned off. The OFF state current of the unipolar GFET can be approximately written as Ioff‑uni ∝ ((GIGD)/(GI + GD)),32 where GI is the conductance at the “pinch-off” point, GD is the conductance at the electrically doped region. Because of the vanishing carrier density in this intrinsic region, GI is much smaller than GD but nonzero.33 So the OFF state current of unipolar GFET is slightly larger than the minimum current of pristine ambipolar GFET. We calculated the transfer curves at various gate voltage profiles, as shown in Figure 2b. It is noticeable that the drain current is sensitive to the potential shapes. A linear profile is the ideal scenario to implement unipolar GFET due to a constant OFF state current. Figure 2c shows the drain current as a function of Vbg and voltage of T2 (VT2) while T1 is grounded.

Figure 1. (a) Schematic device structure and the band diagram of a GPG−GFET. The top gate of GPG−GFET is made of a highresistance conductive layer (HRCL) with two terminal electrodes (T1 and T2) placed above the source and drain regions. T1 is biased while T2 is grounded, enabling a graded-potential on the underneath graphene channel. The solid black line is the local position of the Dirac point, and the dashed red line indicates the Fermi energy level in the device. (b) Schematic carrier concentration in the GPG−GFET channel and simulated transfer characteristic of GPG−GFET using eq 1. When Fermi level is shifted to the region I (EF < EF(S)) or III (EF > EF(D)), the graphene channel is electrostatically doped to p or n-type, respectively. For EF(S) < EF < EF(D), the minimal density point resides in the channel and produces the OFF state.

made of a high-resistance conductive layer (HRCL) with two terminal electrodes (T1 and T2) placed above the source and drain regions. When T1 and T2 are applied with different voltages, the two-terminal top gate enables a linearly varying electric field perpendicular to the channel plane, resulting in a spatially varying doping profile along the single-layer graphene channel. Consequently, the vanishing carrier density creates a “pinch-off” region in graphene channel,27 as illustrated in Figure 1b. For EF(S) < EF < EF(D), where EF(S) and EF(D) are the Fermi energy of graphene under source and drain, respectively, the minimal density (pinch-off) point resides in the channel, rendering a reduced drain-source current insensitive to the back gate voltage. The transport characteristic of GPG−GFET is simulated numerically using a compact physical model based on intrinsic parameters of the GFET device including oxide capacitance, quantum capacitance and mobility. 27 Electric potential distribution of graded-potential gate is described by a spacedependent function VTG(x), where the x-axis is parallel to the device channel. The channel resistance (RT) can be written as28

Figure 2. Calculated transfer properties of GPG−GFET at varying gate voltages. (a) Simulated transfer characteristics of GFET with and without the graded-potential top gate, where VTG(x) is the top gate voltage in position x (0 ≤ x ≤ L, L = 10 μm) along the device channel. VTG(x) = 3x/L (VTG(x) = −3x/L) refers to a linear potential profiles when a voltage of 3 V (−3 V) is applied across the graded-potential gate. (b) Calculated transfer curves of GPG−GFET using different gate voltage profiles. Inset: linear (black line), quadratic (green line), and exponential (red line) potential shapes used in calculation. (c) Drain current as a function of Vbg and VT2 while T1 is grounded. The operation modes corresponding to the different regions are labeled. B

DOI: 10.1021/acs.nanolett.5b00396 Nano Lett. XXXX, XXX, XXX−XXX

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Nano Letters

voltage region) when VT2 was increased to 3 V. The threshold voltage of unipolar GFET is almost the same with the neutrality point voltage of pristine ambipolar GFET due to the zero doping at the source. On the other hand, the device worked as a p-type unipolar GFET when a negative voltage was applied to T2, as shown in Figure 3c. The electron transport branch is gradually suppressed and the back gate voltage region for the OFF state increases as VT2 decreasing. The gradual upshift of the OFF state current when increasing the potential gradient of top gate in Figure 3b,c can be accounted for by the constant GI and increasing GD. The on−off ratio of the unipolar GFET can be improved by reducing the conductance at Dirac point induced by charge disorder.33,36 The field-effect mobilities (Figure 3d) of GPG−GFET for all transistor types were extracted from the Ids−Vbg curves using the following formula: μFE = [(ΔIds/Vds)(L/W)]/CbΔVbg.37 Here, L and W are the length and the width of the graphene channel, respectively. The formation of “pinch-off” point in device channel renders the drain-source current insensitive to the back gate voltage, leading to a selective suppression of hole (electron) mobility to almost zero for n (p)-type unipolar GFET without significantly reducing electron (hole) mobility. Linear current−voltage characteristics of GPG−GFET (see Supporting Information) indicate that graded-potential gate does not change the semimetal nature of graphene. The threshold voltages of the unipolar GPG−GFETs are controlled by the potential gradient and the starting potential, which are determined by the bias voltage applied to T1 and T2 (Figure 4a). As seen in Figure 4b, when voltage difference is fixed and VT1 varies from −0.5 to 0.5 V, the threshold voltage of p-type unipolar GFET decreases from ∼40 to ∼0 V. This effect is understandable by referring to the device band diagrams in Figure 4a. The graded-potential gate with same potential gradient but smaller (larger) VT1 will make an overall up (down)-shift to the tilted barrier in graphene channel and a larger (smaller) back gate voltage is needed to turn the p-type GFET off. The unsatisfactory OFF state in Figure 4b,c is attributed to the random doping of intercalated water38 or remaining residues39 to graphene and this can be improved by thermal annealing.40 The electrical configuration of GPG−GFET is compatible for the construction of graphene-based complementary logic devices. A prototype electrically configurable inverter is fabricated based on two GPG−GFETs connected in series. As schematically shown in Figure 5a, two GPG−GFETs are built in one graphene flake by sharing the common source electrode and one graded gate electrode. The two GFETs operated in p-type and n-type transistor type by applying negative voltage on VT1 and positive voltage on VT2, respectively. When Vin is negatively biased, the p-GFET is turned on and n-GFET is turned off. Therefore, Vout is connected to VDD and resulted in logic 1. On the other hand, for positive input voltages, Vout is connected to ground and pulled down to logic 0. The voltage transfer characteristic and voltage gain, |∂Vout/∂Vin|, of the graphene inverter are shown in Figure 5c. Within the input voltage range from −60 to 90 V, the output voltage shows a transition from ∼27 to ∼18 mV. The relatively low gain of our prototype graphene inverter originates from the minimum current at the OFF state of unipolar GFET, which limits the on−off ratio of the unipolar GFET. The performance of the device should be dramatically improved by employing an efficiently coupled gate and reducing the residual carrier density at Dirac point of graphene. A corresponding

The three regions is defined according to the majority carrier, that is, hole transport branch (left region), electron transport branch (right region), and a pseudotransport-gap (middle blue region), respectively. The back gate voltage range for opening the pseudotransport gap can be estimated by ΔVbg = Ct|VT1 − VT2|/Cb, where Ct is capacitance of the top gate dielectric layer and Cb is the capacitance of the back gate SiO2 layer. Depending on the polarity and magnitude of VT2, this GPG−GFET can be switched among three independent operation modes, that is, p-type unipolar, ambipolar, and ntype unipolar transport, as labeled in Figure 2c. In contrast to the conventional graphene-based FET, our proposed GPG− GFET provides a capability to in situ program the operating functions of the device. The working scheme of GPG−GFET is different from that of the typical graphene p−n junction. For a conventional graphene p−n junction with a steep potential barrier, the width of the p−n interface is less than the electron mean free path, characteristic of the ballistic transport of electrons.34,35 In the case of GPG−GFET, the sloped band configuration enables the formation of a “pinch-off” region and thus results a disorder-induced diffusive transport when the Fermi level crosses with the graded potential. We fabricate a prototype GPG−GFET, where the gradedpotential gate was made of ∼20 nm nickel−chromium alloy as the HRCL and with two Cr/Au contacts (details of device fabrication are given in Supporting Information Figure S2). Figure 3b,c summarizes the transport characteristics of the GPG−GFET device operating under two unipolar modes. Figure 3b shows the hole transport branch gradually suppressed and the back gate voltage region for the OFF state is increasing as VT2 increasing. The device behaved as an n-type unipolar transistor (with an OFF state of more than 70 V back gate

Figure 3. (a) Optical micrograph of the GPG−GFET and circuit structure for the transport type control in GPG−GFET. (b) Transfer characteristics (Ids−Vbg) of GPG−GFET with positive graded top gate voltage. Voltage of terminal 1 (VT1) is fixed at 0 V. Voltage of terminal 2 (VT2) starts from 0 to 3 V in 0.5 V step. (c) Ids−Vbg curves of GPG− GFET with negative graded top gate voltage. VT1 is fixed at 0 V. VT2 starts from 0 V to −3 V in −0.5 V step. (d) Field-effect mobility of the device in the ambipolar (VT1 = VT2 = 0 V), n-type unipolar (VT1 = 0 V, VT2 = 3 V) and p-type unipolar mode (VT1 = 0 V, VT2 = −3 V). The measurements were taken using the same device at 300 K with a drain bias of 50 mV in (b−d). C

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Figure 4. (a) Circuit structure for the threshold voltage control in GPG−GFET and band diagrams for p-type unipolar mode GPG−GFET with different threshold voltage. (b) Ids−Vbg curves of unipolar p-type GFET with VT1 starts from −0.5 to 0.5 V in 0.5 V step and the voltage difference between VT2 and VT1 is fixed at −2.5 V. (c) Ids−Vbg curves of unipolar n-type GFET with VT1 starts from −0.5 to 0.5 V in 0.5 V step and difference between VT2 and VT1 is fixed at 2.5 V.

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ASSOCIATED CONTENT

S Supporting Information *

Experimental methods, Figures S1−S5. This material is available free of charge via the Internet at http://pubs.acs.org.

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This project is partially supported by the Natural Science Foundation of China (NSFC) (Grants 60911130231, 21173058, and 21203038).

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Figure 5. Complementary graphene logic inverter. (a) Schematic view of the graphene inverter with two integrated GPG−GFETs. (b) Circuit configuration of the graphene inverter. Power supply voltage VDD is applied to the drain electrode of p-GFET. Back gate electrode serves as the input voltage (Vin) electrode. Output voltage (Vout) is measured using the common source electrode of the p-GFET and nGFET. (c) Voltage transfer characteristic Vout(Vin) and voltage gain of the graphene logic inverter. (d) Calculated voltage transfer curves of graphene inverter with different residual carrier density.

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