Letter www.acsami.org
Electronically Pure Single-Chirality Semiconducting Single-Walled Carbon Nanotube for Large-Scale Electronic Devices Huaping Li,* Hongyu Liu, Yifan Tang, Wenmin Guo, Lili Zhou, and Nina Smolinski Atom Nanoelectronics Inc., 440 Hindry Avenue, Unit E, Inglewood, California 90301, United States S Supporting Information *
ABSTRACT: Single-walled carbon nanotube (SWCNT) networks deposited from a purple single chirality (6,5) SWCNT aqueous solution were electrically characterized as pure semiconductors based on metal/semiconductor/metal Schottky contacts using both complex instruments and a portable device. Both air-stable PMOS (p-type metal-oxidesemiconductor) and NMOS (n-type metal-oxide-semiconductor, resembling amorphous silicon) thin film transistors were fabricated on (6,5) SWCNT in large scale showing the characteristics of fA off current and ION/IOFF ratio of >1 × 108. CMOS (complementary metal-oxide-semiconductor) SWCNT inverter was demonstrated by wire-bonding PMOS (6,5) SWCNT TFT and NMOS (6,5) SWCNT TFT together to achieve the voltage gain as large as 52. KEYWORDS: single chirality, semiconducting single-walled carbon nanotube, schottky contact, nonlinear current−bias curves, thin-film transistors, large-scale electronic devices
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those constructed on optically pure semiconducting SWCNTs.5 The stable and invariant device performances of (6,5) SWCNT can be plausibly ascribed to its uniform diameter and chirality. By wire-bonding NMOS SWCNT TFT and PMOS SWCNT TFT, CMOS (complementary metal-oxide-semiconductor) SWCNT inverter with a voltage gain of 52 was achieved. The fabrication processes of SiNx top-gated NMOS (6,5) SWCNT TFTs are similar to those for amorphous silicon TFTs. Moreover, the performances of SiNx top-gated NMOS (6,5) SWCNT TFTs resemble the characteristics of amorphous silicon TFTs. These imply that it is feasible to massively fabricate high-quality SWCNT TFT backplanes with industrial amorphous Si manufacturing lines. The high performances of HfO2 top-gated PMOS (6,5) SWCNT TFTs demonstrate the compatibility of (6,5) SWCNT with high κ dielectrics. This qualifies (6,5) SWCNT as an excellent candidate for ultrafast electronics. The above-mentioned potentials thus put the electronically pure single-chirality semiconducting (6,5) SWCNT ink in the place for practical applications in largescale electronic devices. In this contribution, the separation and optical characterization of single-chirality (6,5) SWCNT ink were reported. The obtained (6,5) SWCNT ink was coated on the substrates (glasses and silicon wafers) to form consistent and uniform SWCNT thin films. Cr(10 nm)/Au(40 nm) bimetal electrodes were deposited on these (6,5) SWCNT thin films to form
ingle-walled carbon nanotubes (SWCNTs) have been reported for their prospective applications.1 One of these expectations is to fabricate field-effect transistors for integrated circuits,2 memory,3 computers,4 and thin-film transistor (TFT) backplanes.5 The wide distribution in diameter, chirality, and property of as-grown SWCNTs has obstructed their advance in this forestalling trend.6 Tremendous efforts have been made to sort out single chirality semiconducting species. The separated single chirality SWCNTs have been majorly characterized with optical spectroscopies.7 Devices constructed on those optically claimed semiconducting SWCNTs ubiquitously show linear current-to-bias responses (Figure S1), violating semiconductor characteristics of metal/semiconductor/metal Schottky contacts. This contribution reveals an electronically pure single chirality semiconducting (6,5) SWCNT that consistently exhibits nonlinear current−bias responses from the devices with two metal electrodes on SWCNT networks. Further constructed on these metal/SWCNT/metal Schottky diodes, air-stable NMOS (n-type metal-oxide-semiconductor) and PMOS (p-type metal-oxide-semiconductor) thin-film transistors were obtained by depositing 170 nm SiNx and 30 nm HfO2 as top-gated dielectrics using PECVD (plasma enhanced chemical vapor deposition) and ALD (atomic layer deposition), respectively. Both NMOS and PMOS SWCNT TFTs exhibited fA off current and ION/IOFF ratio of >1 × 108 in their transfer characteristics. In their output characteristic curves, the clear pinch-off and saturated currents reflect that their transistor properties follow the standard field-effect transistor principle. The performances of these top-gated (6,5) SWCNT TFTs were consistent and reproducible, remarkably different from © XXXX American Chemical Society
Received: June 4, 2016 Accepted: August 3, 2016
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DOI: 10.1021/acsami.6b06647 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
Spectralyzer. When the solution was excited with 532 nm laser beam, Raman scattering was detected of a strong tangential G band (G from Graphite) at 1587 cm−1 (ωG+, 15 cm−1 fwhm) and 1525 cm−1 (ωG−, 13 cm−1 fwhm), disorder-induced D band in the range of 1200−1325 cm−1, second-order overtone G′ at 2617 cm−1, and a weak RBM (radial breathing model) band at 310 cm−1 (dt = α/ωRBM= 248 cm−1nm/310 cm−1 = 0.8 nm).11,12 These Raman Scattering peaks correspond to sp2 carbon−carbon stretching and radial expansion-contraction of (6,5) SWCNT, further collaborating the results of Vis−NIR absorption and NIR fluorescence emission. The peak ratio of D/G is estimated to be 0.03, reflective of (6,5) SWCNT with little defects. The purple solution was casted on 0.1% poly(L-lysine) aqueous solution treated Borofloat 33 glass (diameter, 100 mm; thickness, 500 μm) to form uniform thin layer (6,5) SWCNT film with high transparency (Figure 2A).13 On the top of (6,5) SWCNT thin film, Cr(10 nm)/Au(40 nm) bimetals were evaporated to pattern electrodes with channel length and width of 5 and 100 μm (Figure 2B). The (6,5) SWCNT thin film between two electrodes was imaged with SEM (scanning electron microscope) exhibiting a layer of well-dispersed nanotube network (Figure 2C). The (6,5) SWCNT density is about 5−6 nanotubes per μm2. The length of (6,5) SWCNT is around 1−2 μm (Figures S2 and S3). The metal/(6,5) SWCNT/metal double diodes were characterized with Keithley 4200 SCS (semiconductor characterization System) (the inset to Figure 2D) in air at room temperature. A typical current-bias curve is displayed in Figure 2D as a pronounced gaplike nonlinearity. The curve seems to exhibit a power-law behavior, that is, current ∝ (bias)α, where α > 1. The nonlinearity at room temperature indicates that (6,5) SWCNT thin film is semiconducting. The devices are semiconducting SWCNT networks connected to two metal contacts, that is, two Schottky-type diodes connected back-to-back.14,15 Contrastly, the devices fabricated with same procedures using Nanointegris 99% semiconducting SWCNTs gave rise to linear current−bias responses (Figure S1). The nonlinear current−bias curve can be explored for electrical examination of purity of semiconducting SWCNTs in a simple and convenient way. Similarly, the purple solution was casted on a small piece of 0.1% poly(L-lysine) aqueous solution treated silicon wafer (1 cm × 3 cm, 500 nm SiO2) to form (6,5) SWCNT thin film. On the top of (6,5) SWCNT thin film, two 10 mm long gold electrodes separated in 50 μm were aerosol jet printed with 4 nm gold nanoparticles in xylene (40 weight %) and followed by curing at 200 °C for 30 min. The two electrodes were contacted with two copper wires (diameter: 0.5 mm) using silver paste and soldering with metal tin (the inset to Figure 2E). The simple metal/(6,5) SWCNT/metal chip connected to altas DCA Pro purchased from Peak Instrument, which was controlled with a laptop. As shown in Figure 2E, the graph displays nonlinear curves. The purple solution was also casted on a 2.5 cm × 2.5 cm quartz pretreated with 0.1% poly(L-lysine) aqueous solution to obtain (6,5) SWCNT thin film. Silver paste was casted on the top of (6,5) SWCNT thin film to form two 2.5 cm long silver electrodes separated in 2 mm (Figure 2F). A similar nonlinear current−bias curve was observed. The generality of nonlinearity with different metal electrodes on various substrates further demonstrated that these (6,5) SWCNT thin films deposited from purple solution are electronically pure semiconductors.
metal/SWCNT/metal devices for current−bias characterization. TFTs were further constructed on metal/SWCNT/metal devices by depositing different dielectrics (SiNx or HfO2) and then Cr(10 nm)/Au(40 nm) bimetal gate electrodes to show characteristics of NMOS and PMOS devices. NMOS SWCNT TFT was wire-bonded with PMOS SWCNT TFT to demonstrate the voltage output of SWCNT inverter. SWCNTs raw powder was produced by Rice University Mark III high pressure carbon monoxide reactor (Batch number 190.1). The electronically pure semiconducting SWCNT was sorted out using modified gel chromatography method.7 Briefly, SWCNT raw powder was dispersed in 2% sodium dodecyl sulfate (SDS) aqueous solution (deionized water) using tip sonicator with 20 W power for 20 h. After ultracentrifuge or precipitation, the decanted supernatant solution was transferred to Saphacryl S-200 gel column. The SWCNTs trapped in gel were eluted out with 2% SDS solution. After 4−6 cycles of gel chromatography, the pure purple solution was collected in a concentration of 6 μg/mL (Figure 1A). The estimation method is provided in the Supporting Information.
Figure 1. (A) Photo image of 100 mL purple solution with concentration of 6 μg/mL. (B) Vis−NIR absorption spectrum (blue curve) and NIR fluorescence emission spectrum (red curve, excited at 532 nm) of the purple solution. (C) Raman Spectrum of the purple solution excited at 532 nm laser beam. The red curve is the enlarged RBM peak band at 310 cm−1.
Vis (visible)−NIR (near-infrared) absorption and NIR fluorescence emission spectra of the collected purple solution were recorded on NS3 Applied Nano Spectralyzer at ambient temperature (Figure 1B). In the absorption spectrum (blue solid curve in Figure 1B), two major absorbances peaked at 983 nm (extinction coefficient:4400 M−1cm−1) and 570 nm with fwhm (Full Width at Half Maximum) of 30.5 and 30 nm respectively, assigned to S11 and S22 transition between the van Hove Singularities of (6,5) chirality SWCNT.8,9 A broad band between 800 and 880 nm has been considered as the sideband of S11 transition.10 When the solution was excited with 532 nm laser light source, fluorescence emission were detected of a 986 nm peak with fwhm of 26.5 nm and a broad band between 1060 and 1160 nm (red dash curve in Figure 1B).10 The negligible Stokes’ shift (3 nm) and narrow fwhm indicate the high purity of (6,5) SWCNT. The solution was further characterized with Raman spectrum on NS3 Applied Nano B
DOI: 10.1021/acsami.6b06647 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
Figure 2. (A) Photo image of Borofloat 33 glass (diameter, 100 mm; thickness, 500 μm) coated with (6,5) SWCNT thin films between the patterned Au/Cr electrodes with channel length of 5 μm and channel width of 100 μm. (B) Zoomed-in image of A. (C) SEM image of (6,5) SWCNT thin film inside the patterned electrodes showing tube length in the range of 1−2 μm and tube density of 4−6 tubes per μm2. (D) Measured current versus bias curve showing nonlinear curve when probed on two electrodes (microimage in the inset) on SemiProbe PS4L M12 probe station with Keithley 4200 SCS. E) The altas DCA Pro controlled by laptop was used to characterize (6,5) SWCNT thin film on a small piece of silicon wafer (500 nm SiO2) showing a nonlinear curve. The gold electrodes were aerosol jet printed to form a device with channel length of 50 μm and channel width of 10 mm and were bonded with two copper wires (diameter, 0.5 mm) for connecting to the altas DCA Pro. (F) On (6,5) SWCNT-coated quartz (2.5 cm × 2.5 cm), two copper wires (0.5 mm) were bonded with silver paste to form metal/(6,5) SWCNT/metal device with channel length of 2 mm, and channel width of 2.5 cm.
MOSFETs for both the linear and saturated regimes2 when capacitance per unit of SiNx was measured to be 24 nF/cm2.20 These results are remarkably different from those of devices constructed on Nanointegris 99% semiconducting SWCNTs (Figure S4 and S5), which showed 60 nA off-current, ION/IOFF of about 100, and mobility of 70.77 cm2/(V s). The transfer characteristics of over 20 SiNx top-gated (6,5) SWCNT TFTs with 50 μm channel width were plotted in Figure 3F. The excellent uniformity elicits the reproducibility and consistency of (6,5) SWCNT TFTs, illustrating the great advantage of single-chirality SWCNT. About 98% of 1440 unit devices were analyzed statistically (Figure S6 and Table S1). The rest 2% devices were not considered because of the defects. Their ION/ IOFF ratio was plotted against WC/LC (Figure 3G). The overall ION/IOFF is between 1 × 106 and 1 × 107 with less than 10% error bar. Obviously, the ION/IOFF ratio does not vary with the channel width (or the amount of (6,5) SWCNT), further validating the electronical purity of semiconducting (6,5) SWCNT. The SiNx top-gated (6,5) SWCNT TFTs were stressed with VDS = 10 V at room temperature for 1 h, there was negligible VT shift (Figure S7). When VDS = 10 V was applied, the on current reached to 30 μA (Figure S8), which can be used to drive organic light-emitting diodes. More significantly, the transparent electronically pure semiconducting single chirality (6,5) SWCNT thin film deposited with solution process is apt for roll-to-roll fabrication on glasses and transparent plastics like polyethylene film. Besides the NMOS TFTs, PMOS TFTs of (6,5) SWCNT thin film were fabricated by depositing 30 nm HfO2 dielectrics using ALD on Borofloat33 Glass with Pd as electrodes. The device dimensions are same as those of NMOS TFTs. The typical transfer characteristics of HfO2 top-gated (6,5) SWCNT PMOS TFT with channel width of 50 μm is shown in Figure 4A. The drain current (IDS) of PMOS device increased from 1 × 108 are the best
On the Borofloat33 Glass coated with a thin layer of (6,5) SWCNT film, about 1440 (row:40, column: 35) unit TFTs were fabricated using photolithography of a fixed 5 μm channel length and a series of channel widths of 5, 25, 50 (3 rows), 75, and 100 μm (2 rows) (Figure 3A). Briefly, Cr(10 nm)/Au(40 nm) bimetals were evaporated to pattern drain/source electrodes. The (6,5) SWCNT thin film was patterned by O2 plasma etching. Over the patterned SWCNT thin films, a layer of 170 nm SiNx was deposited using PECVD. A second Cr(10 nm)/Au(90 nm) were evaporated to pattern gate electrodes on SiNx layer. The SiNx layer over drain/source test pads were opened using dry etching. The as-formed SiNx top-gated (6,5) SWCNT TFT was photographed as shown in Figure 3B. The cross section diagram is presented in Figure 3C. These SiNx top-gated (6,5) SWCNT TFTs were characterized with Keithley 4200 SCS on Semiprobe PS4L M12 probe station in air at room temperature. The typical transfer characteristics of a SiNx top-gated (6,5) SWCNT TFT with channel width of 50 μm is presented in Figure 3D. Under VDS = 0.1 V, the IDS increased from 1.8 fA to 0.22 μA when VGate swept from −5 to 20 V. The device is NMOS with ION/IOFF greater than 1 × 108. The n-type characteristics was hypothesized to arise from fixed positive charges in SiNx layer.16 It is worthy to note that the fA off-current of (6,5) SWCNT network is 2 orders of magnitude lower than those of amorphous silicon TFTs17 and comparable to those of single semiconducting SWCNT devices.18 Its threshold voltage (VT) is estimated to be 1.5 V and subthreshold swing (ss) to be 592 mV/dec. The output characteristics of SiNx top-gated (6,5) SWCNT TFTs were measured by sweeping VDS from 0 to 5 V (Figure 3E). The downward bending IDS−VDS curve moved down when VGate decreased from 20 V to −6 V with step of 2 V. The saturated IDS was observed when VGate was under 10 V. The linear responses at low VDS indicate near ohmic contact for efficient electron injection.15,16,19 The electron mobility (μe) is estimated to be 0.5 cm2/(V s) following standard models of C
DOI: 10.1021/acsami.6b06647 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
Figure 3. (A) Photo image of 1440 unit (6,5) SWCNT TFTs fabricated using photolithography on Borofloat33 Glass (diameter, 100 mm; thickness, 500 μm) of a fixed 5 μm channel length and a series of channel widths of 5, 25, 50, 75, and 100 μm. (B) Micro image of one SWCNT TFT with channel width of 50 μm. (C) Structural illustration of SiNx top-gated (6,5) SWCNT TFTs viewed from cross-section. (D) Typical transfer characteristics of SiNx top-gated (6,5) SWCNT TFT with channel width of 50 μm showing fA off-current and ION/IOFF ratio of >1 × 108 by sweeping VGate from −5 to 20 V (right IDS is linear scale and left IDS is log scale) under VDS = 0.1 V. (E) Output characteristics of SiNx top-gated (6,5) SWCNT TFT with channel width of 50 μm showing downward bending curves by sweeping VDS from 0 to 5 V. The curves moved down when VGate switched from 20 V to −6 V with step of 2 V. (F) Transfer characteristics of 20 SiNx top-gated (6,5) SWCNT TFTs with channel width of 50 μm to illustrate the reproducibility and consistency. (G) ION/IOFF ratio variation of different channel widths elicits consistent ION/IOFF ratio in a series of channel widths of 5, 25, 50, 75, and 100 μm, reflective of electronically pure semiconductor.
performances of p-type SWCNT TFTs,19,21 and superior to low temperature polycrystalline silicon (LTPS) TFTs.22 The output characteristics of HfO2 top-gated (6,5) SWCNT PMOS TFT is exhibited in Figure 4B with VDS swept from 0 V to −8 V. The downward bending curve moved down when VGate went up from −14 V to 0 V. The saturated on-current was observed under V Gate > −8 V. These results demonstrate the
compatibility of SWCNTs to high-κ dielectrics like HfO2. It is worth noting that there is a fundamental problem for amorphous silicon, LTPS, and metal oxides to be modulated by high-κ dielectrics because of carrier scattering induced degradation of electrical properties.23 Because the performances of SiNx modulated (6,5) SWCNT TFTs are similar to those of amorphous silicon TFTs, the D
DOI: 10.1021/acsami.6b06647 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
Figure 4. (A) Typical transfer characteristics of HfO2 top-gated (6,5) SWCNT TFT with channel width of 50 μm showing fA off-current and ION/ IOFF ratio of >108 by sweeping VGate from 0 V to −15 V (right black curve IDS is in log scale and left red IDS is in linear scale) under VDS= −1 V. (B) Output characteristics of HfO2 top-gated (6,5) SWCNT TFT with channel width of 50 μm showing downward bending curves by sweeping VDS from 0 V to −8 V. The curve moved down when VGate switched from −14 to 0 V with step of 2 V.
Figure 5. (A) Schematic illustration of CMOS inverter by wire bonding PMOS and NMOS (6,5) SWCNT TFTs. (B) Circuit diagram of CMOS (6,5) SWCNT inverter. (C) Voltage transfer characteristics of CMOS (6,5) SWCNT inverter showing a sharp inversion (black curve) at VIN = 4 V and corresponding voltage gain as large as 52 (red dot curve).
To demonstrate (6,5) SWCNT TFTs for integrated circuits, we mounted the PMOS wafer on NMOS wafer. Wire bonding were implemented to connect gate electrode and one drain/ source electrode of PMOS (6,5) SWCNT TFT to gate electrode and one drain/source electrode of NMOS (6,5) SWCNT TFT, respectively (Figure 5A). The constructed CMOS circuit was characterized using Keithley 4200 SCS on Semiprobe PS4L M12 probe station in air at room temperature. As shown in the inverter diagram (Figure 5B), a voltage supply (VDD = 8 V) was applied to the drain electrode of PMOS (6,5) SWCNT TFT and the source electrode of NMOS (6,5) SWCNT TFT was connected to the ground. When input voltage (VIN) swept from 0 to 8 V with interval of 0.05 V, the measured output voltage remained high voltage at 7.9 V before the sharp drop at 4 V input voltage. After 4 V input voltage, the output voltage remained very low voltage at 0.1 V (black curve in Figure 5C). By differentiating VOUT − VIN curve, the voltage gain as large as 52 was obtained for (6,5) SWCNT CMOS inverter (red dot curve in Figure 5C). This high voltage gain for carbon nanotube inverters is plausibly due to the high performance of (6,5) SWCNT TFTs ( fA off-current and ION/IOFF ratio of >1 × 108). By changing photomask design, PMOS and NMOS (6,5) SWCNT TFTs can be fabricated in a same substrate either coplanar (2D) or vertically overlapping
operation principle of amorphous silicon TFTs can be interpreted for SiNx top-gated (6,5) SWCNT TFTs.24 Before the channel was turned on, the large Schottky barrier completely shut down the channel same as metal/(6,5) SWCNT/metal at a low voltage bias. After the channel was turned on but still under VT, the electron was drawn to form depletion layer between (6,5) SWCNT and dielectrics in proportion to the increase in VG. But the drain current increased exponentially (IDS ∝ exp(qVGS/kBT), where q is the charge of an electron, kB is Boltzmann constant, T is temperature), as the band bending increased.14 After the depletion region was completed where VT was defined (VGS > VT), metal/(6,5) SWCNT became ohmic contact and the current linearly increased with applied gate voltage (IDS = kn′W/L(VGS − VT − VDS/2)VDS, where kn′ is constant with units A/V2, W is channel width, and L is channel length).15 This is due to the further drawn electrons by increasing VGS, which occupied conduction band of (6,5) SWCNT to form conductive channel. This operation principle similarly applies to HfO2 modulated PMOS (6,5) SWCNT TFTs. Differently, negative VGS forced holes enter into depletion region. After the depletion region was completed (VGS > VT), the excess holes that occupied valence band to form conductive channel. E
DOI: 10.1021/acsami.6b06647 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces together (3D). The interconnections between PMOS and NMOS (6,5) SWCNT TFTs could be achieved with Via drilling to form logic circuits for microelectronics applications with increasing function per area and less power dissipation. The conclusive remark is that the performances of both PMOS and NMOS (6,5) SWCNT TFTs can be further improved with increasing on-current by shortening channel length25 or widening channel width26 or increasing the density of SWCNT27 without sacrificing the extremely low off current. From SEM images of current devices, the thickness of (6,5) SWCNT film is below 1 nm. The larger on current is accomplishable for TFTs with thicker (6,5) SWCNT film >10 nm.27 For electronically pure semiconducting SWCNT, the off current will not vary with the amount of SWCNT such as channel width or thickness. Therefore, both mobilities and ION/ IOFF ratios would be further improved with thick (6,5) SWCNT films. Statistically, the thick layer of (6,5) SWCNT film could eliminate device variation, especially with single-chirality (6,5) SWCNT of uniform electrical properties. These confer electronically pure (6,5) SWCNT thin film (∼1 nm) as the replacement of amorphous silicon (>100 nm),16 LTPS (>50 nm),20 and metal oxides (>50 nm)28,29 for TFT backplanes to meet the needs for emerging display markets such as transparent, flexible and wearable displays. Further with SWCNT alignment technologies30 and high-κ dielectrics,23 extremely high on-current (6,5) SWCNT TFT can be anticipated with narrow channel length for high-speed and low-power-dissipation electronics.30 The electronically pure (6,5) SWCNT can thus become practical for large-scale electronic applications.
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REFERENCES
(1) De Volder, M. F. L.; Tawfick, S. H.; Baughman, R. H.; Hart, A. J. Carbon Nanotubes: Present and Future Commercial Applications. Science 2013, 339, 535−539. (2) Cao, Q.; Kim, H.-S.; Pimparkar, N.; Kulkarni, J. P.; Wang, C. J.; Shim, M.; Roy, K.; Alam, M. A.; Rogers, J. A. Medium-Scale Carbon Nanotube Thin-Film Integrated Circuits on Flexible Plastic Substrates. Nature 2008, 454, 495−500. (3) Rueckes, T.; Kim, K.; Jeselevich, E.; Tseng, G. Y.; Cheung, C.-L.; Lieber, C. M. Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing. Science 2000, 289, 94−97. (4) Shulaker, M. M.; Hills, G.; Patil, N.; Wei, H.; Chen, H.-Y.; Wong, H.-S. P.; Mitra, S. Carbon Nanotube Computer. Nature 2013, 501, 526−530. (5) Zou, J. P.; Zhang, K.; Li, J. Q.; Zhao, Y. B.; Wang, Y. L.; Pillai, S. K. R.; Demir, H. V.; Sun, X. W.; Chan-Park, M. B.; Zhang, Q. Carbon Nanotube Driver Circuit for 6 × 6 Organic Light Emitting Diode Display. Sci. Rep. 2015, 5, 11755. (6) Almudever, C. G.; Rubio, A. Variability and Reliability of CNFET Technology: Impact of Manufacturing Imperfections. Microelectron. Reliab. 2015, 55, 358−366. (7) Liu, H. P.; Nishide, D.; Tanaka, T.; Kataura, H. Large-Scale Single-Chirality Separation of Single-Walled Carbon Nanotubes by Simple Gel Chromatography. Nat. Commun. 2011, 2, 309. (8) Bachilo, S. M.; Strano, M. S.; Kittrell, C.; Hauge, R. H.; Smalley, R. E.; Weisman, R. B. Structure-Assigned Optical Spectra of SingleWalled Carbon Nanotubes. Science 2002, 298, 2361−2366. (9) Schoppler, F.; Mann, C.; Hain, T. C.; Neubauer, F. M.; Privitera, G.; Bonaccorso, F.; Chu, D. P.; Ferrari, A. C.; Hertel, T. Molar Exctinction Coefficient of Single-Wall Carbon Nanotubes. J. Phys. Chem. C 2011, 115, 14682−14686. (10) Ghosh, S.; Bachilo, S.; Weisman, R. B. Advanced Sorting of Single-Walled Carbon Nanotubes by Nonlinear Density-Gradient Ultracentrifugation. Nat. Nanotechnol. 2010, 5, 443−450. (11) Bonhommeau, S.; Deria, P.; Glesner, M. G.; Talaga, D.; Najjar, S.; Belin, C.; Auneau, L.; Trainini, S.; Therien, M. J.; Rodriguez, V. Raman Spectroscopic Investigation of Individual Single-Walled Carbon Nanotubes Helically Wrapped by Ionic, Semiconducting polymers. J. Phys. Chem. C 2013, 117, 14840−14849. (12) Dresselhaus, M. S.; Dresselhaus, G.; Jorio, A.; Souza Filho, A. G.; Saito, R. Raman Spectroscopy on Isolated Single Wall Carbon Nanotubes. Carbon 2002, 40, 2043−2061. (13) Takahashi, T.; Takei, K.; Gillies, A. G.; Fearing, R. S.; Javey, A. Carbon Nanotube Active-Matrix Backplanes for Conformal Electronics and Sensors. Nano Lett. 2011, 11, 5408−5413. (14) Tans, S. J.; Verschueren, A. R. M.; Dekker, C. RoomTemperature Transistor Based on a Single Carbon Nanotube. Nature 1998, 393, 49−52. (15) Sze, S. M. Semiconductor Devices−Physics and Technology; Wiley: New York, 1985. (16) Ha, T.-J.; Chen, K.; Chuang, S.; Yu, K. M.; Kiriya, D.; Javey, A. Highly Uniform and Stable n-Type Carbon Nanotube Transistors by Using Positively Charged Silicon Nitride Thin Film. Nano Lett. 2015, 15, 392−397. (17) Cherenack, K. H.; Kattamis, A. Z.; Hekmatshoar, B.; Sturm, J. C.; Wagner, S. Amorphous-Silicon Thin Film Transistors Fabricated at 300 °C on a Free-Standing Foil Substrate of Clear Plastic. IEEE Electron Device Lett. 2007, 28, 1004−1006. (18) Javey, A.; Kim, H.; Brink, M.; Wang, Q.; Ural, A.; Guo, J.; McIntyre, P.; McEuen, P.; Lundstrom, M.; Dai, H. High-κ Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates. Nat. Mater. 2002, 1, 241−245.
ASSOCIATED CONTENT
S Supporting Information *
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b06647. Experimental details, (6,5) SWCNT length distribution, statistical analysis of ION/IOFF ratios and threshold voltages for NMOS (6,5) SWCNT TFTs, the transfer characteristics and bias stress test of NMOS (6,5) SWCNT TFTs under VDS = 10 V (PDF)
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TFT, thin film transistor SDS, sodium dodecyl sulfate fwhm, Full Width at Half Maximum
AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. Author Contributions
The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS We are grateful to the USA Air Force STTR fund (Contract FA8750-15-C-0258). ABBREVIATIONS SWCNT, single-walled carbon nanotube PMOS, p-type metal-oxide-semiconductor NMOS, n-type metal-oxide-semiconductor CMOS, complementary metal-oxide-semiconductor fA, femto ampere F
DOI: 10.1021/acsami.6b06647 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Letter
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DOI: 10.1021/acsami.6b06647 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
