Electrospun p-Type Nickel Oxide Semiconducting Nanowires for Low

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Electrospun p-Type Nickel Oxide Semiconducting Nanowires for Low-Voltage Field-Effect Transistors Ao Liu, You Meng, Huihui Zhu, Yong-Young Noh, Guoxia Liu, and Fukai Shan ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b08794 • Publication Date (Web): 22 Sep 2017 Downloaded from http://pubs.acs.org on September 22, 2017

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ACS Applied Materials & Interfaces

Electrospun p-Type Nickel Oxide Semiconducting Nanowires for Low-Voltage Field-Eect Transistors Ao Liu,

†,‡,¶

You Meng,

†,‡,¶

Huihui Zhu,

†,‡,¶

Yong-Young Noh,

and Fukai Shan

§

Guoxia Liu,

∗, †, ‡, ¶

∗, †, ‡, ¶

†College

of Physics, Qingdao University, Qingdao 266071, China ‡College of Electronic & Information Engineering, Qingdao University, Qingdao 266071, China ¶Lab of New Fiber Materials and Modern Textile, Growing Base for State Key Laboratory, Qingdao University, Qingdao 266071, China §Department of Energy and Materials Engineering, Dongguk University, 30 Pildong-ro, 1-gil, Jung-gu Seoul 04620, Republic of Korea E-mail: [email protected]; [email protected]

Abstract One-dimensional metal-oxide nanowires are regarded as important building blocks in nanoscale electronics due to their unique mechanical and electrical properties. In this work, p-type nickel oxide nanowires (NiO NWs) were fabricated by combining sol-gel and electrospinning processes. The polyvinylpyrrolidone (PVP) with 1,300,000 molecular weight was used as the polymer matrix to increase the viscosity of NiO precursor solution. The formation and properties of the as-spun NiO/PVP composite NWs before/after calcination treatment were investigated using various techniques. Due to 1

ACS Paragon Plus Environment


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the enhanced adhesion properties between UV-treated NiO NWs and the substrate, the eld-eect transistors (FETs) based on NiO NWs were found to exhibit satisfying p-channel behaviors. For the fabrication of aligned NiO NW arrays, two parallel conducting Si strips were grounded as NW collector. The integrated FETs based on aligned-NiO NWs were demonstrated to exhibit superior electrical performance compared to the disordered counterparts with the comparable NW coverage. By employing high-k aluminum oxide (Al2 O3 ) as dielectric layer instead of conventional SiO2 , the devices with aligned NiO NW array exhibit a high hole mobility of 2.8 cm2 /Vs with a low operating voltage of 5 V, fast switching speed, and successful modulation of light emission over external light-emitting diode. To the best of our knowledge, this is the rst work demonstrating the low-voltage transistors based on p-type oxide NWs, which represents a great step toward the development of sensors and CMOS logic circuits.

Keywords Nanowire; electrospinning; p-type metal oxides; low-operating voltage; eld-eect transistor

1 Introduction In past decades, one-dimensional semiconductor nanowires (NWs) have attracted great interest for the fabrication of (opto)electronic devices because of their excellent mechanical exibility, optical, and electrical properties.

1

Among assorted NW materials (e.g.

silicon,

germanium, carbon nanotube, III-V semiconductor), metal-oxide NWs are regarded as excellent candidate due to the large bandgap, large specic surface, and distinctive transport feature.

2

Various approaches have been conducted to synthesize high-quality oxide NWs, such as

vapor-liquid-solid growth, hydrothermal synthesis, and electrospinning (ES).

3

Among these

methods, the ES is the most straightforward and versatile technique, which is not only being employed in laboratories but also increasingly being adopted in industry. Besides, ES tech-

2


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nique allows the fabrication of continuous and uniform NWs with controllable diameters and high aspect ratios for mass production. For the applications in electronic devices, the NWs with high aspect ratios were demonstrated to be benecial to the carrier transport without encountering high-resistance NW contact.

4

To investigate the charge carrier transport properties of oxide NWs, their assembly into eld-eect transistor (FET) is one of the most eective routes.

2

FET is a three-terminal

device where the induced current between source and drain terminals can be controlled by gate terminal voltage. In modern electronic applications, FETs play critical roles in diverse elds, such as computers, at panel displays, memorizer, and chemical/bio/light/pressure sensors, etc.

Using thermal compression and calcination processes, Choi et al.

5

recently

demonstrated the rst high-performance electrospun oxide NW FETs based on In 2 O3 -ZnOZnGa2 O4 composites. Meanwhile, the authors demonstrated that the oxide network design was more suitable for practical applications compared to the a few number of NWs (e.g., 1, 2, and 4) because the increased number of NWs could provide more carrier transport pathways between source and drain (S/D) electrodes. Although enormous eorts have been made in the development of electrospun oxide NWs, the majority research works focused on the synthesis of n-type materials (such as In 2 O3 , ZnO, SnO, and their mixtures).

5,6

This undoubtedly impedes the further fabrication of p-n

junctions and complementary logic circuits where both n- and p-type semiconductors are necessary.

7

So the development of the p-type oxide NWs is urgent and essential. The main

obstacles for the p-type electrospun oxide NWs are due to: 1) the limited choices for p-type oxide semiconductors (i.e., Cu x O, SnO, and NiO); 2) the poor hole transport feature due to the large eective mass in valence band maximum; 3) the lack of ecient synthetic method for p-type oxide materials.

Among p-type oxide materials, NiO is a promising candidate

owing to its excellent photoelectric properties and chemical stability.

8

By combining ES and

sol-gel methods, the oxide NWs can be fabricated through the thermal calcination whereby the polymer template reagents can be decomposed.

9,10

In this process, by tuning the pre-

3



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cursor solutions and the experimental parameters during ES and calcination treatment, the component, size, and morphology of oxide NWs can be easily controlled. For the integration of large-area device arrays and circuits, a key challenge is to control the assembly of highly-ordered NWs, which enables the facile and reproducible fabrication process. In addition, the previous reports demonstrated that the devices based on aligned nanomaterials (i.e., carbon nanotubes and silver NWs) exhibited superior electrical performance compared to their disordered counterparts.

11,12

For the conventional ES process, the

as-fabricated composite NWs exhibit a chaotic whipping motion (bending instability) and arrange in random orientation because of the electrostatic force between the charges in the ejective solution and the external electric eld.

13

To control the alignment of electrospun

NWs, various assembly techniques have been developed, such as parallel electrode, rotating collector, and magnetic-eld-assisted method.

1416

Among these, parallel electrode mode

has been demonstrated to be the most reliable and straightforward route because it can collect uniaxially-aligned NWs and enable the facile transfer of NWs to other substrates simultaneously. Most recently, Elshof and coworkers successfully fabricated the aligned electrospun ZnO NWs between two parallel metal electrodes and their applications in FET and ultraviolet detectors were demonstrated.

17

However, as an n-type oxide semiconductor, the

2 low eld-eect mobility (0.018 cm /Vs) of the devices limits the further applications toward high-performance (opto)electronics and circuits. In this report, the p-type NiO NWs were fabricated using ES technique and the postcalcination eects on the NW properties were investigated using various characterization techniques.

The polyvinylpyrrolidone (PVP) was chosen as the polymer matrix due to

its high solubility and good compatibility with metal salts.

18

Instead of the conventional

thermal compression method, a simple UV photochemical treatment was employed in this study and the adhesion enhancement between the NWs and the substrate were demonstrated. To investigate the eect of the NW orientation on the device performance, the FETs with disordered and aligned NiO NWs were fabricated separately and the electrical properties were

4


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compared. The further integration of NiO NWs FETs based on high-k Al 2 O3 dielectrics were demonstrated and the enhanced device performance was achieved at low operating voltage.

2 Results and discussion The schematic illustration for fabricating NiO/PVP NWs by ES is shown in Figure 1a. The experimental details could be found in the Supporting Information. The as-spun NW networks are highly uniform and continuous, with a diameter of around 270 nm (Figure 1b).

For the application in FETs, the PVP polymer matrix in composite NWs should be

decomposed rst because the insulating PVP acts as the trap defects and impedes the carrier transport. To investigate the thermal decomposition behavior of NiO/PVP composite NWs during calcination process, the thermogravimetric and dierential scanning calorimetry (TG-DSC) analysis were carried out and the results are shown in Figure 2a. curve exhibits a three-step change in weight with a total loss of 90%. can be attributed to the decomposition of residual solvent. (II) at

∼270

precursor.

19

◦

The TG

The rst step (I)

The subsequent weight loss

C is mainly caused by the elimination of metal anions and volatile nitrate

The broad exothermic peak implies the decomposition of impurities and the

gradual densication behavior.

The signicant weight loss (III) at

thermal decomposition of PVP chains in the composite NWs.

9

∼400

◦

C is due to the

After this stage, the undesired

residuals were completely decomposed and metal-oxide framework was almost formed. The only change is the evolution of crystalline degree. Based on TG result, the post-annealing treatment at 550

◦

C is demonstrated to provide enough thermal energy and enable the

conversion from NiO/PVP composites to the phase-pure NiO NWs. The X-ray diraction (XRD) patterns of NiO/PVP composite NWs calcinated at dierent temperatures are shown in Figure 2b. It is observed that the as-spun NWs are amorphous in nature and the crystallinity of NWs is strongly dependent on the calcination temperature.

◦ ◦ ◦ ◦ The main diraction peaks observed at 37.2 , 43.6 , 62.8 , and 75.4 correspond to the (111),

5



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Figure 1:

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(a) The preparation methodology for the fabrication of electrospun NiO/PVP

NWs. (b) The scanning electron microscopy (SEM) images of the as-spun NiO/PVP NWs.

(200), (120), and (311) planes of face-centered cubic NiO structure (JCPDS card no.

47-

1049). The crystallinity of the NWs was enhanced with temperature, which is represented by the increased peak intensity and the decreased full width at half maximum of diraction peaks. By using Scherrer's formula (D = 0.9 λ/(βcos θ )), the crystallite size (D) of the NiO NWs annealed at 350, 450, 550, and 650

◦

11.8, 15.7, 22.5, and 26.1 nm, respectively.

C, based on (200) peak, was calculated to be The increased D value at higher temperature

also indicates the enhanced NW crystallinity. For the polycrystalline oxide materials, the enhanced crystallinity could lead to fewer grain boundaries. This can help to decrease the number of trapping center and the carrier scattering events, which is benecial to the carrier transport in the NWs. The compositional variations of NiO NWs before/after calcination were investigated using X-ray photoelectron spectroscopy (XPS) analysis, as shown in Figures 2c and 2d. For the as-spun NiO/PVP composite NWs, the main compositions are composed of Ni NiOOH (Ni 2p

3/2

at 856.3 eV and O 1s at 532.5 eV) and Ni 2 O3 (Ni 2p

at 530.9 eV). After calcination treatment at 550 Ni 2p

3/2

◦

3/2

3+

, such as

at 854.8 eV and O 1s

C, the content of metal-oxide bonds (NiO,

at 853.1 eV and O 1s at 528.9 eV) increased signicantly, indicating the occurrence

of condensation and alloying reactions. Meanwhile, most of the C- and N-related impurities, originating from PVP binder and precursor solution, were decomposed, as indicated in Figure

6


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2e.

Figure 2: a) TG-DSC curves of NiO/PVP composite NWs with a heating rate of 10

◦

C/min

in ambient air. (b) XRD patterns of NiO NWs calcinated at dierent temperatures. XPS 3/2 spectra of (c) Ni 2p , (d) O 1s, (e) C 1s and N 1s peaks of the as-spun NiO NWs and the ◦ NiO NWs calcinated at 550 C.

After post calcination process at 550

◦

C, the thorough decomposition of PVP binder and

the densication of NiO matrix lead to the signicantly decreased average NW diameter from 270 nm to 50 nm. However, it is found that most of the NWs peel o from the substrate (Figure 3a), which could be attributed to the signicant shrinkage of brous network and strong tensile stress during the high-temperature calcination process.

5,20

To achieve ideal

eld-eect performance, the NWs need enhanced adhesion properties with adjacent dielectric layer because the carrier transport is limited in the narrow region at NW/dielectric interface. To date, several approaches, such as the insertion of a buer layer

7


20

and thermal com-


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Figure 3: The SEM images of the 550

◦

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C-calcinated NiO NWs without (a) and with (b) UV-

assisted pretreatment. The inset in (b) shows the frequency distribution of NW diameters before/after thermal calcination. (c) Schematic illustration of the UV-assisted photochemical treatment. (d) Ultraviolet-visible absorption spectrum of NiO/PVP composite NWs.

pression,

5

have been attempted to enhance the substrate adhesion behavior.

However, in

order to achieve large-area device fabrication, these methods exhibit the complexity and increase the production cost. In this work, a simple and low-cost UV-assisted pretreatment was employed to enhance the adhesion properties between the NWs and substrate prior to thermal calcination (Figures 3b and 3c). In our recent work, the UV-assisted photochemical activation was demonstrated to eectively enhance the adhesion force of electrospun NW with the substrate.

6

UV irradiation enables the rapid generation of free radicals at carbonyl

(C=O) position of the PVP units, whereby the coupling with adjacent species is enhanced by a hydrogen abstraction reaction.

This leads to the cross-linking of the polymers and

surface grafting simultaneously in ambient air.

21

As shown in Figure 3d, the strong UV ab-

sorption of the as-spun NiO/PVP composite NWs indicates the eectiveness of UV-induced photochemical reaction. To further analyze the microstructure of the calcinated NiO NWs, an individual NW was investigated by using transmission electron microscopy (TEM) with dierent magnications, as shown in Figures 4a and 4b. The NiO NW is of highly crystalline and composed of a large

8


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number of small-sized NiO nanocrystals with an average grain size of

∼20 nm.

As revealed by

selected-area electron diraction (SAED) pattern in Figure 4c, the interplanar spacings along the (200) and (111) planes are 2.1 and 2.4 Å, which is well consistent with the crystalline structure of face-centered cubic NiO. In addition, there is no porous carbon coating observed in high resolution TEM (HRTEM) images, indicating the eective decomposition of PVP after 550

◦

C calcination and the achievement of phase-pure NiO NW.

Figure 4: (a) TEM, (b) HRTEM, and (c) SAED pattern images of an individual NiO NW ◦ calcinated at 550 C.

To explore the charge transport properties of the obtained NiO NWs, the NW networks with various channel coverage (10%, 23%, 55%, 70%, and 85%) were assembled into FETs on SiO2 /Si substrate (Figure 5a) by varying the NW collection time during the ES process. The corresponding optical microscopy images are shown in Figures 5b-f. The typical transfer curves and the key device parameters of the FETs are presented in Figure 5g and Table 1, respectively. The drain current ( IDS ) increased monotonically with negative gate voltage (VGS ), indicating the p-type semiconductor behaviour of NiO NWs. As the NiO NW channel coverage is increased from 10% to 71%, the maximum output current and on/o current ratio ( Ion /Iof f ) of the FETs improved signicantly while the o-state current ( Iof f ) is not substantially aected. The enhanced output current with coverage could be mainly attributed to the increased number of NiO NWs between S/D electrodes. For the FETs based on polycrystalline NWs, the increased number of channel stripes can lower grain boundary potential barriers, leading to the better gate control capability.

9


22

Meanwhile, the threshold


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voltage (VT H ) was found shifting positively from -10.0 V to 18.2 V, which could be ascribed to the increased number of holes and the hole transport pathways.

5

In this case, a larger

VGS

is needed to deplete the holes near the NiO NW/SiO 2 interface to achieve the o state of the FETs. The eld-eect mobility ( µF E ) of the devices as a function of channel coverage was calculated using parallel-plate capacitance model. improved signicantly to 10 optimized

µF E

−2

23

The results indicate that the

µF E

was

2 cm /Vs as the NW channel coverage increases to 71%. The

was found to be much higher than those previously reported FETs based on

ES p-type oxide NWs (Table 2), which could be attributed to two possible reasons. The rst one is due to the UV-enhanced adhesion properties between NiO NWs and dielectric layer; the other one is benecial from the good electrical contact of NWs with S/D electrodes. In previous reports, the p-type composite NWs were directly electrospun or transferred onto the S/D electrode-coated SiO 2 /Si substrates and then followed by high-temperature calcination.

2426

During the calcination process, the decomposition of PVP species and the

tensile stress between NWs and electrodes, generated by the calcination process, will lead to the NW exfoliation and thus the poor contact. This certainly limits the extraction of the induced charge carriers under electric eld and results in the degraded device performance. However, in this report, the NiO/PVP composite NWs were rst electrospun onto the SiO 2 /Si substrates and followed by the processes of UV treatment and high-temperature calcination. After the calcination process, the S/D electrodes were deposited onto NiO NWs to construct FETs. This guarantees the good physical contact between the deposited S/D electrodes and the NWs, which is benecial to achieve the devices with high performance. When the coverage of the NiO NWs exceeded ca. 85%, the current modulation capability of the device degraded dramatically with a small 3×10

−3

Ion /Iof f

ratio of 5×10

2

and a low

µF E

of

2 cm /Vs. This could be attributed to the change of structure from two-dimensional

network plane to three-dimensional spatial structure with the continuously increased NiO NW density. The overlapping of large amount of individual NWs leads to the uneven channel thickness and morphologies. Meanwhile, the upper overlapped NWs cannot contact the

10


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bottom dielectric directly but increase the bulk resistance, leading to the poor carrier modulation ability under the bias voltage.

Figure 5: (a) Device structure with disordered NiO NW network. (b-f ) Optical microscopy images of NiO NW network with dierent channel coverage (scale bar: 100

µm).

(g) Transfer

curves of the NiO NW FETs with dierent channel coverage ( VDS = 20 V).

Table 1: Electrical parameters of the FETs based on disordered and aligned NiO NWs with dierent NW channel coverage.

Orientation

µF E

Channel Coverage(±5%)

(cm /V s)

10%

8.8×10

23% Disordered

−4 −3

7.5×10 ∼10−2 ∼10−3

55% 71% 85%

Aligned

2

5%

18%

∼10−3 ∼10−2 6.5 × 10−2 7.0 × 10−2

45% 64% 82%

Ion /Iof f ∼10 5×102 ∼103 5×103 2 3 10 ∼10 ∼40 ∼103 6×103 ∼104 ∼104

VT H (V) -10.0 6.5 12.4 18.2 18.7 -9.5 8.0 13.0 18.5 19.0

The above results successfully demonstrated the electrospun p-type oxide NW FETs with controllable electrical properties for the rst time. However, the NiO NWs were arranged in random orientation due to the bending instability during the ES process. To further clarify the eect of NW orientation on the device performance, the highly-ordered NiO NW arrays

11



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Table 2: Recent achievements of the FETs based on electrospun oxide NWs on SiO 2 dielectric.

µF E

Sample

Type

InSnO (aligned)

n

0.45

ZnO

n

ZnGaO

n

2

(cm /V s)

Ion /Iof f 10

Operating voltage

3

100

2007

20

2008

40

2012

100

2013

∼107 ∼103

40

2014

20

2016

70

2016

40

2016

30

2017

10

−2

2.3 × 10

In2 O3

n

InGaZnO

n

4.04

ZnAlO

n

ZnO (aligned)

n

3.3 × 10−3 1.8 × 10−2

In2 O3

n

Year

(V)

4

∼103 7

Ref.

27 28 29 30 5 31 17 32 6

In2 O3

n

2.8

10

CuO

p

40

2006

LiNiO (aligned)

p

3.3 × 10−4

20

2014

ZnCeO

p

30

2014

NiO

p

0.01

25

This work

NiO (aligned)

p

0.07

5 × 103 ∼104

25

This work

33 25 24

with various channel coverage were collected using two high-conductive Si strips (Figure 6a).

17,34

As shown in Figures 6b-6g, the as-spun NiO/PVP composite NWs were arranged in

parallel and the NW density increased with the fabrication time. Meanwhile, the alignment of the NWs got slightly degraded with greater NW density, which was mainly caused by the increased electrostatic repulsions of the adjacent charged NWs. To investigate the electrical properties of those highly ordered NiO NWs, the suspended NiO/PVP NWs were transferred to SiO 2 /Si substrates and followed by the calcination at 550

◦

C. As illustrated in Figure 6h, the electrical properties of the aligned NiO NW FETs

were improved with higher NW channel coverage. 10

−2

, and 6.5×10

−2

The extracted

µF E

values were 10

−3

,

2 cm /V s for the devices with the NW coverage of 18%, 45%, and 64%,

respectively. This could be attributed to the increased number of free carriers associated with more conduction pathways between S/D electrodes. Interestingly, the device performance remains almost unchanged with further increase of NiO NW coverage. electrostatic simulations and the experiments, Dattoli et al.

By combining the

demonstrated that the NW

FETs with coverage over 60% in the channel exhibit similar electrical performance compared to those continuous planar thin-lm transistors with the same thickness.

12


35

With the increase

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Figure 6: (a) Schematic of aligned ES process.

(b) The FET structure with aligned NiO

NW arrays. (c-g) Optical microscope images of the aligned NiO/PVP NWs with dierent channel coverage (scale bar:

100

µm).

(h) The corresponding transfer characteristics of

aligned NiO NWs/SiO 2 FETs (VDS = 20 V). (i) The variation of

µF E

values for the FETs

based on disordered and aligned NiO NWs with dierent channel coverage.

of NW coverage, the eective capacitor area for each NW reduces, leading to the smaller gate capacitance ( Cw ) for a single NW. According to the formula g m = N

µF E Cw VDS /L2 ,

where gm is the transconductance and N is the NW number, the eects of the increase in NW number and the decrease in

Cw

per NW almost counterbalance each other and thus the

device performance no longer improves above a certain NW coverage. In addition, as indicated in Figure 6i and the output curves in Figure S1 (Supporting Information), the optimized FETs with aligned NiO NW arrays exhibit superior

µF E

com-

pared with their disordered counterparts. For the FETs with disordered NiO NW network, a fair amount of NWs have the similar orientation with the electrodes. In other words, this part of NWs does not connect with the S/D electrodes and thus would not participate in the electrical conduction. In addition, the quasi-planar structure of parallel NW arrays has much lower bulk resistivity compared with 3D architecture of disorder NW network in the vertical direction. This can help to improve gate modulation ecacy and be benecial to

13



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the carrier transport between the S/D electrodes. As shown in Table 2, the electrospun oxide NW FETs on SiO 2 dielectric were operated at large voltages ( ≥ 20 V), resulting in undesired power consumption. This is mainly due to the low permittivity (3.9) and thick thickness ( > 100 nm) of conventional SiO 2 gate dielectric.

The dangling bonds (hydroxyl groups) on the SiO 2 dielectric surface generally

act as the carrier traps, which can limit the device performance.

36

To achieve the low-

voltage high-performance FETs, it is necessary to fabricate the gate dielectrics with high permittivity or physically thin layer to enhance the capacitive coupling. Recently, Choi et al. reported the rst low-voltage electrospun oxide NW FETs using high-k MgBiZnNbO lm as gate dielectric.

5

However, the vacuum-based sputtering technique suers from the high

production cost and large-area lm nonuniformity. In contrast, the solution-based techniques exhibit more advantages such as simplicity, atmospheric processing, large-area uniformity, and low cost. Sc2 O3 ,

38

In our recent reports, series of oxide high-k dielectric lms (e.g., Li 2 O,

Al2 O3 ,

39

Y2 O3 ,

40

ZrO2 ,

41

and HfO2

42

37

) have been successfully achieved using spin-

coating method. The high-speed coating process enables the fabrication of dense and uniform thin oxide lms with smooth surface morphologies. Among these high-k materials, Al 2 O3 is regarded as one of the most promising dielectric candidates because of its relatively large permittivity ( ∼9), high crystallization temperature (1000

◦

C), low interface trap density,

and high chemical stability. In this study, to avoid the miscibility between the dielectric layer and NiO NWs during calcination, solution-processed Al 2 O3 dielectric thin lm (Figure 7a) was annealed at 600

◦

C. As shown in Figure 7b, the obtained Al 2 O3 thin lm is amorphous and exhibits smooth

surface morphology with a small root mean square (RMS) value of 0.25 nm.

The Al 2 O3

dielectric thin lm shows a large areal capacitance density ( Ci ) of 240 nF/cm

2

at 20 Hz,

which is 14 times larger than that of conventional SiO 2 dielectric (Figure 7c). For eld-eect devices, the gate dielectric with large areal capacitance can induce more carriers at semiconductor/dielectric interface at given electric eld, leading to the decreased operating voltage.

14


40

Page 15 of 24

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Figure 7: (a) Schematic diagram of solution-processed Al 2 O3 high-k dielectric layer. XRD pattern and AFM image of Al 2 O3 thin lm. (c) The and SiO2 thin lms. various

VDS

Jleak -E

and

C -f

(b)

curves of Al2 O3

(d) Transfer curves of aligned NiO NW FET on Al 2 O3 dielectric at

values (i.e., 2, 3, 4, and 5 V).

IDS

responses to a square wave signal applied to

the gate voltage at (e) 0.5 Hz and (f ) 100 Hz.

The small frequency variation ( ∼10 % deviation from 20 Hz to 100 kHz) of the capacitance indicates low defect density (i.e. hydroxyl group or/and oxygen vacancies) in Al 2 O3 dielectric lm. Meanwhile, the Al 2 O3 thin lm exhibits a low leakage current density ( Jleak ) of 1 nA/cm

2

rial, the

at 5 MV/cm, which is comparable to the thermal-grown SiO 2 . For dielectric mate-

Jleak

should be low enough to guarantee ecient switching characteristic and low

power consumption during device operation. Figure 7d shows the transfer characteristics of the aligned NiO NW FET with Al 2 O3 dielectric at various with the increase of

VDS

VDS .

The positive shift of

VT H

could be attributed to the existence of carrier traps in NiO NWs,

which leads to the channel narrowing eect arising from the surface depletion.

43

Although

some parameters of the NiO NW FETs with Al 2 O3 dielectric did not catch up with the ones on SiO2 (e.g., poor current saturation and high o-state current), the operation voltage was reduced signicantly from 25 V to 5 V by replacing SiO 2 with Al2 O3 . This is of great interest for the applications in low-power consumption devices. The corresponding output

15



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curves are shown in Figure S2 in Supporting Information.

The

Page 16 of 24

µF E

of NiO NW/Al 2 O3

2 FET was calculated to be 2.8 cm /Vs, which is around 40 times larger than the devices based on SiO 2 . When the highly capacitive Al 2 O3 dielectric was employed, a large number of induced charge carriers compensated the trap states in NiO NWs and consequently the undesirable inuence of defects on the carrier transport along the NiO NWs was suppressed. To clarify the interface quality between NiO NWs and two dierent dielectric layers, the interfacial trap concentration

38

was calculated. The results show that the NiO NW/Al 2 O3

FETs exhibit higher interfacial trap concentration ( ∼10 dielectric (5×10

12

cm−2 ),

13

cm−2 )

than the devices on SiO 2

which indicates that the further device optimization is required

via interfacial engineering. Besides the improved

µF E ,

the NiO NW/Al 2 O3 FET exhibits a large

with a high on-state current ( Ion ) of 20

achieve the fast switching speed (1/ τ delay

∝ Ion /W; τ delay

Ion

4

is highly required to

= switch delay). To clarify the

dynamic behaviors of low-voltage aligned NiO NW/Al 2 O3 FET, the

IDS

of 6×10

µA. In practical integrated circuits (ICs), transistors

play a critical role in switching units and the device with high

was measured and the typical

Ion /Iof f

IDS

response over time

response and the clear on/o state of the

observed, as shown in Figures 7e and 7f. Based on the high

IDS

could be

Ion of NiO NW/Al2 O3 FETs, their

applications as driving unit for light-emitting diode (LED) was further explored to evaluate the current controlling capability of the device. p-channel FETs with large

Ion

and

Ion /Iof f

For the practical applications in LEDs,

are considered to possess priorities compared

to the n-type counterpart because of the bottom hole injection electrode structures.

44,45

To

prove the above concept, we fabricated a prototyping model of green-light LED pixel circuit (Figure S3a in Supporting Information). Pictures in Figure S3b show that the modulation of LED light emission intensity over a wide range could be achieved through scanning gate voltage, which demonstrates high current control capability of p-type NiO NW/Al 2 O3 FETs. To the best of our knowledge, this is the rst report demonstrating the LED driven ability using FETs based on electrospun oxide NWs.

16


Page 17 of 24

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3 Conclusion In summary, the p-type NiO NWs was fabricated by electrospinning the polymeric solution and subsequent calcination process. The crystalline, component, and diameter of the NiO NWs could be easily controlled by adjusting post-calcination condition. The FETs based on 550

◦

C-calcinated NiO NWs exhibit the typical p-channel transistor characteristic with good

current modulation capability.

Compared with the disordered NiO NW FETs, the device

based on aligned NiO arrays exhibited an improved electrical performance with a

2 cm /Vs and an

Ion /Iof f

ratio of

∼104 .

µF E

of 0.07

The device performance could be further optimized by

dielectric engineering by introducing high-k Al 2 O3 as the gate dielectric instead of SiO 2 . The aligned-NiO NW/Al 2 O3 FET was demonstrated to possess a high

Ion /Iof f

µF E

2 of 2.8 cm /Vs, a large

4 of 6×10 , a low operating voltage of 5 V, fast switching speed, and LED driving

capability. Considering the low-voltage and high-performance characteristics as well as the low-cost involved in this study, the NiO NW-based devices show great potential applications in complementary logic circuitry and next-generation chemical/biological sensors.

Notes The authors declare no competing nancial interest.

Acknowledgement This work was supported by Natural Science Foundation of China (Grant no. 51572135, and 51672142).

17


51472130,


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Supporting Information Available Detailed experimental section and material characterizations; Figure S1: output curves of (a) disordered (channel coverage: 70%) and (b) aligned (channel coverage: 65%) NiO NW FETs; Figure S2: output curves of aligned NiO NW/Al 2 O3 FET; Figure S3: (a) Circuit diagram of a green LED driven by NiO NW/Al 2 O3 FET. (b) Photographs of LED with various light intensity modulated by varying

VGS .

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Appl.


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Graphical TOC Entry

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Electrospun p-Type Nickel Oxide Semiconducting Nanowires for Low

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