Electrothermal Annealing (ETA) Method to Enhance the Electrical

Aug 23, 2016 - Atomic-layer-deposition-assisted ZnO nanoparticles for oxide charge-trap memory thin-film transistors. Gi Ho Seo , Da Jeong Yun , Won H...
0 downloads 0 Views 2MB Size
Download PDF
Research Article www.acsami.org

Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs) Choong-Ki Kim,†,‡ Eungtaek Kim,†,‡ Myung Keun Lee,‡ Jun-Young Park,‡ Myeong-Lok Seol,§ Hagyoul Bae,‡ Tewook Bang,‡ Seung-Bae Jeon,‡ Sungwoo Jun,⊥ Sang-hee K. Park,∥ Kyung Cheol Choi,‡ and Yang-Kyu Choi*,‡ ‡

School of Electrical Engineering (EE), Korea Advanced Institution of Science and Technology (KAIST), Daejeon 34141, Republic of Korea § NASA Ames Research Center, Moffett Field, California 94035, United States ⊥ College of Engineering, Korea University, Seoul 136-713, Republic of Korea ∥ Department of Material Science and Engineering, KAIST, Daejeon 34141, Republic of Korea S Supporting Information *

ABSTRACT: An electro-thermal annealing (ETA) method, which uses an electrical pulse of less than 100 ns, was developed to improve the electrical performance of array-level amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). The practicality of the ETA method was experimentally demonstrated with transparent amorphous In−Ga− Zn-O (a-IGZO) TFTs. The overall electrical performance metrics were boosted by the proposed method: up to 205% for the trans-conductance (gm), 158% for the linear current (Ilinear), and 206% for the subthreshold swing (SS). The performance enhancement were interpreted by X-ray photoelectron microscopy (XPS), showing a reduction of oxygen vacancies in a-IGZO after the ETA. Furthermore, by virtue of the extremely short operation time (80 ns) of ETA, which neither provokes a delay of the mandatory TFTs operation such as addressing operation for the display refresh nor demands extra physical treatment, the semipermanent use of displays can be realized. KEYWORDS: electrothermal annealing (ETA), Joule heat, amorphous-oxide-semiconductor (AOS), In−Ga−Zn-O (IGZO), thin-film transistor (TFT) luminance of 20% can be distorted by a VT shift of ±0.1 V.11 Various passivation techniques12−16 or post-treatment methods16−21 to enhance reliability of a-IGZO TFTs have been intensively developed and reported. However, such approaches have a number of problems when used in practical applications. First of all, these methods require a lot of time, e.g. at least 1 h, and additional facilities that can have high temperature or extraordinary environments. Otherwise, supplemental process steps for illumination filters14,16 or reflectors13 must be inserted in the TFTs process. The additions directly influence to increase of end product cost. Furthermore, after OLED layers are formed on the TFTs layer, an additional high-temperature annealing step cannot be done because of the low thermal stability of the organic materials.22 In the same manner, when the degradations of electrical performance of AOS TFTs

1. INTRODUCTION Amorphous-oxide-semiconductors (AOS) have been recognized materials for active layer in thin-film transistors (TFTs) mounted in display backplanes due to their inherent amorphous properties, which are closely related to their high device-to-device uniformity. 1,2 Among AOS types, the amorphous In−Ga−Zn-O (a-IGZO) is one of the most promising materials in the current display industry because of its sufficient mobility (10−30 cm2/(V s)),3−5 low off-state current,6 low process temperature,7 process compatibility8 with conventional poly silicon TFTs, and wide bandgap (3−3.05 eV).9,10 Particularly, the wide bandgap promotes high transparency of TFTs in the visible range. However, for future display applications, the reliability of a-IGZO TFTs that work in harsh conditions of outdoor places with elevated temperatures and high illumination levels becomes increasingly important. For example, the luminance of active-matrix organic light-emitting diodes (AMOLEDs) is extremely sensitive to even a small threshold voltage (VT) variation of the TFTs; © 2016 American Chemical Society

Received: May 28, 2016 Accepted: August 23, 2016 Published: August 23, 2016 23820

DOI: 10.1021/acsami.6b06377 ACS Appl. Mater. Interfaces 2016, 8, 23820−23826

Research Article

ACS Applied Materials & Interfaces

Figure 1. Device information. (a) a schematic of a transparent a-IGZO TFT in a bird’s eye view when VETA is applied; (b) cross-section schematic (A−A′); (c) cross-sectional transmission electron microscopy (TEM) image of the active region (B−B′) with scale bar of 20 nm; and (d) measured transmittance of a TFT sample (area ∼4 in.2) at various wavelengths.

2. EXPERIMENTAL SECTION

happens in the display operation, recovery of them cannot be guaranteed by the post-treatment methods. In this respect, the electro-thermal annealing (ETA) technique introduced in this work has numerous merits; the electrical performances of AOS TFTs, which went through optimized annealing steps in fabrication flow can be increased within an extremely short time (80 ns) through a local ETA method without additional processes or post-treatment steps. Furthermore, the in situ ETA recovers the electrical performance of TFTs degraded by environmental stress within extremely short time when they are in the display operation. Herein, the cost-effective ETA method is demonstrated for transparent (∼90% of transmittance) a-IGZO devices that have few-μm gate length (5 μm) and their array structures. Actually, the ETA method showed good efficacy in three-dimensional Sibased metal-oxide-semiconductor field-effect-transistors (MOSFETs) but was not feasible for use in extremely scaled array schemes.23 The ETA method requires an additional gate pad to apply voltage in order to flow currents and generate Joule heat on the gate insulator (GI)/active layer (IGZO). Because tight area restriction are not strongly desired in application of TFTs such as display panels, the ETA method which should be implemented utilizing built-in local heaters (e.g., additional gate pads) can be more feasible to the field of TFTs than that of extremely scaled Si-based complementary metal-oxide-semiconductor (CMOS). By applying the ETA method, the pristine electrical characteristics of a-IGZO TFTs are greatly enhanced and negative-bias-illumination stress (NBIS) in a-IGZO TFTs can be recovered. Post-ETA samples show reduced oxygen (O) 1s subpeak (∼531 eV) in X-ray photoelectron spectroscopy (XPS) analyses, proportional to the number of oxygen vacancies in the a-IGZO.24−26 Furthermore, because the ETA method uses Joule heating across two gate pads assigned as G1 and G2, several tied-array-structure TFTs can be boosted by a single 80 ns-long ETA process.

2.1. Fabrication of the IGZO TFTs. The a-IGZO TFTs with a top-gate bottom-contact (TGBC) structure were fabricated on glass substrates for OLED according to the process flow introduced in our previous work27 and shown in Figure S1 and Table S1. The prepared a-IGZO TFTs are illustrated in Figure 1a, b. A 9 nm thick first GI layer (Al2O3) was used to protect the active layer surface when pattering the active region. The total GI after the entire process is composed of 40 nm-thick Al2O3 deposited by atomic layer deposition (ALD), as shown in Figure 1c. Breakdown voltage (VBD) of 40 nm-thick Al2O3 was larger than 30 V (corresponding to electric field of 7.6 MV/cm) when it was tested with metal−insulator−metal (MIM) structure. The gate and source/drain electrodes metal is indium−tin-oxide (ITO). The gate length (LG) and channel width (W) range from 5 to 20 μm. To obtain the best electrical performance, we optimized the thermal annealing temperature and time. The fabricated samples have transparency of approximately 90%, as shown in Figure 1d. 2.2. Electrical and Chemical Measurements. All electrical measurements of the a-IGZO TFTs were performed using a HP4156C parameter analyzer in an ambient atmosphere. VD values of 0.5 V were used to obtain the linear-state transfer curve according to a gate voltage (VG) range of −2 to 10 V. In order to observe the NBIS stability of the a-IGZO TFTs, a VG of −10 V, corresponding to a vertical electric field (E-field) of 2.5 MV/cm, was applied to G1, whereas G2 was synchronized with G1 bias and the S/D connections were grounded. Illumination was provided by a halogen ramp whose intensity is 13 mW/cm2 at wavelength of 300 nm. Meanwhile, to apply ETA to the a-IGZO TFTs, ETA voltages (VETA) with identical absolute amplitudes but opposite signs, e.g., ± 5 V, were separately applied to G1 and G2 so that the active center would have a zero vertical E-field. Furthermore, for an extremely short electrical pulse (1 h), ETA can be easily utilized by applying voltage to fabricated AOS TFTs without additional time requirements or extraordinary equipment. Therefore, in situ ETA can be implemented to address TFTs using a single electrical pulse assuming that the layout is slightly revised, as shown in Figure 7a. Because of the lack of tight area restrictions in display layouts thus far, metal lines with widths of a few micrometers for connections of the G2 strings can be readily inserted. Metal lines that have high transparency and low level resistance are preferred for transparent display products with smaller RC constant. Additional bias lines for mode selection (MS), i.e., VMS, are supplemented for G2 strings in the proposed layout. The addition of G2 strings would not be a critical bottleneck or penalty in current TFT process technologies because it can be interposed without deterioration of transparency and display resolution by use of half-pitch bias lines. When VMS is set to be synchronized with the signal bias (VS(t)), normal operation (mandatory addressing works) becomes feasible. On the other hand, when VMS is grounded or in cases of −VETA, ETA can be conducted by applying VETA to a conventional VS (t) line. The experimental demonstration of ETA in array-structure a-IGZO TFTs shows the good possibility of realizing the scheme proposed above. Five aIGZO TFTs arrayed with Cr/Au metal lines as shown in Figure 7b could be improved by a 1 μs long ETA pulse simultaneously. Figure 7c shows the uniformly improved electrical performance metrics (gm,max, Ilinear, and SS) while demonstrating the sufficient feasibility of the ETA method in TFTs array. However, for electrical improvement of the single ETA pulse in an array including more than five TFTs, further RC constant reduction of the bias lines and optimization of ETA conditions (e.g., VETA, tETA) should be performed. Fortunately, the research stream to reduce the RC constant for minimization of the refresh period, has been developed. It could be a very helpful milestone for increasing the number of TFTs that can be recovered by the

single ETA. The corresponding pristine transfer curves are in Figure S5. As displays are more commonly moved from indoors to outdoors, device operation under harsh environmental stress conditions, such as those with high illumination levels and elevated temperatures should harness satisfactory stability in such an environment. Our a-IGZO TFTs showed perfect stability in accelerated tests of the positive-bias-illumination stress (PBIS), positive-bias-temperature stress (PBTS), negative-bias-temperature stress (NBTS), as shown in in the Figure S6 and Table S4. In contrast to these outcomes, the electrical characteristics were distorted by NBIS when the stress time was extended (Figure S6b). Although a partial recovery of the NBIS stress can be achieved under room temperature after sufficient time (natural recovery), complete recovery should be attained with high temperature annealing in almost types of TFTs.14,40 Furthermore, the natural recovery requires a lot of time, approximately hundred order of magnitude seconds. However, the degraded and/or distorted electrical characteristics could be recovered by ETA within 1 μs, as shown in the Figure S7. Therefore, NBIS recovery can be another key application of ETA because the origin of NBIS is also well-known as Vo.24 Moreover, the iterative recovery of NBIS for the permanent usage of a-IGZO TFTs even under harsh environmental conditions can be actualized when the amount of NBIS does not exceed a specific level, as shown in Figure 7d. The VON value was defined as VG when ID is 20 pA. When a-IGZO TFTs undergo ETA, they show greater immunity to NBIS. The initial a-IGZO TFTs showed a SS degradation of 132 mV/dec after 10 s in the NBIS condition, whereas the ETA-treated a-IGZO TFTs showed only degradation of 54 mV/dec with the same amount of NBIS. Furthermore, the electrical characteristics improved by ETA were maintained for at least 20 days in an idle state, as shown in Figure 7e.

4. CONCLUSION An electrothermal annealing (ETA) technique involving only an extremely short electrical pulse is proposed for the enhancement of the electrical performance capabilities of amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). Using ETA with an ETA time (tETA) of 80 ns, the 23824

DOI: 10.1021/acsami.6b06377 ACS Appl. Mater. Interfaces 2016, 8, 23820−23826

Research Article

ACS Applied Materials & Interfaces

Composition on the Electrical Performance of Thin-film Transistors. Mater. Chem. Phys. 2011, 131, 512−518. (6) Hayashi, R.; Sato, A.; Ofuji, M.; Abe, K.; Yabuta, H.; Sano, M.; Kumomi, H.; Nomura, K.; Kamiya, T.; Hirano, M. In 42.1: Invited Paper: Improved Amorphous In-Ga-Zn-O TFTs. Dig. Tech. Pap.- Soc. Inf. Disp. Int. Symp. 2008, 39, 621−624. (7) Lee, M. H.; Shih, C. C.; Chen, J. S.; Huang, W. M.; Gan, F. Y.; Shih, Y. C.; Qiu, C. X.; Shih, I. In 15.4: Excellent Performance of Indium-Oxide-Based Thin-Film Transistors by DC Sputtering. Dig. Tech. Pap. - Soc. Inf. Disp. Int. Symp. 2009, 40, 191−193. (8) Hsieh, H. H.; Lu, H. H.; Ting, H. C.; Chuang, C. S.; Chen, C. Y.; Lin, Y. Development of IGZO TFTs and Their Applications to Nextgeneration Flat-panel Displays. J. Inf. Disp. 2010, 11, 160−164. (9) Nomura, K.; Ohta, H.; Ueda, K.; Kamiya, T.; Hirano, M.; Hosono, H. Thin-film Transistor Fabricated in Single-crystalline Transparent Oxide Semiconductor. Science 2003, 300, 1269−1272. (10) Lee, S.; Park, J.-H.; Jeon, K.; Kim, S.; Jeon, Y.; Kim, D. H.; Kim, D. M.; Park, J. C.; Kim, C. J. Modeling and Characterization of Metalsemiconductor-metal-based Source-drain Contacts in Amorphous InGaZnO Thin Film Transistors. Appl. Phys. Lett. 2010, 96, 113506. (11) In, H.-J.; Kwon, O.-K. External Compensation of Nonuniform Electrical Characteristics of Thin-film Transistors and Degradation of OLED Devices in AMOLED Displays. IEEE Electron Device Lett. 2009, 30, 377−379. (12) Park, J. H.; Kim, Y.-g.; Yoon, S.; Hong, S.; Kim, H. J. Simple Method to Enhance Positive Bias Stress Stability of In−Ga−Zn−O Thin-Film Transistors Using a Vertically Graded Oxygen-Vacancy Active Layer. ACS Appl. Mater. Interfaces 2014, 6, 21363−21368. (13) Kim, E.; Jang, W. J.; Kim, W.; Park, J.; Lee, M. K.; Park, S.-H. K.; Choi, K. C. Suppressed Instability of a-IGZO Thin-Film Transistors Under Negative Bias Illumination Stress Using the Distributed Bragg Reflectors. IEEE Trans. Electron Devices 2016, 63, 1066−1071. (14) Chang, S.; Do, Y. S.; Kim, J. W.; Hwang, B. Y.; Choi, J.; Choi, B. H.; Lee, Y. H.; Choi, K. C.; Ju, B. K. Photo-Insensitive Amorphous Oxide Thin-Film Transistor Integrated with a Plasmonic Filter for Transparent Electronics. Adv. Funct. Mater. 2014, 24, 3482−3487. (15) An, S.; Mativenga, M.; Kim, Y.; Jang, J. Improvement of Biasstability in Amorphous-indium-gallium-zinc-oxide Thin-film Transistors by using Solution-processed Y2O3 Passivation. Appl. Phys. Lett. 2014, 105, 053507. (16) Yamada, K.; Nomura, K.; Abe, K.; Takeda, S.; Hosono, H. Examination of the Ambient Effects on the Stability of Amorphous Indium-gallium-zinc oxide Thin Film Transistors using a Laser-glasssealing Technology. Appl. Phys. Lett. 2014, 105, 133503. (17) Jeong, H.-y.; Lee, B.-y.; Lee, Y.-j.; Lee, J.-i.; Yang, M.-s.; Kang, I.b.; Mativenga, M.; Jang, J. Coplanar Amorphous-indium-gallium-zincoxide Thin Film Transistor with He Plasma Treated Heavily Doped Layer. Appl. Phys. Lett. 2014, 104, 022115. (18) Tak, Y. J.; Yoon, D. H.; Yoon, S.; Choi, U. H.; Sabri, M. M.; Ahn, B. D.; Kim, H. J. Enhanced Electrical Characteristics and Stability via Simultaneous Ultraviolet and Thermal Treatment of Passivated Amorphous In−Ga−Zn−O Thin-Film Transistors. ACS Appl. Mater. Interfaces 2014, 6, 6399−6405. (19) Yoon, S.; Tak, Y. J.; Yoon, D. H.; Choi, U. H.; Park, J.-S.; Ahn, B. D.; Kim, H. J. Study of Nitrogen High-Pressure Annealing on InGaZnO Thin-Film Transistors. ACS Appl. Mater. Interfaces 2014, 6, 13496−13501. (20) Fuh, C.-S.; Liu, P.-T.; Huang, W.-H.; Sze, S. M. Effect of Annealing on Defect Elimination for High Mobility Amorphous indium-zinc-tin-oxide thin-film transistor. IEEE Electron Device Lett. 2014, 35, 1103−1105. (21) Liu, X.; Wang, L. L.; Hu, H.; Lu, X.; Wang, K.; Wang, G.; Zhang, S. Performance and Stability Improvements of Back-ChannelEtched Amorphous Indium−Gallium−Zinc Thin-Film-Transistors by CF4+O2 Plasma Treatment. IEEE Electron Device Lett. 2015, 36, 911− 913. (22) Miura, K.; Ueda, T.; Nakano, S.; Saito, N.; Hara, Y.; Sugi, K.; Sakano, T.; Yamaguchi, H.; Amemiya, I.; Akimoto, K.; et al. In 4.1: Low-Temperature-Processed IGZO TFTs for Flexible AMOLED with

electrical performance of transparent amorphous In−Ga−Zn− O (a-IGZO) TFTs was successfully enhanced. The ETA time (tETA) and ETA voltage (VETA) were optimized by considering the addressing time in state-of-the-art 4k ultra-high-definition (UHD) displays and the stability of the annealing temperature in the a-IGZO channel. ETA lasting for 1 μs showed the greatest improvement of the electrical characteristics and satisfied the speed requirements of UHD displays. The improvement by ETA could be interpreted as occurring through a reduction of the bulk trap density-of-states (DOS) originating from the oxygen-deficient condition (Vo). The reduction of Vo was directly observed by an X-ray photoelectron spectroscopy (XPS) analysis. Attributed to the simplicity of ETA, the electrical characteristics of five arrayed a-IGZO TFTs were uniformly boosted using a single ETA pulse. Furthermore, the accumulated negative-bias-illumination stress (NBIS) damage in a-IGZO TFTs was fully repaired by ETA, demonstrating its potential for use in iterative manner for the semipermanent operation of TFTs.

■

ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b06377. Detailed process flow for a-IGZO TFTs, parameter values for COMSOL simulation, and detailed results of environmental stress test with a-IGZO TFTs (PDF)

■

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Phone: +82-42-350-3477 Author Contributions †

C.-K.K. and E.K. contributed equally to this work.

Notes

The authors declare no competing financial interest.

■

ACKNOWLEDGMENTS This research was supported by the Open Innovation Lab Project from National Nanofab Center (NNFC) and the IT R&D program of MSIP/IITP. [R-20150224-000291, Development on Semiconductor based Smart Antenna for future mobile communications]. This work was also supported by the IDEC (EDA Tool, MPW).

■

REFERENCES

(1) Chiang, H.; Wager, J.; Hoffman, R.; Jeong, J.; Keszler, D. A. High Mobility Transparent Thin-film Transistors with Amorphous Zinc Tin Oxide Channel Layer. Appl. Phys. Lett. 2005, 86, 013503. (2) Hosono, H. Ionic Amorphous Oxide Semiconductors: Material design, Carrier Transport, and Device Application. J. Non-Cryst. Solids 2006, 352, 851−858. (3) Yabuta, H.; Sano, M.; Abe, K.; Aiba, T.; Den, T.; Kumomi, H.; Nomura, K.; Kamiya, T.; Hosono, H. High-mobility Thin-film Transistor with Amorphous InGaZnO4 Channel Fabricated by Room Temperature RF-magnetron Sputtering. Appl. Phys. Lett. 2006, 89, 112123. (4) Kim, M.; Jeong, J. H.; Lee, H. J.; Ahn, T. K.; Shin, H. S.; Park, J.S.; Jeong, J. K.; Mo, Y.-G.; Kim, H. D. High Mobility Bottom Gate InGaZnO Thin Film Transistors with SiOx Etch Stopper. Appl. Phys. Lett. 2007, 90, 212114. (5) Olziersky, A.; Barquinha, P.; Vila, A.; Magana, C.; Fortunato, E.; Morante, J.; Martins, R. Role of Ga2O3−In2O3−ZnO Channel 23825

DOI: 10.1021/acsami.6b06377 ACS Appl. Mater. Interfaces 2016, 8, 23820−23826

Research Article

ACS Applied Materials & Interfaces Integrated Gate Driver Circuits. Dig. Tech. Pap. - Soc. Inf. Disp. Int. Symp. 2011, 42, 21−24. (23) Park, J.-Y.; Moon, D.-I.; Seol, M.-L.; Kim, C.-K.; Jeon, C.-H.; Bae, H.; Bang, T.; Choi, Y.-K. Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced From Hot-Carrier Injection. IEEE Trans. Electron Devices 2016, 63, 910−915. (24) Ryu, B.; Noh, H.-K.; Choi, E.; Chang, K. O-vacancy as the Origin of Negative Bias Illumination Stress Instability in Amorphous In-Ga-Zn-O Thin Film Transistors. Appl. Phys. Lett. 2010, 97, 022108. (25) Oh, H.; Yoon, S.-M.; Ryu, M. K.; Hwang, C.-S.; Yang, S.; Park, S.-H. K. Photon-accelerated Negative Bias Instability Involving Subgap States Creation in Amorphous In−Ga−Zn−O Thin Film Transistor. Appl. Phys. Lett. 2010, 97, 183502. (26) Chowdhury, M. D. H.; Migliorato, P.; Jang, J. Temperature Dependence of Negative Bias under Illumination Stress and Recovery in Amorphous Indium Gallium Zinc Oxide Thin Film Transistors. Appl. Phys. Lett. 2013, 102, 143506. (27) Kim, E.; Kim, C.-K.; Lee, M. K.; Bang, T.; Choi, Y.-K.; Park, S.H. K.; Choi, K. C. Influence of the Charge Trap Density Distribution in a Gate Insulator on the Positive-bias Stress Instability of Amorphous Indium-gallium-zinc Oxide Thin-film Transistors. Appl. Phys. Lett. 2016, 108, 182104. (28) Chang, Y.-G.; Moon, T.-W.; Kim, D.-H.; Lee, H. S.; Kim, J. H.; Park, K.-S.; Kim, C.-D.; Im, S. DC versus Pulse-Type Negative Bias Stress Effects on the Instability of Amorphous InGaZnO Transistors under Light Illumination. IEEE Electron Device Lett. 2011, 32, 1704− 1706. (29) Bae, H.; Jun, S.; Jo, C. H.; Choi, H.; Lee, J.; Kim, Y. H.; Hwang, S.; Jeong, H. K.; Hur, I.; Kim, W.; Yun, D.; Hong, E.; Seo, H.; Kim, D. H.; Kim, D. M. Modified Conductance Method for Extaction of Subgap Density of States in a-IGZO Thin-film Transistors. IEEE Electron Device Lett. 2012, 33, 1138−1140. (30) Bae, H.; Seo, H.; Jun, S.; Choi, H.; Ahn, J.; Hwang, J.; Lee, J.; Oh, S.-M.; Bae, J.-U.; Choi, S.-J.; et al. Fully Current-based Subbandgap Optoelectronic Differential Ideality Factor Technique and Extraction of Subgap DOS in Amorphous Semiconductor TFTs. IEEE Trans. Electron Devices 2014, 61, 3566−3569. (31) Jun, S.; Jo, C.; Bae, H.; Choi, H.; Kim, D. H.; Kim, D. M. Unified Subthreshold Coupling Factor Technique for Surface Potential and Subgap Density-of-states in Amorphous Thin Film Transistors. IEEE Electron Device Lett. 2013, 34, 641−643. (32) Gan, J.; Lu, X.; Wu, J.; Xie, S.; Zhai, T.; Yu, M.; Zhang, Z.; Mao, Y.; Wang, S. C. I.; Shen, Y.; Tong, Y. Oxygen Vacancies Promoting Photoelectrochemical Performance of In2O3 Nanocubes. Sci. Rep. 2013, 3, 1021. (33) Chen, W.-T.; Lo, S.-Y.; Kao, S.-C.; Zan, H.-W.; Tsai, C.-C.; Lin, J.-H.; Fang, C.-H.; Lee, C.-C. Oxygen-dependent Instability and Annealing/passivation Effects in Amorphous In−Ga−Zn−O Thin-film Transistors. IEEE Electron Device Lett. 2011, 32, 1552−1554. (34) Kang, J. H.; Cho, E. N.; Kim, C. E.; Lee, M.-J.; Lee, S. J.; Myoung, J.-M.; Yun, I. Mobility Enhancement in Amorphous InGaZnO Thin-film Transistors by Ar Plasma Treatment. Appl. Phys. Lett. 2013, 102, 222103. (35) Chen, M.; Pei, Z.; Sun, C.; Wen, L.; Wang, X. Surface Characterization of Transparent Conductive Oxide Al-doped ZnO Films. J. Cryst. Growth 2000, 220, 254−262. (36) Kamiya, T.; Nomura, K.; Hirano, M.; Hosono, H. Electronic Structure of Oxygen Deficient Amorphous Oxide Semiconductor aInGaZnO4−x: Optical Analyses and First-Principle Calculations. Phys. Status Solidi C 2008, 5, 3098−3100. (37) Noh, H.-K.; Chang, K.; Ryu, B.; Lee, W.-J. Electronic Structure of Oxygen-vacancy Defects in Amorphous In-Ga-Zn-O Semiconductors. Phys. Rev. B: Condens. Matter Mater. Phys. 2011, 84, 115205. (38) Noh, H.-K.; Chang, K. J.; Ryu, B.; Lee, W.-J. Electronic structure of oxygen-vacancy defects in amorphous In-Ga-Zn-O semiconductors. Phys. Rev. B: Condens. Matter Mater. Phys. 2011, 84, 115205.

(39) Hsieh, H.-H.; Kamiya, T.; Nomura, K.; Hosono, H.; Wu, C.-C. Modeling of amorphous InGaZnO4 thin film transistors and their subgap density of states. Appl. Phys. Lett. 2008, 92, 133503. (40) Ryu, B.; Noh, H.-K.; Choi, E.-A.; Chang, K. J. O-vacancy as the Origin of Negative Bias Illumination Stress Instability in Amorphous In-Ga-Zn-O Thin Film Transistors. Appl. Phys. Lett. 2010, 97, 022108.

23826

DOI: 10.1021/acsami.6b06377 ACS Appl. Mater. Interfaces 2016, 8, 23820−23826