Enabling Energy Efficiency and Polarity Control in Germanium

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions Jens Trommer,*,†,‡ André Heinzig,‡,§ Uwe Mühle,∥,⊥ Markus Löffler,‡,∥ Annett Winzer,† Paul M. Jordan,† Jürgen Beister,† Tim Baldauf,‡,§ Marion Geidel,‡,§ Barbara Adolphi,§ Ehrenfried Zschech,⊥ Thomas Mikolajick,†,‡,§ and Walter M. Weber†,‡ †

NaMLab gGmbH, Noethnitzer Straße 64, D-01187 Dresden, Germany Center for Advancing Electronics Dresden (CfAED), TU Dresden, D-01062 Dresden, Germany § Institute of Semiconductor and Microsystems (IHM), TU Dresden, D-01062 Dresden, Germany ∥ Dresden Center for Nanoanalysis (DCN), TU Dresden, D-01062 Dresden, Germany ⊥ Fraunhofer Institute for Ceramic Technologies and Systems (IKTS), D-01277 Dresden, Germany ‡

S Supporting Information *

ABSTRACT: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the offstate leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finiteelement drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems. KEYWORDS: germanium nanowire, low-band-gap, ambipolar transistors, Schottky barrier, reconfigurable field effect transistors, reprogrammable logic, polarity control, multigate, junction leakage suppression, temperature-dependent measurement

I

This is especially true for emerging nanoscale device concepts, which often feature metal-to-semiconductor Schottky junctions at the source/drain contacts.6,7 Indeed it has been established that for such ultrascaled Schottky-junction-based transistors the maximal possible on/off current ratio is given solely by the band-gap energy EG of the channel material:8

n order to further increase the transistor performance, high-mobility materials are envisioned to replace silicon as channel material in future complementary oxide semiconductor (CMOS) technology.1 Among the common semiconductor materials, germanium is one of the most promising candidates for future p-channel transistors, as it offers the highest hole mobility within the bulk material and an electron mobility that is twice that of silicon.2−5 However, three key challenges have prevented a widespread application of germanium so far:4 first, the cost-effective integration of highquality germanium thin films on silicon wafers; second, the formation of high-quality gate dielectrics with low equivalent oxide thickness (EOT) due to the instable nature of its native oxide; and third, the high amount of static power dissipation arising from high reverse junction leakage currents, which are related to its comparatively low band-gap energy of 0.66 eV. While the first two challenges are mainly of manufactural nature, the high leakage current poses a fundamental problem. © 2017 American Chemical Society

ION 1 ≈ e(EG /2kBT ) IOFF 4

(1)

whereby T is the temperature and kB the Boltzmann constant. For germanium eq 1 gives a ratio of 105 at room temperature. This effect and the resulting high static power dissipation practically hinder the application of low-band-gap semiReceived: November 9, 2016 Accepted: January 12, 2017 Published: January 12, 2017 1704

DOI: 10.1021/acsnano.6b07531 ACS Nano 2017, 11, 1704−1711

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Figure 1. Back-gated germanium nanowire Schottky barrier transistor. (a) Schematic device layout. (b) Top-view SEM image of a measured device. (c) Comparison of continuous and pulsed gate sweep under vacuum conditions after bake-out. (d) Family of ambipolar ID−VBG characteristics of a back-gated germanium nanowire transistor. (e) Extracted effective barrier height ϕB,eff in dependence on VDS and VBG. Transport regimes are associated with on-state and subthreshold regimes of p- and n-branches, showing modulation by applied fields in agreement with theory.

silicon, carbon nanotubes, MoTe2, or graphene, enabling an operation at low supply voltages.

conductor materials, such as pure germanium, in very large scale integration (VLSI) electronics. One approach to diminish this effect is to apply a complex heterostructure along the transport direction, placing a material with higher band gap as energetic barrier in the center of the channel as demonstrated in InAs/InAsP nanowires.9 However, integrating a heterostructure along the channel direction is very complex. Thus, a solution applicable to uniform channel materials would be desirable. In this paper, it will be shown that the reverse junction leakage current in germanium transistors can also be suppressed by a special device design employing several independent gates, thus lowering the power consumption. Here, the approach is experimentally demonstrated on an intrinsic germanium nanowire Schottky barrier field effect transistor. The same basic approach of having multiple gates can be transferred toward other types of field effect transistors (FETs), such as tunnel FETs, spin-FETs,6 or junctionless transistors.10 Temperature-dependent measurements were carried out in order to characterize the influence of the gated nanojunctions on the band structure, and finite-element driftdiffusion simulations are employed in order to prove that the effect is persistent at highly scaled geometries. Moreover, the presented device can be dynamically programmed to resemble both p-type and n-type functionality within a single device without using any kind of physical doping.7,11 This so-called feature of polarity control can be employed to drastically reduce the transistor count while also decreasing the delay of arithmetic circuits.12−16 Thereby, our fabricated germanium nanowire transistor is superior in terms of threshold voltages, as compared to earlier reported polarity-controllable device concepts7,11,17−21 employing other channel materials such as

RESULTS AND DISCUSSION Schottky Contact Formation and Analysis. Nominally doping-free ⟨110⟩-oriented germanium nanowires were used for device fabrication. The employed nanowires were catalytically grown from diluted GeH4 by a Au particle-assisted vapor− liquid−solid growth mechanism. Subsequently, the wires were covered with a protective Al2O3 layer grown from trimethylaluminum (TMA) and ozone (O3) via atomic layer deposition (ALD). Due to an ozone-first treatment, an in situ GeOX passivation layer is formed at the Ge−Al2O3 interface.22 Source and drain contact pads were deposited by nickel sputtering after locally etching the oxide shell with diluted NHF4. Subsequently, intruded metallic Ni2Ge contacts were formed within the passivated germanium nanowires by a rapid-thermal-annealinginduced oxide-confined diffusion process, giving an abrupt junction to germanium.23 The resulting structure, similar to the one shown in Figure 1a, can be already steered within a backgate configuration prior to the top-gate formation. In this configuration an ambipolar behavior typical for Schottky barrier FETs is observed. The transfer characteristics exhibit a notable hysteresis if measured in a quasistationary setup (Figure 1c, red line), which can be related to border traps or defects within the oxide.24 In order to eliminate this effect, a pulsed measurement scheme as proposed by Mattmann et al. was applied.25 Thereto, each individual measurement pulse is followed by a detrapping pulse of the same magnitude in the opposite direction (see Supporting Information). The resulting full family of hysteresisfree transfer characteristics of the back-gated nanowire device is depicted in Figure 1d. At a drain−source voltage level VDS of 1.2 V on-currents of 2.2 × 10−9 and 4.1 × 10−7 A are achieved 1705


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Figure 2. Off-current leakage suppression and polarity control in a nanowire transistor. (a) Top-view SEM image of a multigated germanium nanowire transistor. (b) Cross-sectional TEM image below one of the two top-gates. (c) High-resolution TEM image of the channel region revealing a crystal lattice in the ⟨110⟩ direction and the presence of a sub-1-nm GeOX interface passivation layer. (d) Schematic device layout in longitudinal section and applied voltages employed for leakage current suppression and polarity control. Program-gates (PG) at front and back are coupled. (e) Unipolar ID−VCG transfer characteristics of p-type and n-type operation due to leakage current suppression. (f) Simulated band diagrams in the on-state (typical operation) and off-state (additional barrier near drain contact) of the p-type configuration. Barrier tunneling is indicated by an arrow. The n-type configuration band diagrams can be constructed in an analogous manner by simply reversing the respective band bending.

for the n- and p-type branch at VBG = 5 V and VBG = −5 V, respectively. This equals to on/off ratios of 2.2 × 102 and 4.1 × 104 for the n- and p-branch, respectively. Using this back-gated structure, the Schottky barrier heights of the germanium-togermanide contacts were determined by thermal activation energy measurements in the temperature range from 250 to 360 K, as described in detail within the Methods section. The analysis thereby is focused on four discrete values of VBG associated with on-states and subthreshold regimes of the pbranch and n-branch, respectively. For each state effective barrier heights ϕB,eff as shown in Figure 1e were extracted from the slopes of Arrhenius plots. Naturally, for both branches the effective barrier is larger in the subthreshold region as in the respective on-state. Interestingly, no effective barrier is present for the on-state of the p-type branch even at very low source− drain voltages. If the applied voltages approach zero, the effective Schottky barrier height is expected to converge toward the natural Schottky barrier height ϕB of the injecting junction. Consequently, ϕB could be extracted to be ∼0.2 eV for holes and ∼0.4 eV for electrons, neglecting the abrupt increase for VDS ≤ 50 mV, which can be attributed to the additional influence of the ejecting barrier as described by Beister et al. for silicon devices.26 The achieved values are in good agreement with literature data for Ni2Ge.27 The formation of this germanide phase could also be verified based on a quantitative energy-dispersive X-ray (EDX) analysis using a Zeiss Libra 200 transmission electron microscope (TEM).

Suppression of Reverse Junction Leakage and Polarity Control. The ambipolar conduction of Schottky transistors generally leads to high off-state leakage currents if either electron or hole conduction is desired. In order to reduce the leakage current, two independent omega-shaped top-gates were added to the nanowire structure aligned on top of the two Schottky junctions, as shown in Figure 2a. A cross-sectional TEM image (Figure 2b) of a typical device revealed an 18 nm thick germanium channel with a 7 nm Al2O3 dielectric below the gates. Lattice parameters extracted from the high-resolution TEM image shown in Figure 2c confirm that the wire is oriented in the ⟨110⟩ direction, for which Ge and Ni2Ge share an epitaxial relation.28 The gate aligned on top of the source contact serves as a control-gate, turning the transistor on or off. In the off-state the additional gate aligned on top of the drain contact induces a band bending opposite that at the source contact. This feature efficiently suppresses the reverse junction leakage, while not diminishing the device on-state performance, which is an essential feature to enable germanium-based transistors. Depending on the applied voltage of the drain side top-gate (further called program gate), either electron or hole leakage can be suppressed employing negative or positive voltages, respectively. In order to achieve a better control over the whole device and to eliminate trapping effects, the backgate is used in conjunction with the drain side top-gate for programming (Figure 2d,e). Applying |VPG| = 3 V, a total on/off-ratio of 1 × 104 and 6 × 102 is achieved for p-type and n-type modes, respectively. 1706


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Figure 3. Temperature-dependent operation. ID−VCG transfer characteristics of (a) p-type and (b) n-type operation of a germanium nanowire transistor with two individual top-gates and additional back-gate support for programming at various operation temperatures. An increase in off-current level and subthreshold swing with temperature is visible. No current increase in off-direction was observed. An energy barrier of 0.35 eV in the off-state was calculated.

Within the control gate voltage VCG range from −2 to 2 V maxima on-currents of 1 × 10−7 A (1.8 × 10−6 A/μm normalized to the nanowire’s Ge-core circumference) and 8.5 × 10−9 A (1.5 × 10−7 A/μm) were achieved for p-type and n-type programs at |VDS| = 2 V, respectively. This corresponds to maximum current densities of 38 and 3.5 kA/cm −2 , respectively. A peak transconductance of 1.8 μS/μm was calculated for the p-type program, and 160 nS/μm could be calculated for the n-type program. The off-currents of the measured device were determined to be 1 × 10−11 A (1.8 × 10−10 A/μm) and 1.3 × 10−11 A (2.3 × 10−10 A/μm) for p-type and n-type operation, respectively. Those values can be solely attributed to thermionic generated carriers, while other reverse junction leakage mechanisms, which would lead to an ambipolar operation, are well suppressed. Although the achieved off-currents are significantly larger than those typically achieved in silicon devices, the measured currents are about 3 orders of magnitude lower compared to other germanium device concepts built on FinFETs,4 fully depleted germaniumon-insulator,29 or even Si/Ge quantum-well heterostructures,2 which typically exhibit off-currents of approximately 1 × 10−7 A/μm at a source−drain voltage of 0.5 V. This outstanding result is achieved by the additional energy barrier added to the channel via the multigate structure (see Figure 2f). Utilizing the temperature-dependent IV methodology applied to characterize the energy barriers at the injecting contacts, the effective height ϕB,eff of this additional barrier within the off-state was determined. Thereto, p-type and n-type transfer characteristics were taken in the temperature range from 300 to 360 K, as depicted in Figure 3. As expected from theory, the subthreshold slope is degrading with increased temperature for both operation types. Further, an increase in off-current with temperature is evident, which can be attributed to a higher amount of thermally generated carriers. Nevertheless, ambipolar operation is still well suppressed for both operation types even at 360 K and a comparably high VDS level of 1.2 V. Relatively equal off-current levels of 2.2 × 10−9 A/μm are achieved under this condition for both operation types. From the resulting Arrhenius data, the effective barrier height could be determined to be as large as 0.35 eV for both program types, matching roughly with half of the band-gap energy. Furthermore, the threshold voltages of both program types were determined to be VTH,p = −0.2 V and VTH,n = 0.4 V. These values are considerably lower than the previously achieved values for reconfigurable silicon nanowire transistors or other

polarity-controllable devices, regardless of the channel material used. For example threshold voltages VTH of |1.4 V| were reported for both operation types for a Si-based device with similar geometrical layout.18 Consequently, the transistor is able to operate at a much lower supply voltage, while still delivering a sufficient output current. This considerably reduces the fraction of dynamic power consumption, which is proportional to the square of VDD. Finally, minimal inverse subthreshold slopes of 150 and 215 mV/dec could be extracted for p-type and n-type programs, respectively. In an ideal case 60 mV/dec should be reached at room temperature, if the gate oxide capacitance COx ≫ CSemi + CIT, where CSemi is the semiconductor body capacitance and CIT the capacitance of interface traps. Given the low corresponding planar EOT of only 3 nm, the deviation from this ideal value is typically considered to originate from an increased amount of interface traps as compared to silicon-based devices. Thus, the gate dielectric interface was analyzed more in detail employing TEM, X-ray photoelectron spectroscopy (XPS), and electrical measurement techniques. Interface Properties. In the high-resolution cross-sectional TEM image in Figure 2c a small interfacial layer, as envisioned by the in situ ozone passivation, is visible between the Al2O3 and the germanium region. To yield more insights into this passivation layer, the in situ formation of GeOx during the ALD process was analyzed on planar reference samples. Thereto, a silicon wafer with a 1 μm thick epitaxial-grown germanium layer was cleaned in HF and immediately covered with 24 cycles of Al2O3 employing the identical process as used for device fabrication. Angle-resolved X-ray photoelectron spectroscopy (ARXPS) as described in detail by Paynter30 and Kozlowska31 was applied in order to confirm the thickness of the suspected interfacial layer to be less than 1 nm. As the O 1s binding energies of Al2O3 and GeO2 overlap, the stoichiometry of the interface layer was analyzed based on the Ge3d and Ge2p3 peak positions. For both binding energies a distinct oxide peak is present next to the peak assigned with pure Ge−Ge bonds. However, they could not be unambiguously assigned to one of the oxidation states (see Supporting Information). Consequently, it can be inferred that the formed in situ interface is not purely stoichiometric but rather a mixture of GeO2 and GeO. In order to give a measure for the quality of the passivation layer, interface trap density + IT and density of border traps 5BT were analyzed on planar reference samples and compared to the values achieved in pure thermally grown GeO2 layers 1707


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Figure 4. Simulation data of multigated germanium nanowire transistors with scaled geometries. (a) Schematic longitudinal view of a dualgated transistor model, showing geometry parameters and materials used for simulation. (b) Simulated transfer characteristics of the transistor in (a) with germanium nanowire channel (solid lines), exhibiting largely improved on-currents and reduced threshold voltages compared to the silicon-based device (dashed lines) having identical geometry. NiSi2 contacts are used for the silicon device. (c) Schematic longitudinal view of a three-gated transistor model, showing geometry parameters and materials used for simulation. (d) Simulated transfer characteristics of the transistor in (c) with a germanium nanowire channel. Both program gates are coupled and steered simultaneously. For comparison inverse subthreshold slopes are given.

directly after oxidation. For both gate stacks + IT values in the low to mid 10−11 cm−2 eV−1 range and 5BT values of ∼10−11 cm−2 eV−1 were achieved, indicating that a similar interface is formed during the ALD process. The resulting + IT values match well with literature data of thermally grown32 as well as plasma-based22 GeO2 passivation layers and are suitable for an integration of the device toward scaled geometries. It can be concluded that the relatively high inverse subthreshold slopes are rather caused by the comparably large germanium nanowire diameter, which is associated with a high body capacitance CSemi and not by defects at the dielectric interface. Therefore, an outlook to devices with scaled feature sizes will be given next, in order to demonstrate that the device concept is suitable for low-power operation if the right geometries are chosen. Simulation of Highly Scaled Geometries. In order to evaluate the functionality of our device under scaled geometrical features, a finite-element drift-diffusion model was set up using a technology computer aided design (TCAD) software. The channel length of the transistor was set to 48 nm. A gate stack of 5.6 nm thick HfO2 (corresponding to an EOT of 1 nm in a planar capacitor) and metallic Ti electrodes were applied surrounding the 6 nm thick nanowire. Both gates were set to 24 nm length overlapping the Schottky junctions. Metallic Mn3Ge5 contacts were used as source and drain electrodes, as they are reported to exhibit a hole Schottky barrier height of 0.25 eV,6 aligning closest to the germanium midgap energy. The resulting structure and the simulated transfer characteristics at an operation voltage of 1.2 V are shown in Figure 4. As a result of the strongly improved gate coupling, both device programs exhibit increased on-currents of up to 785 μA/μm as well as reduced subthreshold swings of 80 and 85 mV/dec, respectively. Note that these predicted currents are in reach of values achieved with modern FinFET technology, which have reached 1.04 mA/μm in the 14 nm node.33 The threshold voltages VTH,n/VTH,p = 0.4 V/−0.3 V extracted from the simulations are similar to our fabricated germanium device. All of those metrics outperform a silicon nanowire device with identical geometry as indicated by the

dashed lines, where threshold voltages of VTH,n/VTH,p = 0.7 V/ −0.8 V, inverse subthreshold slopes of 93 mV/dec, and equal on-currents of 90 μA/μm are reached. As already stated, this enables a largely reduced dynamic power consumption using the germanium technology, while keeping the performance identical. More remarkably, although the device layout is aggressively scaled, the off-current level of 0.5 nA/μm is nearly identical to that of the fabricated device, leading to an on/off current ratio off 1 × 106 for both operation types. This ratio is about 1 order of magnitude higher than the theoretical limit for single-gated devices predicted using eq 1. Off-state leakage is again well suppressed. The extracted band diagrams reveal that this is achieved by the additional energy barrier due to opposite band bending induced by the two individual gates. The barrier height within the off-state could be determined to be 0.33 eV, nicely confirming the earlier presented measurement results. Perspectives. Although, at a first glance, additional gates are an impediment for scaling, substantial additional functionality is added to the circuit level by the option to operate the same doping-free device as both n- or p-type transistor. As a simple example, not-and (NAND), not-or (NOR), and majority function can all three be executed by a single sixtransistor cell,12 which compares to a logic gate with at least 10 transistors in standard CMOS technology. The number of transistors needed to provide a certain function can even be reduced if more than two independent gates are crammed into a single device.13,34 In terms of process and layout, the device concept does not require any doping, well implantation, or shallow trench isolation. As a result, faster, more compact, and energy-efficient circuit designs have been proposed despite the larger individual footprint of the transistors.13,15,16 Although specified initially for Si-based devices, these methods can be applied to germanium nanowires as well. In fact the use of Ge nanowire transistors with reduced leakage and supply voltage, as proposed here, will enable those designs to unveil their full advantage on the circuit level. For more details on circuit design possibilities the reader is referred to the Supporting Information, where a short review on the topic is provided. 1708


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determined using conductance and CV-hysteresis methods.37,38 A pulsed gate sweep measurement routine using an arbitrary waveform generator was used to evaluate the ID−VG characteristics independently of border traps, which are present at the Al2O3/GeOx/Ge interface. In order to support our measurement data, drift-diffusion simulations were performed using TCAD. Barrier tunneling was modeled using the Wentzel−Kramers−Brillouin (WKB) approximation for finite-element-method-based simulations. The corresponding effective tunneling masses in germanium were set to literature values of 0.082m0 for electrons and 0.042m0 for holes.39 A titanium top-gate electrode with WTi = 4.33 eV and a midgap workfunction of 4.41 eV corresponding to Mn5Ge3 as contact material was chosen.6 Barrier Extraction Method. A Schottky transistor can be modeled by two individual Schottky diodes connected back-to-back. The current transport through this equivalent structure can be expressed by40

Beyond that, layouts with multiple gates also have the potential to further boost the performance of the individual device itself. Simulation data of an example design with three top gates are shown in Figure 4c. It is evident that near ideal subthreshold slopes of 62 mV/dec are reached. Also the threshold voltages are decreased down to |0.2 V| for both operation types. This benefit comes at the cost of slightly higher off-state leakage. However, the achieved values are still very good for a Ge-based transistor technology. Both device concepts shown in Figure 4 are compatible with each other in terms of process and functionality and thus bear the possibility to tune the system toward the desired performance measures. All factors together make this germanium device technology a promising candidate for future low-power electronics.

ID = ART 2 e(−ϕB,eff / kBT )

CONCLUSIONS Within this work it could be demonstrated that the approach of having several independent gates within a single transistor design has the potential to eliminate the issue of high reverse junction leakage typically present in low-band-gap semiconductor devices. The limitations set by the band-gap energy can be evaded due to opposite band bending at the drain contact induced by a program gate voltage. As a consequence, the static energy consumption is efficiently reduced. Further, the concept of polarity control has been experimentally demonstrated on a low-band-gap semiconductor channel material. Considerably reduced threshold voltages were achieved as compared to previous device demonstrators applying other materials. This is a prerequisite for lowering the supply voltages, thus minimizing dynamic power consumption. The device bears the possibility to enable energyefficient reconfigurable circuit design concepts. As a conclusion, multigate germanium nanowire transistors hold the potential to enable the application of low-band-gap semiconductor materials in future low-operation-power systems.

(2)

where A is the area, R the reduced Richardson constant, T the temperature, kB the Boltzmann constant, and ϕB,eff the effective Schottky barrier height equaling a thermal activation energy of the system, which can be modulated by the application of an electrical field. As the internal potential of the nanowire body is not accessible, ϕB,eff is treated as a function of the external bias conditions. Consequently, at moderately high temperatures where R and ϕB,eff are essentially temperature independent, ϕB,eff can be extracted from the slope of an Arrhenius plot of ln(ID/T2) versus 1/T as a function of VBG and VDS.39 If all applied voltages converge toward zero, ϕB,eff approaches the natural Schottky barrier height ϕB for the respective carrier type.

ASSOCIATED CONTENT S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.6b07531. Details about the pulsed measurement scheme, the XPS characterization, and a short review of reconfigurable circuit design possibilities (PDF)

METHODS/EXPERIMENTAL SECTION

AUTHOR INFORMATION

Device Fabrication. As a model material system ⟨110⟩-oriented intrinsic germanium nanowires were grown in a latticed-matched fashion from epitaxial germanium layers on top of silicon substrates. The vapor−liquid−solid growth method was carried out with 1% GeH4 in a H2 atmosphere utilizing a nominally 0.5 nm thick plasmacoalesced gold layer as catalyst. In order to yield long and taper-free wires, a two-temperature step process featuring a 3 min coalescence step at 340 °C and 90 min of growth at 280 °C was used.35,36 The resulting nanowires were immediately transferred to an ALD chamber and covered with 20 nm amorphous Al2O3 grown from O3 and TMA at 300 °C (k = 9). The growth rate was 0.75 Å per cycle. An in situ GeOX interface was formed by the ozone-first process. The passivated germanium nanowires were transferred to a silicon host substrate with 100 nm thermally grown silicon dioxide on top via a spray-coating process. Electron beam lithography was used for alignment and patterning of the source and drain contacts. After pocket etching with 1% buffered HF for 3 min a 45 nm thick nickel layer was deposited by sputtering. Sharp metallic Ni2Ge contacts were formed during a subsequent rapid thermal annealing step at 370 °C for 180 s in a N2 atmosphere. Subsequently, the device was passivated with an additional 5 nm thick ALD Al2O3 layer. Two individual omega-shaped Ti/Al (20 nm/10 nm) top-gates of 350 nm length were patterned on top of each Schottky junction. The channel length of the resulting nanowire devices varied from 400 nm to 1 μm. Measurement and Modeling Setup. Electrical characterization took place in an evacuated measurement setup in the range from 250 and 360 K at 2 × 10−6 mbar after in situ bake-out at 380 K applied to remove surface absorbents. Interface and border trap densities were

Corresponding Author

*E-mail: [email protected]. ORCID

Jens Trommer: 0000-0003-2972-438X Author Contributions

J.T. fabricated the shown devices, performed the measurements and simulations, and wrote the manuscript. A.H., T.B., T.M., and W.M.W. motivated the experimental approach and set up the device layout as well as the TCAD facility. A.W. developed the ALD process and performed the border trap analysis. J.B. set up the temperature-dependent measurement as well as the barrier analysis technique. P.M.J. performed and analyzed the DIT measurements. U.M. and M.L. did the TEM sample preparation and imaging. M.G. and B.A. performed and analyzed the XPS data. W.M.W., E.Z., and T.M. led the project and supervised the research. All authors discussed and interpreted the results and contributed to the final version of the manuscript. Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS This work was funded by the German Research Foundation (Deutsche Forschungsgemeinschaft) within the project “Re1709


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ACS Nano

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proNano II” (MI1247/6-2 and WE4853/1-2) and Center for Advancing Electronics Dresden “CfAED” as well as the German Federal Ministry of Education and Research (BMBF) within the “MaKiZu” project. The authors thank J. Gärtner, J. Ocker, T. Neuhaus, and M. Grube from Namlab for technical support.

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Enabling Energy Efficiency and Polarity Control in Germanium

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