Ferroelectric Analog Synaptic Transistors - Nano Letters (ACS

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Ferroelectric Analog Synaptic Transistors Min-Kyu Kim, and Jang-Sik Lee Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.9b00180 • Publication Date (Web): 30 Jan 2019 Downloaded from http://pubs.acs.org on January 31, 2019

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Ferroelectric Analog Synaptic Transistors Min-Kyu Kim and Jang-Sik Lee *

Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Korea *E-mail: [email protected]

ACS Paragon Plus Environment

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ABSTRACT Neuromorphic computing is a promising alternative to conventional computing systems as it could enable parallel computation and adaptive learning process. However, the development of energy efficient neuromorphic hardware systems has been hindered by the limited performance of analog synaptic devices. Here, we demonstrate the analog conductance modulation behavior in the ferroelectric thin-film transistors (FeTFT) that have the nanoscale ferroelectric material and oxide semiconductors. Accurate control of polarization changes in the nanoscale ferroelectric layer induces conductance modulation to demonstrate linear potentiation and depression characteristics of FeTFTs. Our devices show potentiation and depression properties, including high linearity, multiple states, and small cycle-to-cycle/device-to-device variations. In simulations with measured properties, a neuromorphic system with FeTFT achieves 91.1% recognition accuracy of handwritten digits. This work may provide a way to realize the neuromorphic hardware systems that use FeTFTs as the synaptic devices.

KEYWORDS: ferroelectric materials, thin-film transistors, multi-level data storage, artificial synapses, neuromorphic computing, analog conductance modulations


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Development of an efficient computing system may be a way to overcome the scaling limits of complementary metal-oxide-semiconductor (CMOS) devices.1-3 Conventional von Neumann computing systems separate memory from logic; the communication between these components increases the power consumption and heat generation in conventional computing systems.4 New computing paradigms such as neuromorphic computing can overcome this problem. Neuromorphic computing replicates the structure of the human brain, and may enable highlyefficient computing by parallel computation and adaptive learning.5-6 Efficient neuromorphic computing systems require synaptic devices that can achieve analog updates of synaptic weights. Various devices have been successfully demonstrated as synaptic devices to realize neuromorphic computing hardware,7-19 but some of them have suffered from a small on/off ratio, undesirable variations, poor data retention, and non-linear weight-update properties. High accuracy in neuromorphic systems requires development of devices that have ideal synaptic properties.20-22 Ferroelectric materials have a great potential to meet these requirements.23-24 Ferroelectric materials have spontaneous polarization states that can be maintained even without an external electric field. Delicate control of polarization is possible because domains in ferroelectric materials can be controlled by an applied electric field.25-26 Each polarization state of the ferroelectric layer can be confirmed by changes in channel conductance; to exploit this characteristic, ferroelectric materials have been evaluated as the dielectric layer in transistors.27-29 The conductance of channel material in ferroelectric transistor can be gradually controlled by the polarization of ferroelectric materials.23, 30 These characteristics can be the solution to solve some problems in current synapse devices, such as a small on/off ratio, non-linear weight updates, and variations in electric properties. So, ferroelectric transistors constitute promising candidates for memory and synaptic devices.24-25, 31-32

However, ferroelectric materials have been reported to show some issues, for example,


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complex compositions, high annealing temperatures, and difficulty in scaling.33-35 These problems can also be critical in ferroelectric synaptic devices. Additionally, ferroelectric transistors based on Si cause formation of interfacial layers when ferroelectric materials are deposited directly on the Si substrate due to high annealing temperature and volatile elements such as Pb in the ferroelectric layer. Interfacial layers can cause high operation voltage, poor retention, and small memory windows.36-37 To overcome these limitations, ferroelectric materials based on nanoscale hafnium oxide (HfOx) have been suggested. Ferroelectric materials based on HfOx have various advantages, such as CMOS compatibility, low process temperature, and process scalability.38-44 Use of oxide semiconductors and low temperature HfOx-based ferroelectric layers can minimize the formation of interfacial layers, so these materials are desirable as channel materials and ferroelectric layers in ferroelectric transistors. Therefore, a ferroelectric transistor based on nanoscale HfOx and an oxide semiconductor could be useful in fabricating synaptic devices with CMOS compatibility, process scalability, and desirable synaptic characteristics. In this study, we fabricate ferroelectric thin-film transistor (FeTFT) based on nanoscale ferroelectric material and oxide semiconductor to investigate the feasibility of FeTFTs as synaptic devices. The FeTFT shows the ferroelectric hysteresis in its transfer curve, multi-level data storage capability, and data retention property. We demonstrate analog potentiation and depression characteristics of FeTFTs. This paper shows the feasibility of FeTFT as the synaptic device for the neuromorphic hardware systems.

Results and Discussion FeTFTs with metal-ferroelectric-semiconductor (MFS) structure were fabricated (Figure 1a). Prior to the fabrication of MFS structure, the basic ferroelectric characteristics of metal-


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ferroelectric-metal (MFM) capacitors (TiN/zirconium-doped hafnium oxide (HfZrOx)/TiN) were measured (Figure S1). Ferroelectric polarization hysteresis curves with different sweep voltages were shown in Figure S1a. The capacitors had the typical capacitance-voltage (C-V) curve of ferroelectric materials. HfZrOx was used as the ferroelectric layer in the FeTFTs (Figure S1b). Stable ferroelectric polarization-voltage (P-V) characteristics were also observed from TiN/HfZrOx/TiN structure with different device sizes (Figure S2). In addition, we confirmed that it is possible to operate the ferroelectric capacitors with a size of 1×1 μm2 by measurement using electrostatic force microscopy. To enable use of a ferroelectric material based on HfZrOx as dielectric layer, the FeTFTs were fabricated with a bottom-gate structure. This structure is suitable because induction of ferroelectric properties in HfZrOx layer requires an appropriate bottom layer.45-46 To fabricate MFS structure, HfZrOx was transformed to the ferroelectric phase by thermal annealing on the TiN gate electrode. Then a layer of indium gallium zinc oxide (IGZO) was deposited as the channel layer on the HfZrOx layer. To investigate the ferroelectric properties in MFS structure, P-V measurements were performed by applying voltage to the TiN bottom electrode with the Al top electrode grounded (Figure 1b). The hysteresis loop indicated that positive remnant polarization (+Pr) = 5.3 μC/cm2 and -Pr = -5.9 μC/cm2. In addition, to estimate the reliability of MFS structure, the endurance properties of Al/IGZO/HfZrOx/TiN structure were tested by applying pulses (±7 V, 10 μs). Ferroelectric properties of MFS structure was retained without degradation for 105 cycles (Figure S3). The C-V curve revealed the charge responses of MFS structure according to the applied voltages (Figure 1c). A butterfly-shaped curve was observed, which is a result of the ferroelectric nature of HfZrOx. Capacitance decreased when negative bias was applied to TiN bottom electrode, but capacitance increased when this bias was positive; these results indicate that electrons are accumulated and depleted at the interface between


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the ferroelectric layer and IGZO layer, depending on the direction of the polarization in HfZrOx layer.47-48 The accumulation and depletion states in the IGZO layer were maintained without the applied voltage.30 These results confirm the ferroelectric characteristics of HfZrOx in the MFS structure. The electrical characteristics of FeTFT was investigated by applying a gate voltage (VG) sweep to the TiN bottom electrode, while a source-drain voltage (VDS) of 1 V was applied. The FeTFT with ferroelectric HfZrOx had n-type transfer characteristics. Forward and reverse transfer-curve sweep evoked typical anticlockwise hysteresis, which arose from ferroelectric polarization switching of the HfZrOx (Figure 2a). The hysteresis curve was saturated when a VG > 5 V was applied. Conductance modulation under AC operation was also investigated by applying voltage pulses (Figure 2b). Programming pulses (30 ms, 6 V) and erasing pulses (30 ms, -6 V) were applied to the gate electrode, and read voltages (VG: -1V, VDS: 1V) were used to read its state. The programming pulse increased the conductance G of the channel, but the erasing pulse reduced G. The ratio of maximum conductance Gmax to minimum conductance Gmin of channel was over > 40. The origin of G modulation in a FeTFT is polarization switching in the ferroelectric layer. G of the channel can be controlled by the polarization state of the ferroelectric layer.37, 49 Therefore, multi-level data storage can be achieved by inducing continuous ferroelectric domain switching in the HfZrOx layer.23, 50 The gradual change in polarization state of HfZrOx layer can be possible by controlling the applied voltage (Figure S1a). When a voltage is applied to a ferroelectric layer, the fraction of switched polarization might depend on amplitude of the applied voltage.25-26 The partially switched state can be realized by applying a bias pulse with suitable amplitude. Therefore, the use of an appropriate bias pulse is expected to enable gradual control of the G of the channel, because G is


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closely related to the polarization state in ferroelectric layer.25-26, 30 To investigate multi-level data storage properties in FeTFTs, the partial switching of ferroelectric domain was induced by applying different programming voltage pulses and the resulting G of the channel was measured (Figure 3a). First, the erased state was set up by applying a negative bias pulse (30 ms, -6 V) to the gate electrode. In this state, the polarization of the HfZrOx layer pointed downward (toward TiN gate electrode), and the channel had low G because electrons were depleted from the interface between the channel and ferroelectric layer by the downward polarization.30 With applying the positive bias pulse to the gate electrode, the polarization began to switch to the upward direction (toward IGZO channel) starts. As the amplitude of positive bias pulse increased, the polarization in the ferroelectric layer changes sequentially from downward to upward. When upward polarization increased, G of the channel increased because electrons could accumulate at the interface region with the upward polarization (Figure 3b).37 Therefore, G of the channel could be delicately modulated by the changing the amplitude of applied bias pulses. Here, four data levels were shown, but it is possible to control levels much more since the polarization reversal can be controlled almost linearly by changing applied bias amplitudes and/or widths.25, 37 The retention properties were evaluated by measuring four channel G levels at read voltage (VG = -1 V and VDS = 1 V). FeTFTs based on the ferroelectric HfZrOx and oxide semiconductor showed the stable data storage properties of four channel conductance levels for 104 s (Figure S4). These stable retention characteristics are very promising because previously-reported devices, such as organic and inorganic FeTFTs have suffered from poor data retention properties ( 10, data levels >32, and low cycle-to-cycle/device-to-device variations.20-21,

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The conductance modulation

properties of FeTFTs give them potential as ideal synaptic devices. To investigate the analog conductance modulation properties of FeTFT, multiple bias pulses with incremental amplitude (potentiation: 2.7 V to 4.3 V with 25 mV step, depression: -2 V to -3.6 V with 25 mV step) and 10 ms width were applied to the gate. After applying each bias pulse, the conductance of device was measured at VG of -1 V and VDS of 1 V (Figure S5). The FeTFT exhibits the good potentiation and depression properties, such as 64 level conductance states, good linearity (Ap: -0.8028, Ad: 0.6979), and Gmax/Gmin ratio >10 (Figure 4a). To evaluate linearity of potentiation and depression, the change in G with number of pulses is described as21, 24 −P

𝐺𝐺p = B �1 − eAp � + 𝐺𝐺min , 𝐺𝐺d = −B �1 − e

Pmax −P Ad

� + 𝐺𝐺max ,

𝐵𝐵 = (𝐺𝐺max − 𝐺𝐺min )/ �1 − 𝑒𝑒

−𝑃𝑃max 𝐴𝐴p,d

�

, where Gp is the conductance of potentiation, Gd is the conductance of depression, Pmax is the maximum number of pulses, and A is the parameter that represents the linearity of potentiation and depression.


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An artificial neural network (ANN) was simulated to perform supervised learning on the Modified National Institute of Standard and Technology (MNIST) database.2 For simulation, a two-layer multilayer perceptron (MLP) neural network with 400 input neurons, 100 hidden neurons, and 10 output neurons was utilized (Figure 4b).2, 20, 24 The MLP algorithm with analog weight update was used in a simulation based on FeTFT conductance modulation properties, such as number of conductance states, linearity, Gmax/Gmin, cycle-to-cycle variation, and device-to-device variation. The 400 input neurons correspond to a 20×20 MNIST data, and the 10 output neurons correspond to 10 classes of digits (0-9). At each epoch, the ANN was trained on 8,000 patterns that had been randomly selected from 60,000 images in a training dataset, and the recognition accuracy was tested on a separate set of 10,000 images from the testing dataset.2 In the simulations, the NN based on FeTFT was achieved 91.1% accuracy after 125 training epochs, which is comparable to the recognition accuracy of 94.1% obtained by the ideal synapse NN. The high recognition accuracy is achieved because of the 64-level conductance states, good linearity (Ap: -0.8028, Ad: 0.6979), and reasonable Gmax/Gmin ratio (>10). In addition, the good variation properties of FeTFT would contribute to the high recognition accuracy. Endurance property was measured up to 100 cycles (12800 pulse operation) (Figure 5a). During repeated pulse operation, degradation was not serious. Small cycle-to-cycle variation of 2.36% (n = 100 cycles) and device-to-device variation of 3.93% (n = 40 devices) were obtained (Figures 5b, c, and S6). These parameters affected recognition accuracy (Figure 6). A comparison between previous synaptic devices and FeTFTs is made (Table S1).7, 9, 13, 24 FeTFTs are promising candidates for synaptic devices due to high Gmax/Gmin ratio, small variation properties, and the number of conductance levels. In particular, FeTFT exhibits good variation properties compared to previously-reported synaptic devices based on the resistive switching behavior.7, 9, 24 When cycle-to-cycle variation of synaptic devices is >


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3%, the recognition accuracy may be seriously degraded because variation can overwhelm the amount of conductance modulation.21 Neuromorphic devices based on FeTFT have advantages in variation properties because the origin of conductance modulation in FeTFT is obtained by controlling partial polarization switching in ferroelectric layer.24 Thus, the controllability of channel conductance presents opportunities for developing neuromorphic hardware based on ferroelectric analog synaptic transistors.

Conclusions In summary, we fabricated and demonstrated an analog synaptic device that used the nanoscale ferroelectric material and oxide semiconductor. The conductance of channel was controlled by the polarization of the ferroelectric layer. The potentiation and depression properties in FeTFTs were measured by applying incremental bias pulses. The FeTFT had good weight-update properties, including good linearity, multiple data states, a high Gmax/Gmin, and small device variation properties. An artificial neural network simulation using those measured properties showed 91.1% recognition accuracy in recognizing handwritten digits. These results may facilitate the development of the neuromorphic hardware systems based on FeTFTs.

Experimental Section Fabrication of Devices: In this study, the proposed FeTFT devices have MFS structure with TiN/HfZrOx/IGZO structure (Figure 1a). First, TiN layer was deposited on the SiO2/Si substrates using DC sputtering. HfZrOx films were deposited on sputtered TiN/SiO2/Si substrate using atomic layer deposition (ALD) at 280 °C. Hf[N(C2H5)CH3]4 (TEMAH), Zr[N(C2H5)CH3]4 (TEMAZ), and ozone were used as Hf precursor, Zr precursor, and oxygen source, respectively. HfZrOx with thickness of about 24 nm was deposited using HfO2:ZrO2 ALD cycle ratio 1:1. TiN layer was


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deposited on HfZrOx films as a capping layer, then the device was thermally annealed for 1 min at 400 °C under N2 gas. TiN capping layer was removed by wet etching. This etching process did not increase the surface roughness (Figure S7). A layer of 10 nm IGZO film was deposited by radiofrequency (RF) sputtering using a sputtering target with In:Ga:Zn = 1:1:1 atomic ratio at room temperature. During the sputtering, the RF power was 150 W and working pressure in the chamber was 5 mTorr. And Al source/drain electrodes were deposited by e-beam evaporation. The channel width and length were 50 μm and 300 μm, respectively. Samples were then annealed at 100 °C for 1 h. TiN/HfZrOx/TiN and Al/IGZO/HfZrOx/TiN device with the capacitor structure were fabricated in the same way and the top electrodes of TiN/HfZrOx/TiN and Al/IGZO/HfZrOx/TiN device were 350 μm in diameter. Characterizations: All characteristics of FeTFT were measured under ambient conditions and room temperature. The electrical characteristics were obtained using a semiconductor parameter analyzer (4200a-SCS, KEITHLEY). The thickness of HfZrOx was measured by spectroscopic ellipsometer (M-2000, J.A. Woollam). The surface roughness of HfZrOx layer was measured by atomic force microscopy (AFM) (Dimension 3100, VEECO) operated in tapping mode with Sitip at scan rate of 0.6 Hz. The thickness of IGZO layer was measured by AFM (Dimension 3100, VEECO) operated in tapping mode with Si-tip at scan rate of 0.5 Hz. The polarization-voltage and capacitance-voltage curves were measured using a pulse measurement unit (4225-PMU, KEITHLEY) and an impedance analyzer (4194A, HP), respectively. All simulations were performed in Linux system with GCC, GNU make, CNU C libraries by using C++ code.20 The simulated MLP neural network consisted of 400 input neurons, 100 hidden neurons, and 10 output neurons. The 400 input neurons corresponded to the 20 × 20 MNIST image, and the 10 output neurons corresponded to 10 classes of digits. Gmax/Gmin, linearity, and cycle-to-cycle/device-to-


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device variations of the FeTFTs were considered as synaptic device characteristics in these simulations. For simulation of an ideal synapse neural network, ideal synaptic properties including perfectly linear conductance modulation with Gmax/Gmin ratio = 50, and 64 conductance states were used.


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FIGURES

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Figure 1. (a) Schematic diagram of ferroelectric thin-film transistor (FeTFT). (b) Polarizationvoltage (P-V) hysteresis curve (Inset: schematic of MFS structure with Al/IGZO/HfZrOx/TiN). (c) Capacitance-voltage (C-V) characteristic of the Al/IGZO/HfZrOx/TiN structure.


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Figure 2. (a) Transfer curve of ferroelectric thin-film transistor. (b) AC operation characteristics of ferroelectric thin-film transistor with programming pulses (6 V, 30 ms) and erasing pulses (-6 V, 30 ms).


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TiN

TiN

④ Programmed state

③ Interstate 2

Figure 3. (a) The multiple levels of the ferroelectric thin-film transistor. (b) Schematic illustrations of suggested mechanism of multi-level data storage. The direction and size of arrow represent the direction and value of polarization in HfZrOx layer, respectively.


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Figure 4. (a) Potentiation and depression properties of ferroelectric thin-film transistor with incremental pulse scheme. (b) Schematic illustration of two-layer multilayer perceptron neural network. (c) Simulated pattern recognition accuracy of the two-layer multilayer perceptron neural network based on the ferroelectric thin-film transistors compared to an ideal neuromorphic device.


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Figure 5. (a) Endurance properties of FeTFT. Cycle-to-cycle variations of (b) potentiation and (c) depression operations for 100 cycles.


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Figure 6. The effects of potentiation and depression characteristics on recognition accuracy. (a) Conductance levels, (b) Gmax/Gmin ratio, and (c) cycle-to-cycle variation.


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Supporting Information. Polarization-voltage hysteresis and capacitance-voltage characteristic of the TiN/HfZrOx/TiN structure; Polarization-voltage hysteresis of TiN/HfZrOx/TiN structure with different device size and remnant polarization of TiN/HfZrOx/TiN structure with different device size; The endurance properties of Al/IGZO/HfZrOx/TiN structure over 105 cycles and remnant polarization of Al/IGZO/HfZrOx/TiN structure over 105 cycles; Retention properties of the ferroelectric thin film transistor for multi-level state; Potentiation and depression pulse schemes applied to gate electrode; Device-to-device variation of potentiation and depression operation of 40 different devices; Topography image measured by atomic force microscope for HfZrOx film before TiN deposition and HfZrOx film and after TiN etching process; This material is available free of charge via the Internet at http://pubs.acs.org. AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] (J.-S.L) Author Contributions J.S.L. conceived and directed the research. J.S.L. and M.K.K. designed and planned the experiment. M.K.K. performed the experiment and acquired the data. M.K.K. and J.S.L. wrote the manuscript.

Competing financial interests The authors declare no competing financial interests. ACKNOWLEDGMENT


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This work was supported by the National Research Foundation of Korea (NRF2016M3D1A1027663, 2018R1D1A1B07043368). In addition, this work was partially supported by the Brain Korea 21 PLUS project (Center for Creative Industrial Materials).


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Nano Letters

TOC 0.20

Conductance (µS)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Potentiation Depression Potentiation fitting Depression fitting

0.15

1

20 x 20 MNIST data

Synapses 1

Synapses

2

1 2 2

3

0.10

3 4 10 100

0.05

Gmax/Gmin = 14.4 0.00

-20

0

20

40

60

80 100 120 140

400

400 Input neurons

100 Hidden neurons

10 Output neurons

Pulse number


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Ferroelectric Analog Synaptic Transistors - Nano Letters (ACS

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