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Ferroelectric second-order memristor Vitalii Mikheev, Anastasia Chouprik, Yury Lebedinskii, Sergei Zarubin, Yury Matveyev, Ekaterina Kondratyuk, Maxim G. Kozodaev, Andrey M. Markeev, Andrei Zenkevich, and Dmitrii Negrov ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.9b08189 • Publication Date (Web): 12 Aug 2019 Downloaded from pubs.acs.org on August 15, 2019

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ACS Applied Materials & Interfaces

Ferroelectric second-order memristor Vitalii Mikheev,1 Anastasia Chouprik,1,* Yury Lebedinskii,1 Sergei Zarubin,1 Yury Matveyev,2 Ekaterina Kondratyuk,1 Maxim G. Kozodaev,1 Andrey M. Markeev,1 Andrei Zenkevich,1 and Dmitrii Negrov1

1

Moscow Institute of Physics and Technology,

9 Institutskiy lane, Dolgoprudny, Moscow Region, 141700, Russia

2

Deutsches Elektronen Synchrotron,85 Notkestraße, Hamburg, 22607, Germany

KEYWORDS: ferroelectric hafnium oxide, ferroelectric tunnel junction, ferroelectric memristor, resistive switching, second-order memristor, synaptic plasticity

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Abstract While the conductance of a first-order memristor is defined entirely by the external stimuli, in the second-order memristor it is governed by the both the external stimuli and its instant internal state. As a result, the dynamics of such devices allows to naturally emulate temporal behavior of biological synapses, which encodes spike timing information in synaptic weights. Here, we demonstrate a new type of second-order memristor functionality in the ferroelectric HfO2 based tunnel junction on silicon. The continuous change of conductance in the p+-Si/Hf0.5Zr0.5O2/TiN tunnel junction is achieved via the gradual switching of polarization in ferroelectric domains of polycrystalline Hf0.5Zr0.5O2 layer, whereas the combined dynamics of built-in electric field and charge trapping/detrapping at the defect states at the bottom Si interface defines the temporal behavior of the memristor device similar to synapses in biological systems. The implemented ferroelectric secondorder memristor exhibits various synaptic functionalities, such as paired-pulse potentiation/depression and spike-rate-dependent plasticity, and can serve a building block for the development of neuromorphic computing architectures.

Introduction Despite the significant progress in the software approach to neuromorphic computing based on the mathematical models of synapses and neurons, a high interest persists in the hardware realization of neural networks. An appropriate hardware approach would enable faster and more energy efficient solution of complex tasks using artificial intelligence algorithms. One of the key elements put forward within this paradigm is the device emulating the plasticity of biological synapses. To date, attempts of on-chip implementation of artificial synapses focus on memristors,1,2 which are passive twoterminal electric devices with inherent resistance memory. The large variety of first-order memristors3-6 exhibits the continuous resistance change upon applying voltage pulses with different 2 ACS Paragon Plus Environment

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amplitude. The change of resistance is associated with the “synaptic weight” representing the activity state of biological synapse in the frame of Hebbian theory. The synaptic learning functionalities, such as long-term potentiation/depression (LTP/LTD) and spike-timing-dependent plasticity (STDP), have been successfully demonstrated in such electronic synapses.3-6 However, in these devices the modulation of memristor conductance is solely controlled by the applied external voltage (a so called first-order memristor) leading to some stratagems required in order to emulate synaptic properties to emulate synaptic properties. In particular, pre- and postsynaptic voltage pulse shape (“spike”) should be carefully adjusted.5 Furthermore, in order to achieve the resistance decay and thus to emulate the temporal synapse response an accurate overlapping of pre- and postsynaptic spikes is also needed, which is not the case in the biological synapses. The biological synapse possesses internal temporal mechanisms determining its instant state and subsequent synaptic plasticity. The synapse response to an encoding spike train is determined by the complex interplay of the multiple temporal processes in pre- and postsynaptic neurons including Ca2+ ion diffusion across postsynaptic membrane.7-8 Overall internal temporal mechanism controls the state of the synapse (“weight”) depending on the frequency of stimuli. At low frequency of the spike train, the synaptic weight does not undergo long-term changes, whereas the higher frequency leads to the increase of the synaptic weight (LTD/LTD processes). Therefore, the specific feature of the biological synapse is its own response to the frequency of the spike train encoding the information. The memristors which exhibit the conductance controlled by some internal temporal mechanism, do not require the peculiar shape of spikes and their overlapping and thus allow to naturally emulate the frequency response. So far, the temporal dynamics of biological synapses in these so called “secondorder” memristors has been achieved by the ion drift and diffusion dynamics of metal species.9-11 The frequency response there was governed by different internal decay processes, such as thermal dissipation of the oxygen vacancies in the conducting filament,9 the decay of the oxygen vacancies 3 ACS Paragon Plus Environment


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mobility10 or the minimization of metal species interfacial energy.11 All demonstrated second-order memristor devices can be used to naturally emulate the temporal synaptic performance on chip. However, they suffer both significant instability of switching parameters (i.e., switching voltage and resistance levels) and relatively low endurance, the challenges originating from the stochastic nature of the migration process in devices employing ion drift/diffusion. Alternatively, the “synaptic weight” can be emulated by the polarization orientation in a ferroelectric (FE) thin film. Due to inherent physical properties of FE, such memory devices can exhibit excellent stability and reproducibility of switching parameters as well as potentially unlimited endurance.12 In a ferroelectric tunnel junction (FTJ) memory concept13,14 the information is encoded by the polarization orientation in a tunneling transparent ferroelectric barrier, sandwiched between two electrodes. The switching of polarization affects the asymmetric potential energy profile shape and subsequently the tunneling current across the barrier. Furthermore, the possibility of tuning the resistance by gradual switching of polarization in multidomain FE layer allows to produce virtually continuous range of resistance levels between low- and high-resistance states (ON and OFF, respectively).15,16 Previously, FTJs have been fabricated by employing classic perovskite ferroelectric materials.17-20 Alternatively, the discovery of ferroelectric properties in doped polycrystalline hafnium oxide thin21,22 and ultrathin23 films has opened an opportunity to design complementary metal-oxidesemiconductor (CMOS) compatible FE memory devices. Indeed, FE-HfO2-based memristors have been recently implemented.24-28 Furthermore, the synaptic functionality in such first-order memristor devices has been demonstrated.29,30 However, high frequency of operation and the lack of the internal resistance decay mechanism do not allow to expect the emulation of the temporal synaptic behavior in these devices. Meanwhile, the defect-rich Si/HfO2 interface which at some point was a constraint for the integration of HfO2 as high k gate dielectric in CMOS logic applications31 can provide an internal temporal mechanism for resistance change in FTJ memristors. 4 ACS Paragon Plus Environment

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In this work, we have implemented the ferroelectric HfO2-based second-order memristor, which exhibits several synaptic learning functionalities, such as paired-pulse facilitation (PPF), paired-pulse depression (PPD) and spike-rate-dependent plasticity (SRDP) in the spike-frequency range typical for biological systems. The gradual increase and decay of resistance across such ferroelectric memristor controlled by the spike frequency are attributed to the evolution of internal depolarization electric field coupled with the population of traps with charges at the interface between FE HfO2 and highly doped Si electrode. Experimental Hf0.5Zr0.5O2 (HZO, 4 nm) and TiN (20 nm) layers were grown on a highly doped p+-Si substrate using the atomic layer deposition and magnetron sputtering, respectively, with subsequent annealing to stabilize the ferroelectric phase of HZO (as described in Supporting Information, Sections S1 and S2). The ferroelectric tunnel junctions were then patterned with a p+-Si substrate used as a bottom electrode. The cross sections of the junctions based on amorphous and crystallized films films were obtained by transmission electron microscopy (TEM). For details, see the Supporting Information, Section S2. The ferroelectric properties of FTJ devices were characterized using positive-up negativedown (PUND) technique12 (details of PUND measurements are described in Supporting Information, Section S3). The details of the I-V and C-V measurements are described in Supporting Information, Section S4, S5. Results and discussion The calculated switchable polarization 2Ps ≈ 30 C/cm2 of implemented FTJ devices (Figure 1a) measured by PUND technique is comparable to that of 10 nm-thick HZO layer in FE capacitors32,33 and in good agreement with the previous results.34 Visual inspection of P-V curve indicates the asymmetry of the coercive voltages for positive and negative branch implying the presence of the built-in electric field in the device. PUND measurements were further performed at different 5 ACS Paragon Plus Environment


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frequencies. The derived coercive voltage as a function of the switching voltage pulse frequency for both positive and negative branch is shown in Figure 1b. The effect of the voltage pulse-train frequency used during PUND measurements on the coercive voltage as well as the presence of the built-in electric field leading to the instability of downward polarization are evident from these data. Indeed, both up- and downward coercive voltage values for polarization switching measured at low frequencies are located in the positive branch. In addition, during the first measurement cycle ~ 1 second after the previous pulse voltage train (Figure 1c), the negative voltage does not produce any noticeable change in P-V curve (Figure 1a), which clearly indicates unstable downward polarization.

Figure 1. (a) High frequency P-V curves obtained during PUND measurements on p+-Si/HZO/TiN capacitor; (b) Coercive voltage values derived from both PUND measurements 6 ACS Paragon Plus Environment

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for different ramp time (solid circles) and the static I-V curves (empty circles); red-contoured circles correspond to the coercive voltages obtained from P-V curves shown in (a); (c) Voltage pulse train used during PUND measurements

The gradual evolution of static I-V curves as a function of the switching voltage amplitude in the range V = 1 - 2.7 V is presented in Figure 2a (details of I-V measurements are described in Supporting Information, Section S4). The gradual change of the differential resistance extracted from the set of these data is the signature of the memristive properties in our FTJ device. In order to confirm the ferroelectric origin of the resistive switching, one should compare the coercive voltage versus the resistive switching voltage. The hysteretic differential Roff/Ron ratio (for the particular readout voltage 1 V) as a function of the coercive voltage switching polarization in the FTJ is shown in Figure 2b. The resistance hysteresis loop is shifted toward the positive voltage: in particular, the mean left-hand-side coercive voltage shift is ~ 0.4 V, which is in good agreement with the values obtained from PUND results (Figure 2b). The correlation between the resistive switching and the coercive voltage as well as the current density independent on the device area (Figure 2c) are both evident of the ferroelectric origin of the resistance changes in p+-Si/HZO/TiN based FTJ.



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Figure 2. (a) Static I-V curves for different switching voltages in the range 1 - 2.7 V, (b) the corresponding Roff/Ron ratio as a function of the polarization switching voltage, (c) current density vs. device area plot for OFF state (cyan) and ON (coral) state.

In order to test the reproducibility of the resistive switching states in our FTJ devices Roff/Ron ratio was derived (upon the wake-up cycling) for 110 devices by measuring static I-V curves with the maximal biasing voltage V = 2.7 V and the differential resistance measured at 1 V. While ~10% of the tested devices suffered electric breakdown during the wake-up process, the rest ~90% demonstrate very good reproducibility, compared to the oxygen vacancy driven HfO2 based memristors, with the average Roff/Ron ≈ 8 (Figure 3a).

Figure 3. The performance of the p+-Si/HZO/TiN memristors: (a) reproducibility: differential resistances Ron and Roff measured for 100 tested devices; (b) endurance: switchable polarization (coral line) and Roff/Ron ratio (cyan line) as a function of the number of switching cycles


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An additional evidence of the ferroelectric origin of the resistive switching mechanism in our FTJ memristors comes from the observed correlation between the ferroelectric polarization value and Roff/Ron ratio as a function of number of switching cycles shown in Figure 3b. Indeed, it is known that fresh FE HfO2-based films contain the significant fractions of nonpolar monoclinic and tetragonal phases.34 Moreover, the polarization reversal is suppressed by the domain pinning due to the internal bias fields of the oxygen vacancies initially accumulated at the electrode interfaces.35 During the initial stage of the FE HfO2-based capacitor operation (so-called wake-up process) both the field-induced phase transformations from nonpolar phases to polar orthorhombic phase36-40 and the gradual reduction of an internal bias fields occur.35,39, 41 These effects lead to the opening of initially pinched P-V hysteresis35,39, 41 which are accompanied by the evolution of the static I-V curve in the HZO-based FTJs under investigation (Figure S4). The larger fraction of switching domains gives rise to the more effective modulation of the current transport across the studied HZO-based FTJ following the polarization reversal. The remnant polarization as well as the Roff/Ron stabilize after 5·104 cycles. Let us now discuss the physical mechanisms behind two specific phenomena in ferroelectric p+-Si/HZO/TiN memristor devices: (i) built-in electric field causing the depolarization and (ii) the observed temporal dynamics of the coercive voltages. The results of the additional C-V measurements (shown in Supporting Information, Section S5) considered together with the above described device performance indicate the presence of the donortype traps at the interface with Si. These traps are positively charged (the charge of traps Qt > 0) at the relaxed state, i.e., either without voltage or at low frequency stimuli, and we attribute the observed built-in electric field to these interface charges. To better understand the effect of interface traps on the shape of potential barrier across the junction, we performed the simulation of the p+-Si/HZO/TiN band electronic structure of our FTJ device with realistic parameters. In particular, we take the flat band voltage VFB = -0.45 V as extracted 9 ACS Paragon Plus Environment


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from C-V data (for details of simulation see the Supporting Information, Section S6). The simulated band diagram across FTJ (Figure 4a) reveals the depletion/inversion state in Si for both up- and downward orientations of polarization. The density of the charged states corresponding to the simulated band diagrams is ~ 7·1012 см-2, which corresponds to the captured charge of ~1 C/cm2 previously measured for similar structures and attributed to the ferroelectric charge.42

Figure 4. (a) The simulated electronic band diagram of p+-Si/HZO/TiN FTJ for both polarization directions at the applied voltage Vappl = 1 V; (b) the electronic band diagram of the device as reconstructed from the experimental data (CBO is the conduction band offset)

In order to experimentally verify the simulated electronic band structure of our p+Si/HZO/TiN based FTJ device, we further employed hard X-ray photoelectron spectroscopy (HAXPES) technique. With a tunable energy range of 5-12 keV, this technique enables probing layers down to about 20 nm beneath the surface, thus allowing for a non-destructive characterization of the interface properties in functional ferroelectric capacitors.4343 Using 10 ACS Paragon Plus Environment

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the previously developed methodology44 (described in Supporting Information, Section S7), we reconstructed the precise electronic conditions at p+-Si/HZO interface as well as the band bending in p+-Si in contact with as prepared FE layer (Figure 4b). The obtained flat band voltage VFB ≈ -0.39 V is consistent with VFB = -0.45 V derived from C-V measurements. The very good agreement between the simulated and experimentally derived electronic structure confirms the validity of the model. The presence of defect states in HZO layer positively charged in the relaxed state is evident from the reconstructed band diagram. It should be noted that bulk defect traps located at the HZO grain boundaries could also affect the performance of the HZO-based FTJs. However, it was recently found that for 10nm-thick HZO films the contribution of the electrode interface traps prevails.41 Moreover, it is known that the Si/HfO2 interface is rich in defects31 and, therefore, it should increase the contribution of the electrode interface traps compared with the metal-FE-metal capacitors. As for the frequency dependence of the coercive voltages in ferroelectric p+-Si/Hf0.5Zr0.5O2/TiN memristor devices shown in Figure 1b, it can be explained by the FE domain switching kinetics12 and in real structures can also be caused by the finite RC time constant.40,45 However, for the FE HfO2based capacitors ~100 μm in diameter this effect manifests itself at much higher frequencies (cf. 10 kHz46 vs. 10 Hz in this work). Therefore, we suggest that the observed frequency dependence originates from the varying electric field in the FE layer depending on the frequency of the applied 11 ACS Paragon Plus Environment


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voltage. Since we have found that charged interface traps are present in the memristor device, we assume that they contribute to the frequency dynamics of coercive voltages. Specifically, such dynamics can be achieved through the accumulation/emission of negative charges at these traps. In general, the screening of the positive polarization charge at the bottom interface (corresponding to the downward polarization) is defined by the concentration of acceptor dopants in silicon as well as the concentration of negative charges both in the bulk of silicon and at the interface with HZO. The negative charge accumulated at the interface traps (excited state of traps: the traps are neutralized or negatively charged) can facilitate the screening of the applied electric field in Si thus increasing the potential drop across the ferroelectric layer. Indeed, the applied voltage Vappl is distributed between FE layer and Si electrode: Vappl = VFE + VSi, where VFE and VSi are the potential drop across the FE layer and in Si, respectively. The decrease of VSi leads to automatic increase of VFE (Figure S12), which eventually increases the fraction of switched domains and corresponding decrease of the measured coercive voltage. If PUND positive voltage sweeps slow enough to excite (i.e., negatively charge or neutralize) all the interface traps, VFE at the same applied voltage is larger compared to that upon high frequency PUND pulse train (Figure S12). High frequency PUND pulse train thus shifts coercive voltage values since one needs to apply higher voltage to the device to reach the same coercive electric field in FE layer. It should be mentioned that the effect of positive coercive voltage shift can be also enhanced by the low rate of the minority charge (electrons for p+-Si) accumulation in the space charge region. However, the observed dynamics of coercive voltages cannot be described through the dynamics of space charge in inversion state only, since the release of the space charge determined by the drift velocity takes the time, which is less than the shortest PUND pulse (1 s). Thus, the negative voltage


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shift cannot be defined by minority carriers’ dynamics in semiconductor. In turn, short negative PUND pulse train shifts negative coercive voltage due to the finite emission rate from the interface traps. To demonstrate the frequency response of the resistance across our FTJ memristor device, we exploit the behavior of interface traps as an internal dissipation mechanism. Specifically, the instant resistance of p+-Si/HZO/TiN stack depends on the frequency of applied voltage pulses through the interplay of two described mechanisms: the depolarization effect in FE and the frequency dependence of the potential drop across FE. In outline, during pulsed (spike) stimuli with the certain duration the coercive voltage is defined by the charge accumulated at the interface. The switching pulse with the amplitude lower than the coercive voltage for certain pulse duration does not result in the polarization switching. However, if the delay time between pulses is shorter than the lifetime of the excited state, consecutive pulses would lead to the accumulation of charges at the interface traps, giving rise to the increasing potential drop across the ferroelectric layer and setting the structure in ON state. In order to evaluate the effect of the switching frequency on the dynamics of the charge accumulation at p+-Si/HZO interface we performed the simulation of trapping-detrapping process using the model described in Supporting Information, Section S8. The concentration of accumulated charges increases (Figure 5a) if the delay time is small compared to the relaxation time of the interface traps, and, on the contrary, the charge concentration at the interface is decreased by increasing the pulse delay time. Indeed, in our FTJ device the biasing at high (200 Hz) frequency gradually increases the voltage drop across the ferroelectric layer giving rise to the switching of ferroelectric domains and subsequently setting the structure in the lower resistance state (ON) as shown in Figure 5b. This functionality is similar to the paired-pulse facilitation (PPF) in biological synapses. The decrease of the pulse train frequency gradually turns the device in the high resistance state (OFF) due to the gradual decay of the potential drop across the ferroelectric layer and subsequent switching of the polarization back, thus emulating the paired-pulse depression (PPD) (Figure 5b). 13 ACS Paragon Plus Environment


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Figure 5. (a) Calculated concentration n of the accumulated charge at p+-Si/HZO interface (in arbitrary units) for two different delay times between voltage pulses, which generate carriers; (b) Experimental demonstration of PPF and PPD functionality in p+-Si/HZO/TiN memristor device. The conductance (synaptic weight) Δw (coral) change during multiple subsequent switching voltage pulses (cyan) with the same amplitude (2.5 V) and duration (10 s), but different frequency (readout pulse is 1 V, 5 ms); SRDP showing the conductance (synaptic weight) Δw change in p+-Si/HZO/TiN device as a function of delay time between pulses due to the depolarization effect (c) and the temporal effect


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of minority carriers accumulation in the depletion region (d); in insets the appropriate voltage pulse trains are shown

As described above, this effect is achieved due to the interplay between the depolarization effect and charge accumulation, however, the depolarization effect by itself can be used to facilitate spikerate dependent plasticity (SRDP). In this case, the conductivity across the device decreases with time after the switching pulse due to the depolarization effect. In order to differentiate between these two effects, different voltage waveforms were used (Figure 5c, d). In case of pure depolarization effect, the readout voltage pulse is preceding the switching pulse (4 V) in the pulse train (inset in Figure 5c), which significantly exceeds the coercive voltage (Vc ≈ 3.1 V) for the given frequency in order to fully reverse the polarization. The conductance changes up to 500% is achieved for the smallest delay time 10 s between pulses. In the second case, the readout voltage pulse (inset in Figure 5d) comes upon the switching pulse amplitude (2.5 V), which is less than the coercive voltage (Vc ≈ 2.8 V) in order to avoid the conductance change caused by the depolarization effect. The effect of the charge accumulation on the interface states results in the conductance change up to 30%. Conclusion Using the temporal dynamics in the ferroelectric HfO2-based tunnel junction with highly doped silicon as a bottom electrode, we have implemented a new type of second-order memristors. The conductivity (synaptic weight) modulation with ROFF/RON ~ 8 is achieved via the gradual switching of the ferroelectric domains affecting the potential barrier in the structure. The built-in electric field and the frequency-dependent response of charged defect states at the interface with Si bottom electrode provide the internal temporal dynamics that can be used for hardware emulation of biological synapse. In particular, the synaptic functions such as short-term plasticity, PPF, PPD and SRDP have been



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demonstrated. In contrast to memristors based on the drift and diffusion, excellent reproducibility and endurance are inherent for the ferroelectric second-order memristor.

ASSOCIATED CONTENT

Supporting Information. Additional information related to the fabrication and characterization of the ferroelectric p+-Si/Hf0.5Zr0.5O2/TiN devices, C-V measurements, simulation of band diagrams and charge accumulation and HAXPES methodology is presented in the Supporting information file (PDF). Corresponding Author *E-mail

address of the corresponding author: [email protected]

Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript.

ACKNOWLEDGMENTS This work was performed using equipment of MIPT Shared Facilities Center with financial support from the Russian Foundation for Advanced Research Projects. The experimental studies of electronic structure at the interfaces was financially supported from the Russian Science Foundation (Grant No. 18-14-00434). Part of the work was carried out using equipment of VNIIOFI Shared Facilities Center 16 ACS Paragon Plus Environment

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for High-Precision Measuring in Photonics (ckp.vniiofi.ru). ABBREVIATIONS HZO, Hf0.5Zr0.5O2; ALD, atomic layer deposition; FE, ferroelectric; CMOS, complementary metaloxide-semiconductor; HZO, Hf0.5Zr0.5O2; TEM, transmission electron microscopy; PUND, Positive Up Negative Down; dc, direct current; ac, alternating current; PPF, paired-pulse facilitation; PPD, paired-pulse depression; SRDP, spike-rate dependent plasticity; STDP, spike-time dependent plasticity; LRS, low resistance state; HRS, high resistance state; CBO, conduction band offset; VBM, valence band maximum. REFERENCES

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