Fundamental Limits on the Subthreshold Slope in Schottky Source

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Fundamental Limits on the Subthreshold Slope in Schottky Source/Drain Black Phosphorus Field-Effect Transistors Nazila Haratipour, Seon Namgung, Sang-Hyun Oh, and Steven J. Koester ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.6b00482 • Publication Date (Web): 25 Feb 2016 Downloaded from http://pubs.acs.org on March 4, 2016

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Fundamental Limits on the Subthreshold Slope in Schottky Source/Drain Black Phosphorus Field-Effect Transistors Nazila Haratipour, Seon Namgung, Sang-Hyun Oh, and Steven J. Koester* Department of Electrical and Computer Engineering, University of Minnesota, 200 Union Street SE, Minneapolis, Minnesota 55455, United States * Address correspondence to: [email protected]

ABSTRACT The effect of thickness, temperature and the source-drain bias voltage, VDS, on the subthreshold slope, SS, and off-state properties of black phosphorus (BP) field effect transistors are reported. Locally backgated p-MOSFETs with thin HfO2 gate dielectrics were analyzed using exfoliated BP layers ranging in thickness from ~ 4 to 14 nm. SS was found to degrade with increasing VDS, and to a greater extent in thicker flakes. In one of the thinnest devices, SS values as low as 126 mV/decade were achieved at VDS = −0.1 V, and the devices displayed record performance at VDS = −1.0 V with SS = 161 mV/decade and on-to-off current ratio of 2.84 × 103 within a 1 V gate bias window. A one-dimensional transport model has been utilized to extract the band gap, interface state density and the work function of the metal contacts. The model shows that SS degradation in BP MOSFETs occurs due to the ambipolar turn on of the carriers injected at the drain before the onset of purely thermionic-limited transport at the source. The model is further utilized to provide design guidelines for achieving ideal SS and meet off-state leakage targets, and it is found that band edge work functions and thin flakes are required for ideal operation at high VDS. This work represents a comprehensive analysis of the fundamental performance limitations of Schottky-contacted BP MOSFETs under realistic operating conditions.

Keywords: Black phosphorus, phosphorene, subthreshold slope, Schottky, MOSFET

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Black phosphorus (BP) has recently emerged as one of the most promising layered semiconductor materials for high-performance transistor applications. Black phosphorus, originally discovered in 1910, is the most stable and least reactive allotrope of phosphorus and can be formed from red phosphorus either using high pressure1 or using a catalytic process.2 The bulk properties of BP were studied several decades ago,3-5 but in the last two years it has received renewed interest as a potential platform for advanced transistor applications.6-13 Fewlayer BP has numerous interesting properties that make it attractive for field effect transistors. First of all, few-layer BP has an energy-dependent band gap that varies between the bulk value of 0.3 eV to between 1-2 eV in monolayer.7,14-16 This controllability holds the prospect for tailoring the on- and off-state current values of BP MOSFETs depending upon the application needs. Several reports showing the thickness-dependence of the on- and off-state current values have been reported.7,16 BP also has much higher mobility compared to most other 2D semiconductors with values as high as 1000 cm2/Vs (600 cm2/Vs) reported for holes and electrons at room temperature.6,17 Conversely, transition metal dichalcogenides (TMDs) have mobilities typically in the 20-50 cm2/Vs range.18,19 The crystal structure of black phosphorus is a puckered honeycomb structure with D2h point-group symmetry,20 and due to the large difference of the effective mass in the zigzag (heavy mass) and armchair (light mass) directions,15,21-22 the mobility has been found to be highly dependent upon the crystal direction.15,23 Several demonstrations of high-performance field-effect transistors have recently been reported as well. The first demonstrations utilized devices with relatively thick gate dielectrics6-7,15,24-25 and while these structures have allowed determination of several important properties of BP MOSFETs, including the maximum drive current, contact resistance and mobility, they do not provide insight into the important practical performance capabilities of BP MOSFETs. For instance, in


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logic devices, the subthreshold slope, SS, is of critical importance to determine the practical onstate drive current that can be achieved. If SS is degraded, the drive current (at fixed off-state current) will be substantially reduced compared to the maximum current that the device can support. Similarly, the contact resistance and mobility can also be affected by the dielectric material and thickness.26 Therefore, it is critical that assessments of the ultimate device performance be carried out using realistic geometries. In this work, we perform a detailed experimental and theoretical assessment of the performance of BP p-MOSFETs with a focus of the factors that affect the subthreshold slope. We demonstrate devices with record-low subthreshold slopes27-28 at high bias voltages, though we show that, unlike TMDs, the subthreshold slope degrades significantly both at high bias voltages and in thicker samples where the band gap is closer to its bulk value. We verify the experimental results with transport simulations based upon a Schottky-barrier limited current model and provide critical insight into the factors that limit the subthreshold slope in BP MOSFETs and provide guidelines for how to achieve devices with ideal turn off behavior.

Results and Discussion The device fabrication is similar to that described previously.29-30 The starting substrate was a Si wafer upon which a 100-nm-thick SiO2 layer was grown. After formation of alignment marks, quasi-planarized gate electrodes were first formed by using e-beam lithography (EBL) to form gate patterns in PMMA and then recessing the SiO2 by 50 nm using a combination of wet and dry etching. Ti/Pd (10/40 nm) was then evaporated and lifted off to form the gate electrode, followed immediately by atomic layer deposition (ALD) of a thin (10-15 nm) HfO2 for the gate dielectric. This gate stack configuration is beneficial because the HfO2 nucleates very smoothly on Pd thus allowing thinner gate dielectrics to be realized compared to dielectrics grown directly 3 ACS Paragon Plus Environment

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on the 2D material.29 Black phosphorus was then exfoliated from bulk crystals and aligned and transferred onto the local back gates. Source and drain contacts were patterned using EBL, followed by deposition and lift off of contact metallization consisting of 10 nm Ti and 90 nm Au. The effective channel length, defined as the distance between the edges of the source and drain electrodes ranged from 0.2 µm to 1.0 µm. After the contact metallization step, all devices were transferred into a vacuum probe station and electrical characterization was performed (see Methods section for details). After initial electrical characterization, ALD Al2O3 (20-30 nm) was deposited to act as a passivation layer and the samples were measured again in vacuum. After the device characterization was completed, atomic force microscopy (AFM) was performed on the passivated devices to determine the thickness, tBP, of the BP flakes. An area 3D map and line scan of a typical device are shown in Figs. 1a and 1b and the devices had BP thicknesses in the range of 4 nm to 14 nm. Raman spectroscopy was also performed on the devices after electrical characterization had been completed (Fig. 1c), and the existence of black phosphorus was confirmed by identification of the ~ 463 cm-1, ~ 436 cm-1 and ~ 363 cm-1, peaks, which are in good agreement with previous studies.31 It has also previously been shown that Raman spectroscopy can be used to determine the crystal orientation of BP flakes.32,33 However, Raman spectroscopy is time consuming and requires relatively highintensity illumination. Therefore, in this work, the crystal direction was determined using optical reflectance measurements. The optical reflectance technique is based upon the principle that in a material with anisotropic electrical conductivity, the optical absorption will also vary depending on the crystallographic orientation.34 In these measurements, the reflectance was measured by illuminating the device using a focused spot of linearly polarized white light, rotating the polarization angle from 0° to 360° and then measuring the reflectance at a specific wavelength 4 ACS Paragon Plus Environment

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(Fig. 1d). The minimum reflectance corresponds to the direction with higher light absorption and therefore higher mobility. In this work, a total of 10 devices were fabricated and a summary of the devices and dimensional parameters is provided in Table 1. All the electrical measurements were performed in vacuum and most devices were measured before and after Al2O3 passivation. A plot of the drain current, ID, as a function of the gate-tosource voltage, VGS, at drain-to-source voltages, VDS, from −0.1 V to −2.5 V is shown in Fig. 2a for an unpassivated device at room temperature. This device (#3) had BP thickness of 4.5 nm. As can be seen in the figure, before Al2O3 passivation, the BP MOSFET shows strong p-type behavior with an on-to-off current ratio over 105. The off-state leakage current is observed to increase with increasing VDS, but the on-to-off current ratio remains on the order of 103 even at VDS = −2.5 V. Fig. 2b shows the ID vs. VGS characteristics for the same device after passivation with ALD Al2O3. The plot shows that the device becomes much more ambipolar, with the nchannel branch becoming much more symmetric with the p-channel branch. Interestingly, while the on-to-off current ratio at low VDS is little changed, at high VDS, the minimum current increases dramatically, leading to an on-to-off current ratio less than 100. To further investigate the degradation of the turn-off characteristics at high drain bias, the value of SS was extracted and plotted vs. current for the same device both before (Fig. 2c) and after (Fig. 2d) passivation. At VDS = −0.1 V the minimum subthreshold slope is 140 mV/decade before passivation and 180 mV/decade after passivation. Furthermore, the subthreshold slope is observed to increase dramatically for both situations at higher values of VDS, but to a greater extent in the passivated device. Additionally, the current at which the minimum SS value occurs also increases at higher drain bias, further exacerbating the degradation of the turn-off behavior. Figs. 2e and 2f show the minimum subthreshold slope, SSmin, plotted vs. VDS for both forward 5 ACS Paragon Plus Environment

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(increasing VGS) and reverse (decreasing VGS) sweep directions. The plots show that SSmin has a relatively constant value at low |VDS| which is limited by the interface state density, but then increases monotonically with increasing |VDS|. Given the relatively long gate lengths in our devices compared to the scaling length, λ, this increase is not due to the drain-induced barrier lowering as would be found in short gate-length Si MOSFETs. Rather, this increase is due to the “turn on” of the ambipolar current arising from the electron back-injection from the drain. Further analysis of this behavior will be provided later in the manuscript. This process is similar to the gate-induced drain leakage (GIDL) in conventional MOSFETs, with the difference that in the BP MOSFETs, the drain current arises from injection from the drain Schottky contact, while in conventional MOSFETs, the GIDL current is due to band-to-band tunneling. To provide additional insight into the factors that limit the turn-off characteristics of BP MOSFETs, the linear and saturation values of the on-state current, ION, off-state current IOFF, and SSmin were determined for different thicknesses of the BP layer and the results are shown in Fig. 3. In these plots, we define IOFF as the minimum current, while ION is defined as the drain current at fixed gate voltage difference, ∆V, from the voltage at which the minimum current occurs. For all the plots in Fig. 3, ∆V = −1.5 V. Figs. 3a and 3b show ION and IOFF plotted as a function of the BP flake thickness in the linear (VDS = −0.1 V) and saturation (VDS = −1.5 V) regimes. The values both before and after passivation are shown. The results show that for thin flakes (tBP ~ 4 nm), reasonable values of IOFF can be maintained. In the linear regime, IOFF is < 10 pA/µm and while IOFF increases in saturation, it retains a reasonable value of ~ 1 nA/µm. The ION value in saturation is relatively low (< 10 µA/µm) for thin flakes, however. However, the situation is very different for thicker flakes. For the thickest flake in this study (tBP = 13.8 nm), IOFF ~ 100 nA/µm in the linear regime, roughly five orders of magnitude higher 6 ACS Paragon Plus Environment

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than the 4-nm-thick flakes. Moreover, at VDS = −1.5 V, despite the high values for the on-state current (ION > 100 µA/µm), the off-state current is very high (IOFF > 10 µA/µm), far exceeding the ITRS off-current specifications, even for high-performance devices. This degradation is attributed to the reduced band gap as the BP thickness increases. To further highlight the effect of thickness and bias voltage on the device performance, the ION/IOFF ratio is plotted vs. tBP in the linear and saturation regimes in Figs. 3c and 3d, respectively. These results further emphasize the degradation in modulation that occurs at high drain bias in BP. In fact, for thick BP, at VDS = −1.5 V, the on-off ratio is similar to that of graphene MOSFETs.35 Finally, Figs. 3e and 3f show SSmin vs. tBP at VDS = −0.1 V and −1.5 V, respectively. The results in Fig. 3e show an additional interesting trend, which is that the linear SSmin generally improves after surface passivation (except in the thinnest flakes). We attribute this trend to the high-temperature (200 °C) process of the ALD passivation step, which is believed to desorb moisture from the BP/HfO2 interface, thus reducing the density of interface traps, Dit. However, at high VDS, the opposite trend is observed, where SSmin is degraded after passivation. We attribute this trend to a shift in the effective Schottky barrier height after passivation toward midgap from nearer to the valence band edge. This result is consistent with previous observations for Al2O3 passivation of BP MOSFETs.30,36 In this study, the scaling length, λ, for all the devices ranges from 7.7 to 11.7 nm. Based upon prior results on Si MOSFET scaling,37 short channel effects should only begin to degrade the subthreshold slope when Leff < 10λ. Given that all the gate lengths in our work are 200 nm or greater, the impact of short-channel effects on SSmin in the data shown in Figs. 3e and 3f is expected to be negligible. The results in Fig. 3 show that devices with thin BP channels suffer less performance degradation at high bias voltages compared to thick devices. In Fig. 4, we show the transfer and 7 ACS Paragon Plus Environment

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output characteristics of device #2 (one of the thinnest device characterized in this study). Fig. 4a shows ID vs. VGS at VDS = −0.1 V and −1.0 V. The values of SSmin extracted from the data are 126 mV/decade at VDS = −0.1 V and 161 mV/decade at VDS = −1.0 V. Furthermore, we benchmarked the performance at VDS = −1.0 V, −1.5 V and −2.0 V within a gate voltage window equal to VDS, and found on-to-off current ratios of 2.84 × 103, 4.75 × 103, and 6.85 × 103 respectively. To our knowledge these are the highest on-to-off current ratios within these fixed VGS windows reported to date for any BP MOSFET. The output characteristics for the same device are shown in Fig. 4b, where long-channel MOSFET behavior is observed, as expected, with good current saturation. Further insight into the limitations on the subthreshold slope in BP MOSFETs can be obtained by examining their temperature-dependent behavior. Figs. 5a and 5b show SS plotted vs. ID for two BP MOSFETs in the linear regime (VDS = −0.1 V). Fig. 5a utilizes a thinner flake before passivation (tBP = 4.3 nm, device #2) while Fig. 5b shows results for a thicker flake after passivation (tBP = 8.1 nm, device #7). For both devices, the subthreshold slope is observed to decrease with decreasing temperature, as expected. However, for device #2, SS shows a relatively “flat” minimum value over roughly one decade of drain current, suggesting it is reaching the thermionic limited regime, while in device #7, the minimum SS occurs only in a very narrow range of current values. In Figs. 5c and 5d, SSmin is plotted vs. temperature at VDS = −0.1 V for both devices. In the standard thermionic limited regime of operation, SSmin vs. temperature can be utilized to extract the interface trap density, Dit, according to SS min =

C + C it  kT ln (10 ) ⋅  1 + dep q C ox 

  , 

(1)


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where k is Boltzmann’s constant, T is the temperature, Cdep is the depletion region capacitance, Cit is the interface trap capacitance and Cox is the oxide capacitance. For ultra-thin body devices, it is assumed that the device is fully depleted and hence Cdep = 0. The value of Cox in our devices is estimated to be 0.98 µF/cm2, based upon previous measurements that showed the dielectric constant in our HfO2, εHfO2, is 16.6.29 Using this value, and assuming Dit = Cit/q2, then we extract a value of Dit = 5.3 × 1012 cm-2/eV for device #2. If the same procedure is applied to device #7, a much higher apparent value of 1.1 × 1013 cm-2/eV is obtained. However, because the latter device may not be in the purely thermionic-limited regime, this value may not be valid, as will be described later. The temperature-dependence of SSmin has also been studied for different bias voltages, where both a thin (tBP = 4.3 nm, device #2) and thick (tBP = 8.1 nm, device #7) flake were studied and these results are shown in Figs. 5e and 5f. For the thin flake, the subthreshold slope dependence on temperature becomes weaker with increased VDS, but some temperature dependence remains. For the thicker flake, as the bias voltage increases, the temperature dependence of SSmin steadily weakens, and becomes essentially temperature independent at VDS = −2.5 V. We attribute the differences in the temperature-dependent behavior of thick and thin flakes to differences in the origin of the current injected from the drain electrode. In thin flakes, the current arising from back-injection of electrons from the drain is largely thermionic in nature, even at high drain bias. This is due to the large band gap, and thus large Schottky barrier height for electron injection at the drain contact. For thicker flakes, the barrier height for electron injection is lower, and at high drain biases, the injection transitions to purely tunneling-dominated current flow. In order to better understand our experimental observations, a one-dimensional analytical model was developed which follows the procedure outlined by S. Das, et al.16,38 and A. 9 ACS Paragon Plus Environment

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Penumatcha, et al..39 In this model, three different transport regimes are included: band-to-band tunneling, thermionic field emission through a Schottky barrier and thermionic emission. The energy-dependent tunneling probability, T(E), was calculated by using the Wentzel–Kramers– Brillouin (WKB) approximation:  x2  T (E ) = exp  − ∫ κ (E )dx  ,    x1 

(2)

where κ(E) is the wave function in the tunneling regime, and x1 and x2 are the endpoints for the tunneling integration. An elliptical model40 for κ(E) was utilized to account for the imaginary band structure for the direct-gap semiconductor:  mv E (2 − E / E q ) , for 0 < E < E q   h κ =  mc ( E g − E )[ 2 − ( E g − E ) /( E g − E q )] , for E q < E < E g  h

(3)

where Eq = Eg × [mc/(mc + mv)], mc and mv are the electron and hole effective masses, respectively, in the direction of transport, ћ is the reduced Planck’s constant, Eg is the band gap, and E is the energy relative to the valence band edge. Here, the same values of mc and mv as used in reference 39 were utilized. The valence and conduction band bending at the contacts has been assumed to have an exponential dependence on distance ( ∝exp(-x/λ)) at the metalsemiconductor junctions, where the = ( / ) . Here, εBP is the dielectric constant of the BP, and tHfO2 is the gate dielectric thickness. For these simulations, a value of εBP = 8.3 was assumed. At this point, we note again that none of the devices are expected to exhibit substantial short-channel effects since the maximum λ in our devices (λ = 11.7 nm for the 13.8nm BP flake) is still much less than the effective gate lengths (Leff = 0.2 – 1.0 µm) used in this


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study. Therefore, SS degradation due to the drain-induced barrier lowering can be ignored. Both source and drain energy barriers were considered and therefore the total transmission is () ()

() = ( ())(

())

,

(4)

where TS(E) and TD(E) are the energy-dependent transmission coefficients at the source and drain, respectively. Finally the current per unit width for electrons can be obtained from =

! "

(

#

)*

()$()(% () − % ())',

(5)

where the M(E) is the number of one-dimensional modes in the channel per unit width, f1(E) and f2(E) are the Fermi-Dirac distribution functions at the injection and receiving contacts, respectively, and ECB is the conduction band energy in the center of the channel between source and drain. This current can also be found for holes by changing the integration range from -∞ to EVB, where EVB is the valence band energy in the center of the channel. The total current can then be obtained by adding the electron and hole components of current. It should be noted that, similar to reference 39, ECB and EVB are assumed to change in proportion to VGS/(1+Cit/Cox), which is a valid assumption for fully-depleted devices operating near the off-state region of operation, where the carrier concentration in the channel is very low. The model was fit to the experimental data using Eg, Dit, and the contact metal work function, ΦM, as fitting parameters. Here, we assumed that the midgap energy of BP is 4.00 eV, and that the increase in Eg with decreasing thickness is symmetric about this energy. In contrast to previous work,39 we found out that the anisotropic nature of BP is an important fitting factor and needs to be considered for obtaining an accurate fit to the experimental results. We attribute this discrepancy to the more mid-gap nature of our Ti contacts, compared to the Py and Pd contacts used in reference 39, which cause the effective mass to dramatically affect the tunnel injection for both the electron and hole currents. The fitting results for two devices (before and after 11 ACS Paragon Plus Environment

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passivation) with the BP thicknesses of 4.5 nm (device #3) and 8.1 nm (device #7) are shown in Fig. 6a. These results show that good fitting can be obtained for VGS values in the off-state region. Fig. 6b shows a summary of the extracted fit parameters and several interesting results are found. First of all, we find that the extracted band gap increases slightly after passivation, presumably due to the slight thinning of the BP when exposed to atmosphere. In general, the Dit is also found to improve after passivation, which we attribute to bake out of trapped moisture at the BP/HfO2 interface during the passivation layer deposition step. Secondly, we find that for device #7, the Dit extracted from the fit is indeed different than obtained by using (1). This can be understood by examining the “ideal” value of SS for the case where Dit = 0, which is found to be well above 60 mV/decade. This further supports that the turnoff of these devices is not fully limited by thermionic mechanisms. We have found some devices (e.g. device #3 before passivation) that can achieve ideal subthreshold slope at room temperature and we attribute this to the more p-type contacts that can be generally achieved in devices before passivation. Finally, Fig. 6c shows a plot of the extracted band gap vs. thickness from the fitting of all the passivated devices compared with density functional theory calculations from the literature.14 The good agreement provides additional confidence in our fitting procedure. The extracted Ti work functions for all passivated devices are found to be very similar with average value of ΦM = 4.03 + 0.02 eV, and these results confirm that Ti lines up close to the midgap in Al2O3-passivated BP MOSFETs, consistent with previous reports.30,41 We do note that there are several factors that can cause uncertainty in the parameter extraction, which are not taken into account in the model. These issues include possible BP thickness non-uniformity, differences between the work function of the source and drain contacts, and the fact that only a simple 1D model is used to describe the carrier injection from the contacts.


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We used the model to understand the current device performance limitations, and also predict the metal work function and thickness values that Schottky-contacted BP MOSFETs must have in order to achieve ideal subthreshold slope at practical operating conditions. The simulated ID vs. VGS characteristics at VDS = −1.0 V for devices with BP thickness of 4 nm, 8 nm and 12 nm are shown in Fig. 7a. In this simulation, a metal work function of 4.10 eV was used for the simulations and the Dit was assumed to be 0. The transport is considered to be along the armchair (low-mass) direction, which is the preferred direction for high performance BP MOSFETs due to the higher mobility and injection velocity. The figure shows that the subthreshold slope is ~ 150 mV/decade for the 4-nm BP simulation and even higher for the 8-nm and 12-nm devices. The off current is higher than our experimental devices with the same parameters, primarily due to the lower tunneling mass chosen for these simulations. The inset shows the value of SSmin as a function of VDS for different BP thicknesses. It is clear that SSmin degrades with increasing VDS and BP thickness, consistent with the experimental trends in Fig. 2. The simulations provide insight into the degradation of the subthreshold slope at high VDS, for the situation where the Fermi-level is near mid-gap. The band diagram shows that, at the ambipolar point, the electron current turns on before the hole current becomes fully thermionic-limited, and it is this behavior that leads to non-ideal SSmin. This degradation becomes more significant at higher VDS and in thicker BP MOSFETs due to the higher drain-side electron current under these conditions. In order to explore the effect of the contact Schottky barrier height on the BP MOSFET subthreshold swing, simulations with ideal band edge contacts were investigated. The results for BP thickness of 4 nm, 8 nm and 12 nm at VDS = −1.0 V are shown in Fig. 7b. In contrast to Fig. 7a, these simulations show that nearly-ideal subthreshold slope can indeed be achieved at high 13 ACS Paragon Plus Environment

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VDS. The inset again shows SSmin vs. VDS, which shows that for the 4-nm BP, that SSmin < 70 mV/decade can be achieved up to VDS = −1.5 V, though with increasing thickness, the voltage at which SSmin begins to degrade increases. This behavior is explained by the band diagrams at the minimum current point (at VDS = −1.0 V), where, unlike in the case of near-midgap work function contacts, in the optimized case, the ambipolar electron current only turns on after the device has reached the thermionic-limited transport regime. Although our simulation results show that band edge work function can be used to achieve ideal SSmin at high VDS, the value of the off current remains a concern, particularly for thicker BP flakes. In order to ensure that the off-state leakage is less than 100 nA/µm at VDS = −1.0 V, then thin flakes (~ 4 nm or less) are required. It is also interesting that the minimum currents for the cases in Figs. 7a and 7b are not substantially different, showing that the off-current is primarily determined by the flake thickness and not the metal work function. This is due to the fact that for band-edge work functions, the electric field at the drain is increased, partially counter-acting the higher Schottky barrier height. Additional studies are needed to determine the crystal orientation that provides the best compromise between on- and off-state performance. More advanced concepts such as heterostructures and strain also need to be studied further in determining the optimal device parameters for BP MOSFETs.

Conclusion In conclusion, we have performed a comprehensive experimental and theoretical evaluation of design and operating parameters that limit the subthreshold slope in black phosphorus MOSFETs. We have fabricated a series of black phosphorus MOSFETs that utilize thin (< 15nm-thick) HfO2 gate dielectrics and have flakes varying in thickness from 4 to 14 nm. We find that the off-state leakage current and subthreshold slope are degraded with increasing flake 14 ACS Paragon Plus Environment

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thickness and increased source-to-drain bias voltage. The best devices display saturated subthreshold slope of 161 mV/decade and on-to-off current ratio of 2.84 × 103 within a bias window of 1 V, the best performance reported to date for any BP MOSFET. The drain-voltageinduced degradation is more prominent in thicker flakes due to the reduced energy gap. We have further shown that extraction of the interface trap density from the temperature-dependent subthreshold slope must be performed with care, as it can overestimate the trap density in devices that cannot achieve an ideal subthreshold slope, even in the absence of interface traps. Our analytical transport model for the source and drain Schottky contacts shows that non-ideal subthreshold slope occurs when the drain side carrier injection turns on before the source current transitions to the purely thermionic-limited regime. This model can then be used to determine design guidelines for achieving ideal SS and reasonable off-state leakage. The insights provided by this work will be invaluable for the design of BP MOSFETs for realistic logic, memory and analog circuit applications.

Methods The BP field effect transistors were fabricated on a heavily-doped n-type silicon substrate upon which 100 nm of SiO2 was grown by thermal oxidation. To pattern the alignment marks the wafer was coated with PMMA and electron beam lithography was utilized to pattern openings for alignment marks. After development in MIBK:IPA (1:3), electron-beam deposition of Ti/Au (10 nm / 40 nm) was performed and the residual resist was lifted off in acetone. Local back gates were patterned and developed using the same method and then SiO2 was recessed by 50 nm using a combination of dry etch (CHF3/CF4/Ar) to create a 40-nm deep recess followed by a wet etch (10:1 BOE) to create a roughly 50-nm recess in the SiO2. Ti / Pd (10 nm / 40 nm) was evaporated using electron-beam evaporation as gate electrodes. After lift off in acetone / IPA; 15 ACS Paragon Plus Environment

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HfO2 was deposited using atomic layer deposition (ALD) using Tetrakis(dimethylamido) hafnium(IV) and water vapor as the precursors. Black phosphorus flakes were mechanically exfoliated and transferred onto a PDMS stamp activated on glass slides. With a specially designed optical alignment station; few-layer BP flakes were aligned and transferred onto the gate finger on the HfO2-coated substrate. To slow down the degradation of BP during processing,42 we spun PMMA on the BP flakes immediately after transfer and kept the sample in a dark desiccator box between steps in the fabrication process. Source and drain contacts were defined by electron beam lithography. After development in MIBK:IPA (1:3), Ti/Au (10nm / 90 nm) was deposited by electron beam deposition and the sample again lifted off in acetone. The samples were quickly transferred to the vacuum probe station for performing the initial measurements. Later the samples were passivated by 20-30 nm Al2O3 at 200 °C using ALD system and again transferred to the vacuum probe station to perform additional measurements after passivation. Raman spectroscopy was performed using a Witec Alpha300R Confocal Raman Microscope with an excitation wavelength of 514.5 nm and 1800 g/mm grating. Atomic force microscopy was performed using a Bruker Nanoscope V Multimode 8 scanning probe microscope in peak force tapping mode. The scanning resolution is 512 x 512 pixels. The 3D image was extracted and plotted from the AFM data using GwyddionTM software. All electrical measurements were performed using an Agilent B1500A semiconductor parameter analyzer where high-resolution SMUs were connected to the source and drain terminals, and a medium-resolution SMU connected to the gate electrode. In addition, all measurements were performed under vacuum (base vacuum ~10-5 Torr) in a Lakeshore CPX-VF cryogenic probe station. For the data shown in Figs. 2, 3, 4 and 6, no cryogen was utilized and


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the samples were measured at ambient room temperature. For the temperature-dependent electrical measurements shown in Fig. 5, liquid nitrogen was used as the cryogen. In these measurements, the sample was allowed to cool down to the base temperature (77 K) and the sample was measured at increasing temperatures of 77 K, 120 K, 140 K, 180 K, 200 K, 220 K, 240 K, 260 K, 280 K and 298 K. For these measurements, the probes were thermally coupled to the sample stage by copper braids to ensure that no accidental heating/cooling of the sample occurred as a result of the probes.

Conflict of Interest The authors declare no competing financial interest.

Acknowledgement This work was supported by the National Science Foundation (NSF) through the University of Minnesota MRSEC under Award No. DMR-1420013 (N.H., S.-H.O., S.J.K.). This work also received partial support from the Air Force Office of Scientific Research under Award No. FA9550-14-1-0277 (S.N., S.J.K.). Device fabrication was performed at the Minnesota Nanofabrication Center at the University of Minnesota, which receives partial support from NSF through the National Nanotechnology Coordinated Infrastructure (NNCI). Portions of this work were also carried out in the University of Minnesota Characterization Facility, which received capital equipment from the NSF.

Supporting Information Available Supporting information includes a diagram of the fabrication sequence, optical images of the completed BP MOSFETs, optical reflectance vs. orientation for several devices, output and double sweep transfer characteristic of several devices, and device stability analysis.


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Figure 1. (a) Three-dimensional atomic force microscopy (AFM) height map of device #7. The plot shows the planarized buried gate electrode, the BP flake and the source-drain metallization. (b) AFM line scan of the BP flake in (a) showing flake thickness of 8.1 nm. (c) Raman spectroscopy taken from a BP MOSFET confirming the presence of BP. (d) Angular dependence of optical reflectance for a BP flake (blue symbols). The angular orientation was determined as the minimum in angle of the sinusoidal fit (dashed line).

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Figure 2. Effect of drain bias on BP MOSFET turn-off characteristics. (a)-(b) Drain current, ID, vs. gate-to-source voltage, VGS, for a BP MOSFET with flake thickness of 4.5 nm (device #3) (a) before and (b) after passivation. These characteristics were taken in the forward sweep direction (increasing VGS). The drain-to-source bias, VDS, is varied from −0.1 V to −2.5 V with the steps of −0.1 V. (c)-(d) Subthreshold slope, SS, vs. ID for VDS between −0.1 V and −2.5 V (c) before and (d) after passivation. (e)-(f) Minimum subthreshold slope, SSmin, vs. VDS for same device as in (a) before and after passivation. The values for both the forward and reverse sweeps are shown.


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Figure 3. Thickness dependence of various BP MOSFET performance parameters. In all cases, open (closed) circles indicate devices before (after) Al2O3 passivation, and all values were derived from the forward (VGS increasing) sweep direction. (a)-(b) ION (blue circles) and IOFF (red circles) vs. BP thickness at (a) VDS = −0.1 V and (b) VDS = −1.5 V. Here IOFF is defined as the minimum current and ION is defined as the drain current at VGS = VGMIN – 1.5 V. (c)-(d) ION/IOFF current ratio vs. BP thickness at (c) VDS = −0.1 V and (d) VDS = −1.5 V. (e)-(f) Minimum subthreshold slope, SSmin, vs. BP thickness at (e) VDS = −0.1 V and (f) VDS = −1.5 V.


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Figure 4. Room-temperature current-voltage characteristics of device #2 with tBP = 4.3 nm. (a) Plot of drain current, ID, vs. gate-to-source voltage, VGS, before passivation. Both forward and reverse sweep directions are shown, and curves are shown at drain-to-source voltage, VDS = −0.1 V (blue) and −1.0 V (black). The minimum subthreshold slopes are SSmin = 126 mV/decade and 161 mV/decade, respectively. Here SSmin is the average of minimum SS for the forward and reverse sweep. For each sweep direction, the solid symbols show the onand off-currents within a 1 V window at VDS = −1.0 V, and the average on-to-off current ratio is found to be 2.84 × 103. (b) Plot of ID vs. VDS for same device as in (a) where the top curve is at VGS = −2.5 V and the gate voltage step, ∆VGS = +0.2 V.


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Figure 5. Temperature-dependent behavior of BP MOSFETs. (a)-(b) Subthreshold slope, SS, vs. drain current, ID, for device #2 (tBP = 4.3 nm) before passivation and device #7 (tBP = 8.1 nm) after passivation. The drain-to-source bias voltage, VDS = −0.1 V. These characteristics were taken in the forward sweep direction. (c) Plot of SSmin vs. temperature, T, for device #2, where the interface trap density Dit is extracted from data. The symbols are the experimental data and the dashed line is the fit for Dit = 5.3 × 1012 cm-2/eV. (d) SSmin vs. T for device #7. Here, an “apparent” Dit is extracted, though later in the text we show that this is not the true Dit due to the fact that the predicted SSmin value is > 60 mV/decade when Dit = 0. (e) Plot of SSmin vs. T for device #2 for values of VDS ranging from −0.1 V to −2.5 V. (f) SSmin vs. T for device #7 using the same symbols as in (e). .


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Figure 6. Model fitting results for BP MOSFETs. (a) Drain current, ID vs. normalized gate-tosource voltage, VGS−VMIN for device #3 and #7 at the VDS = −0.1 V before and after Al2O3 passivation. The experimental data is shown by the symbols and the modeling results by the solid lines. (b) All fitting parameters used in (a) where the free parameters are the band gap, Eg, metal work function, ΦM, and interface trap density, Dit. The table also shows the simulated values of SSmin based upon the fitting parameters when Dit = 0. (c) Comparison of BP band gap vs thickness extracted from the model (red symbols) and previously reported DFT calculations (black dashed line).14 This plot only includes Eg values extracted from passivated devices.


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Figure 7. Simulated drain current, ID, vs. normalized gate voltage, VGS-VMIN, for BP MOSFETs assuming various input parameter conditions. For both plots, the BP thicknesses were assumed to be 4 nm (—), 8 nm (- - -) and 12 nm (- . -), and the sample is assumed to be oriented along with armchair crystal direction. (a) ID vs. VGS-VMIN for a BP MOSFET at VDS = −1.0 V using a contact metal with work function 0.1 eV below midgap. (b) ID vs. VGSVMIN for a BP MOSFET at VDS = −1.0 V using contact metal with work function aligned to the valence band edge. Insets: Minimum subthreshold slope, SSmin, vs. drain-to-source voltage, VDS, for three different BP thicknesses. Above: Band diagrams showing color-map of the energy-resolved current at points A,C and B,D for the 12-nm and 4-nm-thick BP devices, respectively.


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Table 1. Complete list of devices analyzed in this study. In all cases, the BP thickness and width were determined by atomic force microscopy (AFM) after passivation. The effective gate length, Leff, defined as the separation between the source and drain electrodes, varied from 0.2 µm to 1.0 µm and two different thickness (10 nm and 15 nm) of HfO2 gate dielectrics were also used. The rotational angle was determined using optical reflectance measurements, where 0° is defined as being along the zigzag direction and 90° along the armchair direction.


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Table of Contents Figure


Fundamental Limits on the Subthreshold Slope in Schottky Source

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