Gate Modulation of Excitatory and Inhibitory Synaptic Plasticity in a

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Gate Modulation of Excitatory and Inhibitory Synaptic Plasticity in a Low-Temperature Polysilicon Thin Film Synaptic Transistor Nian Duan, Yi Li, Hsiao-Cheng Chiang, Shin-Ping Huang, Kang-Sheng Yin, Jia Chen, Chung-I Yang, Ting-Chang Chang, and Xiangshui Miao ACS Appl. Electron. Mater., Just Accepted Manuscript • DOI: 10.1021/acsaelm.8b00060 • Publication Date (Web): 26 Dec 2018 Downloaded from http://pubs.acs.org on January 4, 2019

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ACS Applied Electronic Materials

Gate Modulation of Excitatory and Inhibitory Synaptic

Plasticity

in

a

Low-Temperature

Polysilicon Thin Film Synaptic Transistor Nian Duan, † Yi Li,*,† Hsiao-Cheng Chiang, ‡ Shin-Ping Huang, ‡ Kang-Sheng Yin, † Jia Chen, † Chung-I Yang, ‡ Ting-Chang Chang,*, ‡ and Xiang-Shui Miao*,† † Wuhan National Research Center for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China ‡ Department of Physics, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan.

ACS Paragon Plus Environment

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ABSTRACT

Neuromorphic computing with intelligent power-efficient data processing has become an innovative technology to overcome the performance bottleneck of traditional von Neumann-type computing architecture. As an essential element to construct a neuromorphic system, a kind of artificial synapse with high technology maturity, rich functionality and homeostatic regulation based on simple and robust mechanism is in urgent demand. Here, we propose the dual-gate low-temperature polycrystalline silicon thin film transistor to be a prospective candidate for scalable biomimetic synapse. Fundamental bilingual homosynaptic behaviors, including excitatory postsynaptic current, inhibitory postsynaptic current and paired pulse facilitation, have been successfully emulated, based on the charge trapping mechanism under electric pulse stimulation at either top or bottom gates. The strength of the top-gated induced excitatory and inhibitory responses can be dynamically modulated by the electrical biases at the modulatory bottom gate, indicating the realization of heterosynaptic plasticity. Furthermore, the transition between excitatory and inhibitory modes can be easily controlled by the


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interplay of the voltage biases at top and bottom gates. These results indicate the commercial thin-film transistor technology could find its novel fundamental role in the emerging artificial intelligence era.

KEYWORDS: Neuromorphic computing, low-temperature polysilicon synaptic transistor, bilingual synaptic plasticity, heterosynaptic plasticity, gate modulation


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INTRODUCTION

Nowadays, a tremendous upsurge in interest in exploring the neuromorphic computing is on the rise. Inspired by the immense parallelism and function flexibility of the human brain, the configuration of neuromorphic computing is different from the conventional von Neumann architecture, of which the limitations of parallel computation and high power consumption may be the main concern in the artificial intelligence era.1–3 In neuron system, the most fundamental computing element connecting neurons to help with communication is the synapse, the plasticity of which is essential to cognitive memory and learning functions.4 Therefore, the construction of artificial synapse with biomimetic functionality has been one of the preferential considerations to realize a neuromorphic system on the hardware level.

To date, various emerging nano-devices have been utilized as the artificial synapse to emulate the fundamental synaptic function. Especially, two-terminal memristive devices such as memristor5–10 and phase change memory11–13 with the ability to be programmed into different conductance states have become hotspot of research focus.


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However, since signal application process and signal transmission in the two-terminal device are performed step by step which is different from the brain synapse, the sync problem of learning process and signal transmission in two-terminal device is nonnegligible and needs to be taken into consideration.14 Recently, synaptic transistor devices with multiple terminals have been introduced to realize comprehensive synaptic functions. In such kind of artificial synapses, the gate electrode is regarded as presynaptic terminal transmitting the pre-spike (VG), and current flowing through source and drain (IDS) represents the postsynaptic signal. During the operation, the application of presynaptic signals at the gate and the transmission of postsynaptic signals between the source and drain are synchronized. Besides, the conductance tuning of memristors depends on the motion of ions, random formation and disruption of conducting filaments, and that of phase change devices relies on the uncontrolled temperature induced structure transformation in chalcogenide phase change materials. These physical processes lead to large performance variability, which severely degrades the learning performance of artificial neural network. In contrast, the transistor devices are preferred due to their electronic based mechanism, higher performance controllability and mature fabrication


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techniques. So far, many kinds of transistors have been studied as artificial synapses, including electron-double-layer electrolyte-based transistors,15–17 carbon nanotube transistors,18,19 ferroelectric transistors,20,21 metal oxide-based transistors,22,23 Li ion electrolyte-based transistors24,25 and organic synaptic transistors.26 Although different mechanisms of diverse channel materials in these works provide possibility for richer synaptic functions, such as heterosynaptic plasticity and metaplasticity, they also bring in problems of performance stability and repeatability. In addition, high compatibility of the artificial synaptic device with the CMOS technology should be taken into account for further consideration in large-scale neuromorphic system integration.

Furthermore, realization of rich functionality and homeostatic regulation of excitability of a synapse in a single device is difficult to achieve. Balance between excitatory and inhibitory synaptic behaviors is of great significant in biological system, so there is an urgent need of a homeostatic role to provide stability of operation in the face of on-going synaptic changes.27,28


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In this work, for the first time we proposed a dual-gate synaptic transistor based on low-temperature polysilicon (LTPS) material, which is the mainstream technology for active matrix displays including tablets, televisions, and smartphones. In the LTPS synaptic transistor device, both the top gate and bottom gate can serve as the presynaptic input terminal or modulatory terminal, and the postsynaptic response is represented by the change of current flowing through source and drain. For the sake of discussion, the top gate is regarded as presynaptic terminal while the bottom gate acts as modulatory terminal in the main body of this paper. Based on simple charge trapping mechanism and electrical operation on gate, the work has been carried out as follows. First, basic synaptic behaviors including excitatory postsynaptic current (EPSC), inhibitory postsynaptic current (IPSC) and paired pulse facilitation (PPF) have been successfully realized in a single device, by applying positive and negative electrical pulses on the top gate when the bottom gate voltage keeps constant to hold the base postsynaptic current. Then, the regulation of postsynaptic current baseline and EPSC/IPSC strength under different bottom gate voltage was demonstrated. Finally and most importantly, the manipulation of the transition between the excitatory and inhibitory functions was demonstrated by


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introducing the bottom gate pulses as the modulatory signals, thus balancing the response of postsynaptic current to play a homeostatic role in the neural system.

EXPERIMENTAL DETAILS

Device fabrication. The p-type LTPS synaptic transistors in this work were deposited on a glass substrate. First, the Mo layer was deposited as the bottom gate on the substrate. Then, a buffer layer containing SiO2 and Si3N4 was fabricated. Next, a 30 nm amorphousSi (a-Si) film was deposited by plasma enhanced chemical vapor deposition (PECVD) on the buffer layer, followed by dehydrogenation via the furnace annealing process. Then the N- channel was formed in the a-Si films by phosphorus doping and then crystallized by a 308 nm XeCl excimer laser. After the active region crystallization and thermal activation, a 100 nm thick SiO2 was deposited as gate insulator by PECVD. Next, Mo was grown by sputtering as the top gate metal. After the gate metal definition process, the source/drain regions were self-aligned by boron implantation to form the P+ regions at source/drain regions. Thermal activation of the dopant impurities after the source/drain region implantation was via the furnace annealing process. Next, 300 nm-Si3N4 and 300


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nm-SiO2 were deposited as the interlayer dielectric. Then, the contact holes were patterned by dry etching and Ti/Al/Ti metallization was performed. Finally, a 200 nm-thick Si3N4 was deposited using PECVD as passivation layer.

Electronic characterization. The electrical measurements were partially performed using Keysight B1500A and B1530A semiconductor parameter analyzer and Cascade M150 microprobe station. The reliability tests under different ambient environments (air, H2O, O2, high temperature) were accomplished with LakeShore CPS-VF cryogenic probe station. The test in high temperature is done in a vacuum environment of 1 × 10−3 torr atmosphere pressure controlled by a vacuum pump. The ambient pressure among H2O and O2 was the same as a standard atmospheric pressure, and the H2O and O2 was introduced into the chamber when the chamber is in vacuum (1 × 10−3 torr).

RESULTS AND DISCUSSION


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Low-temperature polysilicon (LTPS) thin film transistor (TFT) is a mature commercial device, it offers superior advantages in the unambiguous physical mechanisms, controllable electrical performances, CMOS compatibility, and excellent stability, comparing to other emerging synaptic transistors. Besides, LTPS TFT devices have already been massively integrated in electronic terminals such as flat-panel and flexible display.29,30 It brings benefits to the development of future mobile edge devices with neuromorphic computing functions. Figure 1a shows the schematic image of the doublegate LTPS synaptic transistor used in this work. The cross-section view reveals the viacontact structure of the device, which can ensure effective contact between the metal Mo source/drain and polysilicon layer in the via-hole through the Si3N4 etching stop layer. The bottom Mo gate layer is also extracted out from the via structure. The surface morphology of the device observed under the metallographic microscope is shown in Figure 1b. When the device works as a synapse, the top gate (TG) is regarded as the input terminal of presynaptic stimulus and the current flowing through source (S) and drain (D) which is read by a VDS = 0.1 V represents the postsynaptic current (PSC). During the operation, the base postsynaptic current is hold by a constant bottom gate voltage so that there are


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enough charges in the channel for trapping to generate synaptic response. Besides, bottom gate (BG) is a modulatory terminal involving in the realization of modulatable plasticity. The schematic diagram of the operation in the transistor array is shown in Figure S1. Figure 1c shows the output characteristics of the device for different top gate overdrive voltages after negative bias stress (NBS) of different time. When the stress time increases, the degradation of the output current is relatively small, which indicates good reliability of the device. In the output characteristic measurement, the top gate voltage varies from 0 V to -10 V with a step of -2 V. Figure 1d demonstrates the transfer characteristics of the top gate in five different devices. All measured transfer curves of these devices overlap together with a high uniformity, which proves the low device-todevice variation. Besides, high on/off ration (> 106) and low leaky current (< 1 pA) are also obtained. The inset of Figure 1d shows the transfer curves of the bottom gate, of which the control ability is slightly inferior due to the thicker gate insulating layer. To check the uniformity of the devices along the horizontal direction, the applied voltage of source and drain electrode was reversed to do the negative bias stress. In this condition, the time evolution of the transfer curves is shown in Figure 1e. As the stress time increases up to


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1500 s, the Vth still shows no shift and remains almost the same. Little sign of deterioration shown in the NBS test confirms in the reliability of the LTPS synaptic device, ensuring repeatable accurate synaptic weight modification during learning.31,32 Since some environmental effects may strongly influence the device characteristics,33 the stress characteristics in different environments (H2O, O2, high temperature) were also tested, as shown in Figure 1f. Compared between the initial and the stress results (Figure S2, Supporting Information), the existence of water and oxygen hardly influence the device behaviors, which means our device can function well in the moist and oxygen-rich atmosphere. Besides, when the temperature gets higher, the current of the OFF state gets larger and the Vth slightly shifts to the right direction. The inset shows the Vth at IDS = 10 nA, and the ΔVth is calculated to be 0.4 V, which is relatively small and won’t affect the device function. On the other hand, the tendency of device deterioration with increasing temperature is similar to the cell inactivating under high temperature in neuronal system. In short, the LTPS TFT devices are of superior performance with good stability and reliability which can be supported by the experimental results, and can also function well


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in various environment, facilitating the application as synaptic transistors in neuromorphic computing.

Next, the double sweep was carried out to characterize the transfer curves, as illustrated in Figure 2a. By sweeping the top gate voltage Vg in a range from -10 V to 7 V forward and backward, the transfer curve shows a hysteresis window in an anti-clockwise direction, no matter the scanning starts from -10 V or 7 V. It can be explained by the charge trapping in the SiO2 gate insulator (GI) layer.34–36 When the sweep starts at -10 V, the transfer curve shifts to the right as Vg sweeps backward from 7 V. It is the Vg in the positive voltage interval that drives the electron in the channel to move upward and be trapped in GI layer. The electron trapping process is shown in Figure 2b. When the voltage on top gate is in the positive range, the energy band of polysilicon is bent downward to the GI layer. The electrons are accumulated at the interface between GI layer and polysilicon, thus increasing the opportunity of being trapped in the GI layer.[32] The electron trapping in the GI layer results in a negative inner electric field which makes the Vth shift to right. On the contrary, when the sweep starts at 7 V, the shift of the curve


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is attributed to the hole trapping in the GI layer. As Figure 2c shows, when the top gate voltage is sweeping in the negative range, the holes are drove to move upward to the interface between the GI layer and polysilicon, and then be trapped by the traps in the GI layer. During the sweep, the bottom gate is floating. Based on this simple operation mechanism, the channel current can be enhanced or reduced under different gate bias polarities, thus both the excitatory and inhibitory synaptic functions can be realized and converted in a single LTPS device.

In biological system, a synapse is the connection part of two pre- and post-neurons. The connection strength, namely the synaptic weight, can strengthen or weaken in response to presynaptic stimuli which is also named synaptic plasticity.37 Specially, the short-term synaptic plasticity which is of great significance in decoding temporal information can be involved in neuronal tasks such as simple learning and sound source localization.38,39 Excitatory and inhibitory postsynaptic responses that guarantee the normal function of a synapse play a crucial role in neural system, and is important neurochemical foundations of learning and memory.40 In our work, short-term plasticity


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was demonstrated. EPSC and IPSC can be evoked in the LTPS synaptic transistor with a positive or negative pulse applied on either the bottom or the top gate electrode. For the purposes of discussion, the synaptic plasticity realized by applying stimuli to the top gate is shown below in the main body of this paper and the experimental synaptic plasticity based on operation on the bottom gate is shown in the supplementary information (Figure S4-S7).

As Figure 3a shows, when a positive presynaptic signal (5 V, 100 ms) was applied on the top gate, postsynaptic current emerged a sudden increase as the synaptic response and then gradually decayed to a stable state. The difference between the maximum and the initial value of the current (ΔI) can be regarded as the excitability of the synapse. Similarly, the inhibitory postsynaptic current can be triggered in the LTPS synaptic transistor by a negative presynaptic pulse. As Figure 3b shows, when the amplitude of the presynaptic pulse was negative (-5 V, 100 ms), the postsynaptic current decreased to a minimal value, and then gradually recovered to a stable state. In the same way, the strength of inhibition can be described as the difference between the minimal


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and the initial value (ΔI). The inset is the abridged general view of a two-terminal synapse which is constructed by pre- and post-neurons. Since the EPSC and IPSC can be simply realized with pure electrical presynaptic spike, the strength of both EPSC and IPSC can be adjusted gradually by varying the amplitude or width of the presynaptic spike. Figure 3c shows the graded ΔI responding to presynaptic pulses with different voltage amplitudes. When the absolute value of the presynaptic pulse amplitude increased to 10 V, the strength of both the EPSC and IPSC got stronger which indicated that stronger presynaptic stimulus lead to stronger postsynaptic response just like in neurobiology. By the same token, the EPSC and IPSC can be modulated by varying the width of the presynaptic pulse. Figure 3d shows the relationship between ΔI and the presynaptic pulse width. As expected, longer pulse duration generated larger EPSCs and IPSCs. The modulation of PSCs by presynaptic stimulus of different strength is similar to the biological synaptic behavior.

Apart from EPSC and IPSC, paired pulse facilitation (PPF) behavior can be realized in the LTPS synaptic device as well. As an essential form of short-term synaptic plasticity,


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PPF is of great significance in decoding temporal information in biological system. It is a biological phenomenon when a synapse receives two successive spikes, the peak of second postsynaptic current grows stronger than the first one.41,42 The PPF characteristics under two successive presynaptic positive pulses (5 V, 100 ms) with a time interval (Δt) of 0.4 s was shown in Figure 3e. The inset of Figure 3e shows the excitatory postsynaptic current in response to the presynaptic stimuli. Obviously, the second peak is higher than the first one. In the biological system, the PPF index defined by the ratio of the second peak A2 and the first one A1 of the postsynaptic current (PPF index = A2/A1) is the characterization of PPF property. As the interval time (Δt) of the two presynaptic pulse gets shorter, the PPF index gets larger. This is because the second pulse arrived before the effect of the first pulse faded, and biologically the greater release of neurotransmitter resulted by the accumulation of the presynaptic Ca2+ concentration in the synaptic cleft leads to stronger postsynaptic response.43 The relationship between PPF index and Δt can be described in a double exponential decay function:

F  1  C1e

(

t

1

)

 C2e

(

t

2

)

(1)


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Where Δt is the interval time, C1 and C2 are the initial facilitation magnitudes of the respective phases, and τ1 and τ2 are the relaxation time of the respective phase.43 The experiment results in Figure 3e fit well with the function. The fitted curve is shown in solid line. Likewise, the PPF effect under two successive presynaptic negative pulses (-5 V, 100 ms) is shown in Figure 3f, the inset shows the inhibitory postsynaptic currents generated by the presynaptic stimuli. During the operation of EPSC, IPSC and PPF described above, the bottom gate voltage keeps at -8 V.

The experimental results above discuss the modulation of synaptic plasticity by the top gate. Analogously, the bottom gate voltage can also regulate the synaptic plasticity based on the same mechanism, offering an extra degree of freedom to realize complex neuromorphic functions. As shown in Figure 4a, the baseline of the postsynaptic current can be modulated by bottom gate voltage. When 10 successive positive presynaptic pulses (5 V, 50 ms) were applied on the top gate of the device at a frequency of 20 Hz, the baseline of the postsynaptic current increased as the bottom gate voltage increased from -4 V to -8 V. As Figure 4b shows, the same law applies when applying negative


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pulses (-5 V, 50 ms) on the top gate. Modulation of PSC baseline by different bottom gate voltages increases the flexibility of the artificial synaptic device, for different PSC baseline can correspond to synapses with different activities.44 Moreover, the change rule of the postsynaptic current responding to the number of presynaptic pulse can be modulated by bottom gate voltage. Obviously, the peak of the postsynaptic current goes up visibly as the number of presynaptic pulse increases when the bottom gate voltage is -8 V and the PSC baseline is larger. But when the bottom gate voltage decreased to -4 V, the trend of increasing of the postsynaptic current with the pulse number becomes less obvious. It is because the base postsynaptic current of BG = -8 V is much larger than that of BG = -4 V, and higher charge density increases the opportunity of charge trapping. To explore the regulation rule of PSC by bottom gate voltage, the ΔI between the baseline and the 10th peak of postsynaptic current (ΔI @ t = 0 s) was calculated, and the statistical result is shown in Figure 4c. As the voltage of the bottom gate increased, the absolute value of Δ I for both EPSC and IPSC increased at the same time. This phenomenon corresponds to synaptic facilitation in biological system. The residual postsynaptic current after 10second decay (ΔI @ t = 10 s) was calculated to fit the same rule (Figure 4d). More


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remarkably, the Δ I @ t = 0 s of EPSC is obviously larger than that of IPSC when the bottom gate voltage is the same, but the residual current after 10-second decay of EPSC become smaller than that of IPSC. This interesting phenomenon can be explained by the different underline mechanism of EPSC and IPSC. The electron trapping in GI layer is more likely to occur than hole trapping because the energy barrier the electron trapping should overcome is lower than that of hole trapping as shown in Figure 2b and 2c. In the same way, the electron detrapping is more likely to happen than hole detrapping. In addition, ΔI @ t = 0 s is related to charge trapping and ΔI @ t = 10 s is influenced by charge detrapping. That is why ΔI @ t = 0 s of EPSC is larger but ΔI @ t = 10 s of EPSC is smaller than that of IPSCs.

In biological synapse, the stability problems of the synaptic plasticity must be taken into consideration in case that the synapse be over strengthened or weakened, destabilizing the activity of neuronal networks. Hence, a homeostatic mechanism is in urgent need to reconciles the opposite requirement of plasticity and stabilize the properties of neural circuits.27,28 Heterosynaptic plasticity, which need an extra


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modulatory terminal compared with the homosynaptic plasticity, can help regular the synaptic potentiation/depression between the pre and postsynaptic neurons to serve a homeostatic role.

27,28,44

Figure 5a shows a schematic diagram of a three-terminal

synapse with a modulatory terminal. When the synapse receives a stimulus from the presynaptic neuron, the postsynaptic current will increase or decrease as response, thus realizing the homosynaptic plasticity. The heterosynaptic plasticity can be implemented when the modulatory interneuron is involved in. In the double gate LTPS synaptic transistor, the bottom gate can essentially act as the modulatory terminal to realize the heterosynaptic plasticity.

As discussed in Figure 4, the extent of EPSC and IPSC can be modulated by BG bias. Here, a completed modulation result of EPSC and IPSC by BG voltage is shown. Figure 5b shows the modulation of EPSC by the bottom gate voltage bias. When a fixed presynaptic pulse (10 V, 100 ms) was applied on the top gate, a EPSC was triggered. As the BG voltage changed from -4 V to -8 V, the strength of EPSC (ΔI) changes accordingly. Similarly, The IPSCs can be modulated by BG voltage as well, as shown in Figure 5c, the


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postsynaptic current responding to the presynaptic pulse (-5 V, 100 ms) gets large when the BG voltage gets more negative. The modulation effects were calculated and plotted in Figure 5d. Visibly, the peak of postsynaptic current increases regularly as the absolute value of BG voltage increases no matter for the EPSC or IPSC. The experimental result indicates that homosynaptic plasticity realized in the LTPS synaptic transistor can be regulated by the modulatory terminal (BG), which means our double-gate devices are of great potential in achieving the synaptic homeostatic state.

Since the BG pulses can serve as the presynaptic signals and trigger EPSC and IPSC based on the same charge trapping mechanism as shown in Supporting Information, to further explore the effect of the modulatory pulse signals on homosynaptic plasticity, the top gate pulses were paired with the modulatory pulses in the BG electrode to imitate the regulating process of the homeostatic state. As Figure 5e shows, the TG pulse (-2 V, 100 ms) with a base voltage of -1 V alone triggered an inhibitory postsynaptic current, which is draw with the black line. When the modulatory BG pulses with different intensity (amplitude ranges from -10 V to 10 V and width fixed at 100 ms) were applied


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simultaneously with the fixed top gate pulses, the postsynaptic current changed accordingly. As the amplitude of BG pulse became more negative (from 0 V to -10 V), the IPSCs triggered by TG pulses became larger. Conversely, the initial IPSC triggered by the TG pulse will decrease if the amplitude of BG increases in the positive polarity (from 0 V to 10 V). When the BG voltage was 3 V, the IPSC decreased to near zero. It is worth noting that the transition from IPSC to EPSC occurred when the BG voltage increases up to 4 V. As expected, the peak of EPSC got higher when the amplitude of the BG pulse increased from 4 V to 10 V. Similarly, the BG pulse have a regulative effect on EPSC. When the TG pulse (0.5 V, 100 ms, base -1 V) was applied without collaboration of BG pulse, an EPSC of 3.57 nA was triggered. The EPSC evoked by this TG pulse increased up to near 5 nA as the amplitude of BG pulse increased from 0 V to 10 V. On the contrary, the EPSC decreased as the amplitude of BG increased in the negative polarity (from 0 V to -10 V). The transition from EPSC to IPSC occurred when the BG voltage was -7 V. The comprehensive investigation of interconversion between EPSC and IPSC by the BG voltage was shown in Figure 5f. Here we emphasize that the transition between two


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opposite homosyanptic plasticity, i.e. EPSC and IPSC, can provide high potential to meet the need to reconcile the opposite requirement of plasticity.

It is worth noting that, the synaptic plasticity realized in this work is short-term in a sense. The life time of charges trapped in the gate insulator layer has a direct connection with the retention properties of the synaptic plasticity. From this perspective, long-term plasticity can be obtained by stronger presynaptic stimuli with higher amplitude or larger width. Besides, floating gate transistors and ferroelectric field effect transistors can be utilized to obtain more stable non-volatile weight modulation behaviors46-48, taking the advantage of their working mechanism, thus enriching the synaptic devices for hardware neuromorphic computing.

CONCLUSION

In conclusion, an artificial synaptic device base on low-temperature polysilicon thin film transistor has been demonstrated in this paper. High compatibility with traditional


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CMOS circuits vests the LTPS TFT devices with high potential for mass production of synaptic array. The synaptic transistors show high stability and reliability, for the transfer curves of the device under negative bias stress among different ambient (H2O, O2, air and high temperature) exhibited negligible harmful degradation. Basically, essential synaptic functions including both the excitatory and inhibitory plasticity have been successfully mimicked utilizing the mechanism of charge trapping. Most importantly, the dynamic modulation of synaptic plasticity was realized in the LTPS synaptic device by taking advantage of the bottom gate bias effects. Realization of the heterosynaptic plasticity and easy manipulation of the transition between excitatory and inhibitory functions provides a promising way to achieve the homeostatic regulation of the synaptic weights. The results in our work further promote the application prospect of mature TFT technology in the emerging neuromorphic computing field.

AUTHOR INFORMATION

Corresponding Author


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* E-mail: [email protected], [email protected], [email protected]

Author Contributions N. D., Y. L. X.-S. M. and T.-C. C. conceived the idea and analyzed the data. H.-C. C. and S.-P. H. fabricated the film and device samples. N. D. carried out the material characterization and contributed to the electrical characteristics measurements and analysis. K.-S. Y., J. C. and C.-I. Y. contributed to the analysis of electrical characteristics. The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript.

Notes The authors declare no competing financial interest.

ASSOCIATED CONTENT

Supporting Information

Schematic diagram of the operation in the LTPS transistor array (Figure S1); time evolution of transfer curves under negative bias stress (Figure S2); EPSC and IPSC


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triggered by pulses on top gate without the bottom gate voltage (Figure S3); realization of excitatory and inhibitory synaptic behavior under bottom gate pulses (Figure S4); PPF property realized by the bottom gate (Figure S5); excitatory and inhibitory postsynaptic currents under 10 positive and negative bottom gate pulses with different top gate (Figure S6); interconversion between EPSC and IPSC when the BG voltage is fixed (Figure S7).

ACKNOWLEDGMENT This work was ﬁnancially supported by the National Key Research and Development Plan of MOST of China (2016YFA0203800), National Natural Science Foundation of China (61504045, 51732003, 61674061, 61841404).

REFERENCES (1) Jeong, D. S.; Hwang, C. S. Nonvolatile Memory Materials for Neuromorphic Intelligent Machines. Adv. Mater. 2018, 28 (42), 1704729.


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Figure 1. Device structure and electrical properties of the p-type LTPS TFTs. (a) The schematic cross sectional via-contact structure of the LTPS TFT. (b) Top view image of the LTPS TFT device under a metallographic microscope. Figure in the red dotted frame enlarged the device. (c) Output characteristics (IDS-VDS curves) of the device after negative bias stress (NBS) of different time. The gate voltage sweeps in a range of 0 to 10 V with a step of -2 V. (d) The uniform transfer curves of the top gate and bottom gate (inset) measured in five different devices. e) Transfer curves under a constant negative bias stress (NBS) with stressing time ranged from 0 to 1500 s. f) Transfer curves


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measured among different atmospheres. The inset shows that the Vth (IDS = 10 nA) shifts to the right direction when the temperature gets higher, and the ΔVth is 0.4 V.


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Figure 2. Electron and hole trapping in the LTPS TFT. (a) Double DC sweep with a gate voltage range of -10 V to 7 V. The black line starts at -10 V while the red one starts at 7 V. The schematic diagram of (b) electron trapping and (c) hole trapping occurred in the LTPS synaptic transistor.


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Figure 3. Excitatory and inhibitory synaptic behavior under different presynaptic stimulus. (a) The excitatory postsynaptic current (EPSC) and (b) the inhibitory postsynaptic current (IPSC) triggered by presynaptic positive (5 V, 100 ms) and negative (-5 V, 100 ms) electric


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pulses on top gate, respectively. The maximum postsynaptic current change ΔI represents the synaptic weight change. The ΔI can be modulated by changing the parameters of the presynaptic inputs. (c) ΔI as a function of the presynaptic pulse amplitude. (d) ΔI as a function of the presynaptic pulse width. The ΔI increases as the spike amplitude or width increases. (e) and (f) shows the PPF index (A2/A1) plotted as a function of presynaptic spike interval time Δt. The inset show the EPSCs and IPSCs triggered by two pairs of presynaptic spikes of (5 V, 100 ms) and (-5 V, 100 ms) with a time interval (Δt) of 400 ms. A1 and A2 represent the amplitude of the first and second PSC, respectively.


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Figure 4. (a) Excitatory and (b) inhibitory postsynaptic currents under 10 continuous presynaptic pulses with different bottom gate (BG) voltages (-4 V, -6 V, -8 V). As the BG voltage becomes larger, the baseline of the synaptic current accordingly enhances. (c) The maximum postsynaptic current change ΔI occurs at the time the pulse sequence finish (t=0) and is approximately linear to the BG voltage. (d) The remained ΔIs after 10 seconds the pulse sequence finished as a function of the BG voltage.


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Figure 5. Heterosynaptic plasticity realized in the LTPS synaptic transistor. (a) Schematic diagram of a double input synapse, including inputs from a presynaptic neuron and a modulatory interneuron. (b) Normalized EPSCs and (c) IPSCs under different BG voltages. The current change ΔI increases with larger BG gate voltage. (d) The relationship between ΔI and the TG voltage under different BG voltage. (e) Interconversion between EPSC and IPSC when the TG voltage fixed and the BG voltage


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ranged from -10 V to 10 V with a step of 1 V. The width of BG pulse is 100 ms. (f) Manipulation of the transition between EPSC and IPSC by controlling the BG biases.


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Table of Contents Graphic


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Gate Modulation of Excitatory and Inhibitory Synaptic Plasticity in a

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