Gate Modulation of Threshold Voltage Instability in Multilayer InSe

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Gate modulation of threshold voltage instability in multilayer InSe field effect transistors Wei Feng, Wei Zheng, Xiaoshuang Chen, Guangbo Liu, and PingAn Hu ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.5b08635 • Publication Date (Web): 17 Nov 2015 Downloaded from http://pubs.acs.org on November 24, 2015

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ACS Applied Materials & Interfaces

Gate Modulation of Threshold Voltage Instability in Multilayer InSe Field Effect Transistors Wei Feng, †, ‡ Wei Zheng, †, ‡ XiaoShuang Chen, † Guangbo Liu, † PingAn Hu*,†

†

Academy of Fundamental and Interdisciplinary Science, ‡ School of Materials Science and

Engineering, Harbin Institute of Technology, Harbin, 150080, China KEYWORDS: indium selenide, multilayer, field-effect transistors, threshold voltage instability.

ABSTRACT: We report a modulation of threshold voltage instability of back-gated multilayer InSe FETs by gate bias stress. The performance stability of multilayer InSe FETs is affected by gate bias polar, gate bias stress time and gate bias sweep rate under ambient conditions. The oncurrent increases and threshold voltage shifts to negative gate bias stress direction with negative bias stress applied, which are opposite with that of positive bias stress. The intensity of gate bias stress effect is influenced by applied gate bias time and the sweep rate of gate bias stress. The behavior can be explained by the surface charge trapping model due to the adsorbing/desorbing oxygen and/or water molecules on InSe surface. This study offers an opportunity to understand gate bias stress modulation of performance instability of back-gated multilayer InSe FETs and provides a clue for designing desirable InSe nano-electronic and optoelectronic devices.

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Introduction Two-dimensional (2D) layered semiconductor materials have attracted substantial attention because of their unique electronic and optoelectronic properties and potential application in next generation electronic nano-devices. Compared to graphene with zero band-gap structure, 2D layered semiconductors own suitable band-gap, which provides high current on/off ratio for field effect transistors (FETs). Recently, a wide of efforts have been made on 2D transition metal dichalcogenides (TMDS, such as MoS2,16 WSe27-10) and black phosphorus11-13 for FETs and optoelectronic devices. However, another group layered materials, III-VI layered semiconductors (such as GaSe,14,

15

, GaS14,

16

and InSe17-19) have been relatively limited. Bulk InSe is an

important layered semiconductor with direct band-gap of 1.26 eV, which makes it applications in infrared photodetectors. InSe possesses lighter electron effective mass (m* = 0.143 m0)20 and shows a high mobility of 103 cm2V-1s-1,21 indicating its great potential application in high mobility electronic devices. However, there are only few reports on multilayer InSe FETs 22 and optoelectronic devices

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to date. As a typical layered semiconductor, bulk InSe is vertically

stacked by Se-In-In-Se layer with relatively weak van der Waals interactions, leading to successful fabrication of 2D InSe nanosheets by micromechanical exfoliation of bulk InSe.17 Recently, photodetectors based on multilayer InSe have been demonstrated, and show a high performance of photoresponsivity and detectivity.19 Multilayer InSe FETs display a high mobility of 1055 cm2V-1s-1 using dielectric engineering, making it a potential material for next generation electronic nano-devices.22 For practical applications, it is of significance to investigate the stability of multilayer InSe FETs. Gate bias stress induced instability of low-dimensional semiconductors FETs under ambient conditions has been demonstrated.23-26 FETs based on multilayer MoS2,23 ZnO


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nanowires,24 InGaZnO thin films25 and bilayer graphene26 exhibit performance instability under ambient conditions, which can be explained by charge trapping model because of adsorbing oxygen and water molecules at their surface defect sites. In the case of amorphous Si, the performance instability is attributed to dangling band states creation and interface charge trapping between gate dielectric layer and channels.27 Due to the limited reports on multilayer InSe-based FETs22, the performance stability under gate bias stress has not been investigated. It is highly important to explore the gate bias stress induced instability of InSe-based FETs for designing desirable InSe nano-electronic devices. In this letter, we perform a system study on gate-stress-modulation threshold voltage instability of multilayer InSe back-gated FETs. We study gate bias stress effects of multilayer InSe FETs in ambient and in vacuum condition, respectively. The performance of multilayer InSe FETs is sensitive to gate bias polar (positive and negative bias), bias stress time, gate bias sweep rate and sweep range under ambient conditions. The on-current and threshold voltage of multilayer InSe FETs vary with applied gate bias. Applying negative bias stress, the current increases and threshold voltage shifts to negative gate bias stress direction, which are opposite with applied positive bias stress. Under vacuum environment, the performance of multilayer InSe FETs is insensitive to gate bias.

Results and discussion The synthesis process and structure characterization of bulk InSe are described in our early report.22 The InSe nanosheets are obtained from bulk InSe by micro-mechanical exfoliation and transferred to p++Si substrate coating 300 nm SiO2. We locate a target multilayer InSe nanosheet using optical microscope. The thicknesses of multilayer InSe are briefly identified by optical


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microscope with color contrast on 300 nm SiO2/Si substrate and precisely confirmed by atomic force microscope (AFM). We fabricate back-gated multilayer InSe FETs using copper meshes as shadow mask, and Au/Cr (30 nm/10 nm) are deposited by thermal evaporation as source and drain electrodes (in Figure S1). The 3D schematic of InSe FET is shown in Figure 1a upper part. A typical optical image and corresponding AFM image of multilayer InSe FETs are shown in Figure 1a lower part, and the channel thickness is 32 nm. A typical transfer curve measured under ambient environment at fixed source-drain voltage (Vds = 1 V) is shown in Figure 1b, and the inset are the corresponding output characteristics. The multilayer InSe FET shows an obvious n-type conduction behavior due to the current increase with applied gate bias rise. The mobility of InSe FETs can be extracted using the following equation, µ = [L/(WCiVds)]×[dIds/dVg], where L is the channel length of 15 µm, W is the channel width of 10 µm, Ci = ε0εr/d, ε0 = 8.854×10-12 Fm-1 is the vacuum permittivity, εr is 3.9 for SiO2 and d is 300 nm for the thickness of SiO2. The mobility of our transistor is calculated to be 79.5 cm2V-1s-1 under ambient environment (Figure 1b, Vds= 1 V), which is consistent with our early report.22 The Ids-Vds curves display a current linear regime under low Vds and a saturation regime under high Vds, which agrees with the conventional long-channel NMOS transistor (Figure S2). This trait is an important factor for practical applications. The saturation of drain current shown in multilayer InSe FETs can be attributed to the conducting channel of multilayer InSe converting to “pinch-off” condition at high Vds. The contact resistance of Cr-InSe for InSe FETs is roughly calculate to be 1.1×104 Ω µm-1 by the linear region of Ids-Vds curves (Figure S2).


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Figure 1. (a) The upper part is schematic of back-gate multilayer InSe FETs; The lower left is a typical optical image of multilayer InSe FETs with a length of 15 µm and width of 10 µm); the lower right is corresponding atomic force microscopy image of multilayer InSe FETs and inset is corresponding height profile of 32 nm. (b) Transfer characteristics for multilayer InSe FETs; Measurements were performed under ambient environment. We investigate gate bias stress induced threshold voltage instability properties of multilayer InSe FETs. To study the electronic stability properties of multilayer InSe FETs modulated by gate bias stress, we first investigate the effect of gate bias stress polar and duration time. We apply a constant gate bias stress (40 V and -40 V) for 300 s and record the transfer curves for 10 times consecutively. The transfer curves are shown in Figure 2a (-40 V for 300 s, gate bias sweeping from -40 to 40 V) and 2b (40 V for 300 s, gate bias sweeping from 40 to -40 V). As shown in Figure 2a, after applying a gate bias stress of -40 V for 300 s, the current significantly increases and the threshold voltage shifts to negative gate bias stress direction. Then, the current gradually decreases and the threshold voltage shifts into positive gate bias direction, and the curve is back to original state at the tenth measurement. For applying 40 V gate bias stress conditions, opposite to negative gate bias stress, the current significantly decreases and the threshold voltage shifts toward positive gate bias stress direction, then the current gradually increases associated with the threshold voltage shifting to negative gate bias stress direction, and eventually, the curve returns to the original curve (0 s) at the tenth measurement. The transfer curves of gate bias sweeping from -40 to 40 V and from 40 to -40 V are totally different due to


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the hysteresis effect. The subthreshold swing (SS) value are 2.75 V/decade and 3.6 V/decade for transfer curves of sweeping from -40 to 40 V under applying a gate bias stress of -40 V for 300 s and from 40 to -40 V under applying a gate bias stress of -40 V for 300 s, respectively. Figure 2c shows the shift of the threshold voltage for each measurement compared to the value for the prestress curves (0 s). From Figure 2c, we can directly learn the threshold voltage shift for each measurement.

Figure 2. The transfer characteristic curves measured before the gate bias voltage and 10 continuous measured after (a) -40 V (gate bias sweeping from -40 to 40 V) and (b) +40 V (gate bias sweeping from 40 to -40 V) gate bias voltages was applied for 300 s in ambient environment. (c) The shift of the threshold voltage for each measurement compared to the value for the initial measured (pre-stress curves). Transfer curves operated in ambient environment


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after (d) -40 V(gate bias sweeping from -40 to 40 V) and (e) +40 V (gate bias sweeping from 40 to -40 V) gate bias voltages was applied for various times. (f) The shift of the threshold voltage for various gate bias stress duration time compared to the value for the initial measured (0 s). Then, we apply a constant gate bias (-40 V and 40 V) on InSe FET with various duration times from 0 s to 300 s at a fixed gate bias sweep rate of 5 V/s and measure the transfer curves. Each measurement must be separated by 15 minutes for the FETs returning back to original state (details shown in Figure S3). Figure 2d shows the transfer curves of multilayer InSe FET measured after applying -40 V gate bias for various gate bias duration times with gate bias sweep range from -40 V to 40 V. The current gradually rises and the threshold voltage shifts to negative gate bias direction with the gate bias duration times increase. The mobility and current on/off ratio also increase with the gate bias duration time increasing (Figure S4a). The transfer curves of multilayer InSe FET measured after applying 40 V gate bias for various gate bias duration times with gate bias sweep range from 40 V to -40 V are shown in Figure 2e. The current significantly decreases, the threshold voltage shifts to positive gate bias direction with the gate bias duration time increasing, which is opposite to behaviors of applying -40 V gate bias. The mobility and current on/off ratio decrease with the gate bias duration time increasing (Figure S4b). The threshold voltage shift compared to value of initial measurement (0 s) of each measurement as a function of gate bias stress duration time is shown in Figure 2f. The threshold voltage shift increases with the gate bias stress duration time increasing for both the positive and the negative gate biases. Such phenomena can be explained using charge trapping model. The defect states in InSe surface adsorbing oxygen and/or water molecules under ambient conditions lead to change the electronic properties of InSe channel, and charge trapping condition can be modulated by applied gate bias stress on InSe channel. Adsorbing oxygen and /or water molecules on the InSe surface


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can escape from the defect states under applying negative gate bias stress, leading to electrons release from the trapping states as shown in Figure 3b, which results in an increasing conductance and the threshold voltage shifting to negative gate bias direction. Opposite to applying negative gate bias stress, the adsorbing oxygen and /or water on the InSe surface can be enhanced by applying positive gate bias stress because of more electrons can aggregate on surface under applying positive gate bias stress on InSe channel as shown in Figure 3a. The charge trapping reduces the effective electrons concentration and results in a decreasing conductance and the threshold voltage shifting to positive gate bias direction. Similar behaviors have been discovered in various FETs based on multilayerMoS2,23 bilayer graphene,26 ZnO nanowires24 and InGaZnO films25. It is worth noticing that the threshold voltage shift reaches a saturation state as the gate bias is applied for enough time, because of the adsorbed oxygen and/or water molecules on InSe surface are saturated.

Figure 3. Schematics of gate bias modulated (a) adsorption of oxygen and water molecules from the ambient atmosphere under positive Vg and (b) desorption of oxygen and water molecules from the ambient atmosphere under negative Vg. We also study the modulation effect of gate bias sweep rate on threshold voltage instability properties of InSe FETs. The transfer curves measured under ambient environment with various gate bias sweep rates at a fixed gate bias sweep direction from -40 V to 40 V is shown in Figure 4a. From the transfer curves, we can learn that the current decreases threshold voltage shifts toward positive gate bias direction with the gate sweep rate decreasing. And the mobility and


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current on/off ratio decrease with the gate bias sweeping rate decreasing (Figure S4c). The value of the threshold voltage for different gate bias sweep rates is clearly shown in Figure 4b. This behavior can be attributed to the slower sweep rate leading to a longer positive gate bias stress duration time. Similar behaviors can also be observed in the opposite gate bias sweep direction (from 40 V to -40 V) with the same sweep rates, which are presented in Figure 4c and Figure 4d. As shown in Figure 4c and Figure 4d, the current decreases and the threshold voltage shifts to positive gate bias direction. These results are well agreement with Figure 2. And the mobility and current on/off ratio decrease with the gate bias sweeping rate decreasing (Figure S4d).

Figure 4. (a, c) The transfer curves measured in ambient environment for various gate bias sweep rates from 10 to 0.5 V/s. From -40 V to 40 V for (a) and from 40 V to -40 V for (c). (b, d) Threshold voltage of various sweep rates for gate sweeping from -40 V to 40 V for (b) and from 40 V to -40 V for (d). In order to confirm the ambient environment effect, we measure the transfer characteristics with various gate bias stress in vacuum conditions. The transfer curves measured in vacuum with


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various gate bias sweep rates at a fixed gate bias sweep direction from -40 V to 40 V are shown in Figure 5a, and transfer curves measured in vacuum after -40 V gate bias voltage applied for various duration times are displayed in Figure 5b (the other measurements are exhibit in Figure S5). The mobility is 92.2 cm2V-1s-1 in vacuum environment, which is slight higher than of 79.5 cm2V-1s-1 in ambient environment. Compared with ambient conditions, no significant gate bias stress effects are shown in vacuum conditions (details shown in Figure 6S), the mobility and current on/off ratio also show weak variation (Figure S4e). Slight variations are observed in vacuum, which are attributed to the trap states at the interface between InSe channel and SiO2 dielectric layer. The gate bias stress effect

can be induced by two

elements,

adsorption/desorption of oxygen and water molecules on the channel surface and the trap states at the interface between channel and SiO2 dielectric layer. In our experiment, the former element plays a dominant role in inducing the gate bias stress effect.

Figure 5. (a) The transfer curves measured in vacuum for various gate bias sweep rates from 10 to 0.5 V/s with the gate bias sweep from -40 to 40 V. (b) Transfer curves measured in vacuum after -40 V gate bias voltage was applied for various voltage continued times.

Conclusion


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In summary, we have performed a comprehensive study on instability performance of back-gated multilayer InSe FETs induced by gate bias stress. The performance of multilayer InSe FETs can be influenced by gate bias polar, bias stress time, gate bias sweep rate and sweep range under ambient conditions. By applying negative bias stress, the on-current increase and threshold voltage shift to negative gate bias stress direction, which are opposite with applying positive bias stress. The intensity of gate bias stress effects is affected by applied gate bias time and the sweep rate of gate bias stress. The phenomenon can be attributed to the surface charge trapping because of the adsorbing/desorbing oxygen and/or water molecules on InSe surface. Our study offers the opportunity to understand gate bias stress induced performance instability of back-gated multilayer InSe FETs and provides the clue for designing desirable InSe nano-electronic and optoelectronic devices.

Experimental The multilayer InSe nanosheets were mechanically peeled from bulk InSe crystals and transferred onto the silicon substrate which coated 300 nm SiO2. Metals electrodes (Cr = 10 nm, Au = 30 nm) were fabricated using a shadow mask by thermal evaporation. The thickness of InSe thin film was determined by atomic force microscopy (AFM, Nanoscope IIIa Vecco). Electrical characterizations of transistors based on multilayer InSe were performed by using a semiconductor characterization system (Keithley 4200 SCS) with a Lakeshore probe station. ASSOCIATED CONTENT Supporting Information. Transfer characteristics with various gate bias stress, speeds and time in vacuum conditions. This material is available free of charge via the Internet at http://pubs.acs.org.


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AUTHOR INFORMATION Corresponding Author *Email: [email protected] Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Notes The authors declare no any competing financial interest. ACKNOWLEDGMENT This work is supported by National Natural Science Foundation of China (NSFC, No.61172001, 21373068), the National key Basic Research Program of China (973 Program) under Grant No. 2013CB632900.

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Gate Modulation of Threshold Voltage Instability in Multilayer InSe

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