General Purpose System for Computer Data Acquisition and Control Louis Ramaley and George S. Wilson Department of Chemistry, Unioersity of Arizona, Tucson, Ariz. 85721
A general purpose system for data acquisition and control was constructed using an eight-channel multiplexer and a 12-bit analog-to-digital converter as the input system. Sample-and-hold amplifiers are associated with two input channels to take X-Y data with no time skew. The output section contains two digitalto-analog converters for display of analog data or control and a 12-bit register for digital data. The system may be controlled either by computer or manually. Data rates of 30 kHz on a single channel or 10 kHz per X-Y pair are easily achieved with less than one bit of noise. The system is designed to be used with a 16-bit word computer and can be programmed by operators inexperienced in electronic design. THEINCREASING AVAILABILITY of small computers has made digital data acquisition and control of experiments more attractive. The advantages of increased speed and accuracy of data acquisition and the compatibility of data thus obtained with large computer data processing have been already demonstrated (1-5). In order to achieve greater speed and convenience, small computers have been used in conjunction with digital data acquisition systems to oversee data collection and perform calculations (6-10). Frazer has presented a review on the general use of small computers in the laboratory (11). In addition to this general review, others have presented discussions of terminology and practice in the design and use of digital systems ( 4 , 9). The use of the small computer for routine analysis problems will no doubt be common in the near future. More recently (12, 13) the importance of control has been emphasized, In a nonroutine experiment, or where parameter optimization is desired, the computer must be capable of acquiring data, examining it, and then exerting control on the experiment itself. This requires two-way communication between computer and peripheral experimental equipment. Some systems are commercially available--e.g., Varian Aerograph for gas-liquid chromatographs and Picker Nuclear for X-ray diffractometers-which utilize a computer for data acquisition and control of a specific instrument. All the necessary hardware and software are usually provided with these systems. For applications either outside the range of (1) M. W. Breiter, J . Electrochem. SOC.,112, 845 (1965).
(~, 2 ) E. R. Brown, D. E. Smith, and D. D. DeFord, ANAL.CHEM., 38, 1119 (1966). (3) G. Lauer and R. A. Osteryoung, ibid., 38, 1137 (1966). (4) G. L. Booman, ibid., p 1141. (5) J. E. Oberholtzer and L. B. Rogers, ibid., 41, 1234 (1969). (6) G. Lauer, R. Abel, and F. C. Anson, ibid., 39, 765 (1967). (7) H. R. Felton, H. A. Hancock, and J. L. Knupp, Jr., Instrum. Control Systems, 40(8), 83 (1967).
(8) S . P. Perone, J. E. Harrar, F. B. Stephens, and R. E. Anderson, ANAL.CHEM., 40, 899 (1968). (9) G. Lauer and R. A. Osteryoung, ibid., 40(10), 30A (1968). (10) D. M. Hannon, D. E. Horne, and K. L. Foster, I B M J . Res. Develop., 13, 79 (1969). (11) J. W. Frazer, ANAL.CHEM., 40(8), 26A (1968). (12) S . P. Perone, D. 0. Jones, and W. F. Gutknecht, ibid., 41, 1154 (1969). (13) G. E. James and H. L. Pardue, ibid., p 1618. 606
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these systems or where complete systems are unavailable the experimentalist may have certain firms-e.g., Raytheon Computer-custom-build a computer interface as long as the exact and complete specifications and descriptions of the system are provided. It would be extremely valuable to have a general purpose data acquisition and control system which could be used without special effort for a variety of experiments. In such fields as electrochemistry, fast reaction kinetics, and spectroscopy, a medium speed (1 to 10,000 Hz), medium accuracy (0.05 to 0.1 %)conversion system is required. Lauer and Osteryoung (9) have recently described a general purpose data acquisition system. The system described here in some detail is different in several respects from those previously described. It is capable of accepting several analog signals for aigital conversion in simultaneous, sequential, or random fashion. Communication between the computer and the experiment is achieved using both digital and analog signals. This makes possible discrete control (switching operations) or continuous control by a programmed analog output. In addition, a special effort was made to devise the interface hardware so that the development of software would be simplified. The system is easy for a programmer to understand with little or no electronic background. DESCRIPTION OF SYSTEM
A complete diagram of the data acquisition system is shown in Figure 1. The analog-to-digital converter (ADC) is a 12bit, successive approximation type with a conversion time of 18 psec. The output coding is inverted offset binary. The converter consists of a Raytheon MDA5 digital-to-analog converter and comparator, MDS6 data storage resister, and MSC6 sequencer. This assembly has a range of + l o V, a linearity of 0.025 % FS, and an accuracy of 0.025 + 5 mV. Eight analog input channels are available for selection by the multiplexer (MUX), a Raytheon MAMI. The multiplexer can either be sequenced through a selected number of channels or randomly addressed. This function is provided by the multiplexer sequencer, a Raytheon MSC8. The converter sample-and-hold amplifier (ADC S & H) holds the analog input signal during conversion to avoid the uncertain result that would ensue if the analog signal were to vary during the conversion time, This amplifier, a Raytheon MSH2, has an accuracy of 0.01 % and a settling time of 2 psec. Often two related analog signals, which might represent voltage and current, amplitude and phase, or wavelength and intensity, vary in some manner with time. To avoid time skew, the two signals should be sampled and held simultaneously, followed by sequential encoding. To provide this capability, two Raytheon MSH2 sample-and-hold amplifiers are placed on the channel 0 and 1 inputs of the multiplexer. Total system conversion time is slightly greater than 20 psec per point. The output of information from the computer is handled through three individually addressable 12-bit storage registers, Raytheon MDS8. Two of these registers are connected to 12-bit digital-to-analog converters (DAC), Raytheon
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The data acquisition system is interfaced to the computer through a Hewlett-Packard 021 16-6195 general purpose register (GPR) card. This card contains separate 16-bit input and output registers for numerical data. In addition, service requests or device status information enter the computer through a one-bit “flag” flip-flop register and commands to initiate events external to the computer leave through a one-bit “encode” flip-flop register. These registers can be set or cleared by software command. Any external signal which sets the flag flip-flop simultaneously enters the external data into the 16-bit register of the GPR card and clears the encode flip-flop so that another output command can immediately be sent. A set flag may immediately interrupt the program currently being run if the priority interrupt system is being used (this is enabled or disabled by software command). If the interrupt system is not being used, the flag status is checked through software “skip” instructions. The GPR interface card has logic levels “true” = 0 V, “false” = +10 V, the data acquisition system which is DTL (diode-transistor logic) compatible and uses NAND logic, has “true” = + 5 V, “false” = 0 V. The necessary level shifting was accomplished with Raytheon MLC3 level shifters on bits entering the computer and MLC4 level shifters on bits leaving the computer. Gates 1 and 2 are used to interconvert between the offset binary coding of the data acquisition system and the 2’s compliment coding of the computer. Part of the design of this system was influenced by the peculiarities of the Hewlett-Packard computer. However, the principles are general and only slight modifications are necessary to adapt the system to other computers.
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The computer word format used with the data acquisition system is shown in Figure 3. Bits zero through 10 of the input word transmit the magnitude of the data from the ADC and bit eleven transmits the sign. Bit twelve is used to indicate the channel (0 or 1) of data taken into the computer in the sequential mode described below. This allows a check to determine whether sequencing is proceeding properly. Bits 13 to 15 may be used for additional digital information. The first 12 bits of the output word contain the digital information for control or presentation of data to a readout device. If the data are to be converted to an analog signal, the first eleven bits are the magnitude and the twelfth bit the sign. Bits 12 to 14 are address bits which determine the input channel to be converted or the output buffer to receive data. Bit 15 determines whether an input or output operation is to be performed. The number of IjO channels in the system is limited to eight by the output word format since only three binary bits are used as address information. Therefore, the number of input channels in the system as described cannot be expanded. However, five more 12-bit output registers may be added, with or without associated digital-to-analog converters. Encode commands are converted to pulse form by a monostable multivibrator (MONO 3) and routed either to the input or output section through G3 to G7, depending on the value of bit 15. Flag or clock signals enter the computer via G39 to G42. The outputs of these gates are “OR wired” so that a “true” signal at any of the inputs will cause a “false” signal at the combined output. This configuration is not allowed with every type of integrated circuit logic. The input section can be operated in two separate modes, sequential or random. Timing diagrams for these modes are shown in Figure 4. In the sequential mode, the multiplexer sequences automaticaIly between channel 0 and 1 (X and Y
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feature is necessary to prevent clock pulses from being interpreted as flag pulses by the computer when performing operations not involving the clock-e.g., outputting data to an X-Y plotter. In the sequential mode a clock pulse sets the computer flag through G40 and simultaneously sets the X and Y , S & H amplifiers to hold by setting the R-S flip-flop (G29 and G30) through G27. The computer then provides an encode command to convert the X channel signal. This command sets the ADC S & H amplifier to hold through G20. When conversion is complete, the ADC busy signal activates a monostable multivibrator (MONO 1) and sequences the multiplexer to the Y channel. MONO 1 provides a flag to the computer through G39, activates MONO 2, and sets the ADC S & H amplifier to sample. MONO 2 is disabled by G23 when the multiplexer is set to the Y channel. The computer provides a second encode command to convert the Y channel signal. On completion the busy signal again activates MONO 1 and sequences the multiplexer back to channel x . MONO 1 sends a flag to the computer, activates MONO 2, and sets the ADC S & H amplifier to sample. The output of MONO 2 is now passed through G23, G24 and G28 to reset the R-S flip-flop which sets the X and Y , S & H amplifiers to sample again. Gates 32 and 33 and inverters G34 and G35 are used only to provide the drive capability necessary to operate the capacitively coupled X and Y , S & H controls. The fast settling time of the ADC S & H amplifier makes software delays unnecessary between conversion of the X and Y data points. Data are entered into the GPR card input register by the positive going edge of the flag signal. The software must provide for X datum transfer from the GPR card to a register or core memory before completion of Y 610
ANALYTICAL CHEMISTRY, VOL. 42, NO. 6, MAY 1970
conversion to avoid Y overlay of X datum. MONO 1 and MONO 2 provide the necessary delays to allow information to settle on the lines before operations are performed in the system. The next clock pulse starts the operation all over again. With this hardware arrangement, no changes in the software are necessary when the data input rate is varied. Operation in the random mode is quite similar. A channel address must be presented to the sequencer, either by the computer or through the S3-S5 switch register. If either channel X or Y is chosen, the clock pulse sends a flag to the computer and sets both the X and Y , S & H amplifiers and the ADC S & H amplifier to hold through G27 and G19, respectively. Conversion proceeds as before except that the ADC busy signal resets the R-S flip-flop through MONO 2 and G25. If a channel other than X or Y is addressed, the X and Y , S & H amplifiers are locked permanently in the sample mode. In the random mode, the computer’s internal clock may be used for timing. The sample and holds are then set to hold by the encode command through G20 and reset as before with the busy signal. If the output system is to be used, a “0” must be placed in bit 15 of the GPR card output register. In addition the address of the output channel is placed in bits 12 to 14 and the digital information in bits 0 to 11. The encode command in combination with the address signals through G46 and G47 strobes information into the proper register. Digital control information is output to the 12-bit Z register. Analog control signals may be output through either of the DAC‘s. These also may be used to drive readout devices such as oscilloscopes or X-Y plotters. Any oscilloscope with X-Y plotting capability may be connected directly to the two DAC‘s and the information output as rapidly as possible by the computer without waiting for a returned flag. The time required by the outputting operation allows sufficient settling time for the DAC’s and satisfactory oscilloscope traces are obtained. This simple display method has the disadvantage of plotting each Y point with its own X point and the following X point. If desired, a blanking pulse to the oscilloscope CRT could be supplied during the time an incorrect point is output. Provision has been made to allow outputting of data to an X-Y plotter. The plotter used was a Hewlett-Packard 7001A driven by a Hewlett-Packard G2B detector. On receiving a plot-seek signal, the null detector unlocks the recorder servos and allows the new balance point to be reached. A point is then plotted, the servos locked, and a completed-plot signal sent out. The plot-seek pulse is provided by an encode command. Gates 43, 44, 45, and 47 ensure that a plot-seek signal is provided only after a Y datum point is output, avoiding the problem mentioned above with the oscilloscope. The completed plot signal, which is not DTL compatible, returns to the computer through the necessary level shifting as a flag signal on the Flag 1 channel. The Flag 2 channel is provided as a general flag input from external DTL compatible devices. MONO 4, 5 and 6 transform the input level changes to the necessary pulse of correct duration. All gates shown in Figure 1 are Motorola MC846P DTL integrated circuits except G34 and G35 which are 2N3638 transistors wired as inverters. MONO 1-3 are Raytheon MOSl discrete component monostable multivibrators. MONO 4-6 are Motorola MC851P DTL integrated circuits. Visual display of digital data was accomplished with 5-V incandescent lamps driven directly with Motorola MC844P power gates. The lamps functioned as the collector pull-up resisters for the gates. The digital information was taken
directly from the system side of the level shifters, Inverters must be inserted between the level shifters and the power gates to give proper output display. The clocked J-K flip-flops Motorola MC852P in the variable modulus counter (Figure 2) are driven from the cascaded decade counter. The outputs of these flip-flops are compared to the number set in switch register SI to S4 by circuits that perform an EXCLUSIVE-OR function (e.g., G2 to G4). When the number in the counter equals that in the switch register minus one, G24 configures the flip-flop inputs to reset to zero on the next count. The cycle then repeats itself. The clock output is thus a train of pulses, each pulse having the length of a cycle of the base frequency. Pulses of short and constant length can be obtained from OS, a monostable multivibrator (Motorola MC851P). The counter cannot divide by one. When a “one” is set in the switch register (SI is open), the output of G23 disables G26 and allows the base frequency to pass through G27. The counter divides by 16 when a “zero” appears in the switch register. To avoid switch contact bounce problems, the counter is enabled and disabled through an R-S flip-flop, G29 and G30. The counter was designed separately from the data acquisition system and may be used independently of the system. All gates are Motorola integrated DTL circuits, MC846P, MC861P, and MC844P. The performance of the overall system is in general the same or better than the specifications given above for the individual components. The total noise in the sequential mode of operation for the system is h0.5 mV. This value was determined by observing the input voltage span over which jitter
occurred in the least significant bit. The measurement was made at ground potential where jitter causes all bits to change, making system noise a maximum. No significant evidence of crosstalk in the multiplexer was observed. About 20 mV of thermal drift was observed during the first 30 minutes of instrument warmup. After that point, both the short term and long term drift was 1 2 . 5 mV. Figure 5 shows a typical flow sheet for a program to acquire X-Y data in the sequential mode. Operations such as checking for the correct address, storing data, and incrementing counters are performed during the encoding periods if possible. This allows the data rate to approach the time required for analog-to-digital conversion. Data rates of 10 kHz (per X-Y pair) and 30 kHz can easily be obtained in the sequential mode and the random mode (single channel) respectively. Programming is done in assembly language for the reasons given by Lauer and Osteryoung (9). Operation of the system is made easy for the programmer through the use of computer words designed to perform only one function. The input system is enabled by outputting the number (lOOOOO)8 to the GPR card in the sequential mode, and (lXOOOO)8 in the random mode where X is the input channel (0 X i 7)s. The clock is enabled with the word (O2OOOO)8 or inhibited by (024000)8 followed by an encode command. The programmer need only know the proper computer words to operate the system. These may be combined by performing an AND operation to provide several operations at once.
