Graphene and Thin-Film Semiconductor Heterojunction Transistors

Samsung Advanced Institute of Technology, Samsung Electronics Co., 97 Samsung2-ro, Giheung-gu, Yongin-si, Gyeonggi-do 446-712, Korea .... For Vd = −...
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Graphene and Thin-Film Semiconductor Heterojunction Transistors Integrated on Wafer Scale for Low-Power Electronics Jinseong Heo, Kyung-Eun Byun, Jaeho Lee, Hyun-Jong Chung,† Sanghun Jeon,‡ Seongjun Park,* and Sungwoo Hwang Samsung Advanced Institute of Technology, Samsung Electronics Co., 97 Samsung2-ro, Giheung-gu, Yongin-si, Gyeonggi-do 446-712, Korea S Supporting Information *

ABSTRACT: Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene−thin-film-semiconductor−metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate waferscale integration of vertical field-effect transistors (VFETs) based on graphene−In−Ga−Zn−O (IGZO)−metal asymmetric junctions on a transparent 150 × 150 mm2 glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 106 with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V. KEYWORDS: Graphene, thin-film semiconductor, heterojunction transistor, wafer-scale integration, low-power electronics

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asymmetric junctions. In addition, IGZO has been widely used as an active matrix for thin-film transistors (TFTs) in flat-panel displays, and it has the advantage of low-temperature processability with a high uniformity of the deposited film over a large area, thereby making it compatible with a wide range of substrates. For logic applications, we can further design p-type devices by replacing the n-type IGZO with an appropriate p-type material, for example, a Ge thin film.16,17 In such a device, a triangular barrier for holes between graphene and the metal is expected. The approach of combining complementary GSMs offers a route for low-power electronics. Figure 1a shows a schematic diagram of our GSM structure. Wafer-scale integration of such devices is described in detail in Figures S1 and S2 of the Supporting Information. In brief, a drain electrode (50 nm) was first defined on a transparent glass substrate and brought into contact with a postdeposited TFS. The thickness of the TFS was varied from 10 to 20 nm. Subsequently, monolayer graphene grown by chemical vapor deposition (CVD) was transferred6,18 on top of the TFS and brought into contact with a source electrode. Finally, a top-gate electrode was patterned on top of a dielectric Al2O3 film (7−20 nm).

ne-atom-thick monolayer graphene has been enormously explored for future electronics.1−5 In particular, the workfunction tunability of graphene1,2 has recently been exploited in graphene heterostructure devices such as barristors,6 graphenebase transistors,7 and vertical field-effect transistors (VFETs)8−10 and has enabled dramatically increased Ion/Ioff than graphene field-effect devices with planar geometry; hence, they have shown promise for digital electronics. However, from an application point of view, the heterojunctions of the VFETs were created by consecutive manual processes using micrometer-scale flakes of 2D barrier materials such as hexagonal boron nitride (hBN), molybdenum disulfide (MoS2), or tungsten disulfide (WS2),8−10 and scalability remained a critical challenge for practical integration. Aside from the critical issue of scalability, lowpower dissipation in driving logic circuits is highly desirable for VFETs for future electronics. In fact, the current CMOS technology has reached its limit for further reducing the operating bias voltage, which leads to inevitably higher power consumption.11,12 This work presents the wafer-scale integration of VFETs based on GSM junctions on a transparent substrate, with integrated devices applicable for low-power electronics. The key factor is the implementation of the oxide semiconductor IGZO13−15 as a sandwiched thin-film semiconductor (TFS). IGZO is carefully selected so that a triangular energy barrier for electrons forms between graphene and the metal even at zero bias. Thus, low-bias operation is possible in graphene−IGZO−metal © 2013 American Chemical Society

Received: August 22, 2013 Revised: November 15, 2013 Published: November 20, 2013 5967

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Figure 1. Vertical field-effect transistors based on graphene−IGZO− metal heterojunctions. (a) Schematic of a vertical field-effect transistor based on graphene−IGZO−metal junctions. Inset: Heterojunction cross-section. A chain of black circles representing monolayer graphene is in contact with the amorphous IGZO below. (b) Crosssectional TEM image of the vertical transistor illustrated in panel a. From the bottom: Ni drain, IGZO (10 nm), monolayer graphene, Al2O3 (7 nm), Cr (5 nm), and Pt (30 nm). Scale bar: 10 nm. (c) Optical image of a fabricated vertical transistor. A part of the gate electrode was intentionally peeled off to show the false-colored IGZO film. Graphene is not visible but outlined with the dashed line along the source electrode. The junction area is 2 × 12 μm2. The threeterminal measurement scheme is also shown. Scale bar: 5 μm. (d) Integrated vertical transistors on a 150 × 150 mm2 transparent glass wafer. Scale bar: 2 cm.

Figure 2. Electrical properties and statistics of graphene−IGZO−Ni vertical transistors. (a) Semilogarithmic J−Vd characteristics of a graphene−IGZO (10 nm)−Ni vertical transistor at various Vg. Vg varies in the range −3 to 3 V, in steps of 1 V from the bottom curve. The device area is 50 μm2. (b) Semilogarithmic J−Vg characteristics for a few representative devices. A maximum Ion/Ioff of up to 106 is obtained with the minimum SS of 1 V/dec Inset: ΔEF as a function of ΔVg from capacitance−voltage measurements. (c) Log-normal distribution of Ion/Ioff for 2062 devices. Ion/Ioff is 3010 with a standard error of 398.7. (d) Log-normal distribution of Jon and Joff for the devices in panel c. Jon and Joff are 89 and 0.47 nA/μm2, respectively.

high transmittance of electrons through the barrier at the interface between IGZO and Ni. We investigated 2062 devices on a wafer to obtain averages of 3010 for Ion/Ioff with a maximum of 106 (Figure 2c) and 0.089 μA/μm2 for Jon with a maximum of 1.72 μA/μm2 (Figure 2d) at Vd = 0.1 V. Note that Ion/Ioff as well as Ion and Ioff follow a log-normal distribution. Because the normal distribution of Ion/Ioff in conventional graphene devices (Figure S4 of Supporting Information) corresponds to the variation of ΔEF or work function modulation in graphene (ΔWG), the log-normal distribution of Ion/Ioff originates from the exponential dependence of J on ΔWG. It is also likely that a normal distribution of the doping level of graphene in each device results in a log-normal distribution for Jon and Joff. These variations in distributions originate from intrinsic or extrinsic doping in graphene and can be minimized by improving the CVD growth process for graphene and the subsequent transfer. A schematic band diagram along the GSM junction in Figure 3a−c illustrates device operation. WG ≈ 4.5 eV aligns to the conduction band minimum (EC ≈ 4.5 eV) of IGZO14 (Figure S5,6 of Supporting Information), resulting in no energy barrier at the interface. There is a definite energy barrier between IGZO and the metal with the work function WM > 4.5 eV. The barrier height is determined from the work-function difference, ΔWM (eV) = WM − 4.5. This scheme is comparable to band-to-band tunnelling junctions in tunnelling field-effect transistors (TFETs).19−21 In TFETs, the external gate electric field is perpendicular to the direction of current flow across the heterojunction, and the barrier height can only be changed by replacing the channel material. The vertical current flow in GSM VFETs is well-controlled by a parallel gate electric field over the junction area, and the barrier width and height can be easily engineered by changing the thickness (t) of the TFS and metal with different WM, respectively.

A cross-sectional transmission electron microscopy (TEM) image from the top gate electrode to the bottom drain electrode in the inset of Figure 1a is shown in Figure 1b. The thickness of the deposited IGZO film (t) is ∼10 nm, and the film has a uniform amorphous phase14 on top of the Ni drain electrode. In addition, a well-defined junction between the transferred monolayer graphene and IGZO is clearly seen. Figure 1c shows the top view of a fabricated device (width: 12 μm, length: 2 μm) with a three-terminal measurement scheme. We intentionally peeled off a part of the gate electrode to expose the underlying heterojunction. We demonstrated wafer-scale integration of over 2000 devices on a 150 × 150 mm2 transparent glass substrate (Figure 1d). Figure 2a shows the current density (J) versus the drain voltage (Vd) characteristics of a GSM VFET composed of graphene−IGZO (10 nm)−Ni for various applied gate voltages. For Vd = −0.5 to 0.2 V, Ion/Ioff = 105 to 106 is obtained as the top gate voltage (Vg) is varied from −3 to 3 V with an oncurrent density (Jon) of 0.7 μA/μm2 at Vd = −0.5 V. A colorscale plot of J versus Vd and Vg for a typical sample is illustrated in Figure S3 of Supporting Information. As Vg increases from −3 to 3 V at Vd = 0.1 V, J is exponentially modulated, yielding a minimum subthreshold swing (SS) of 1 V/dec with an average of 1.2 V/dec for a few representative samples (Figure 2b). SS can be improved when the gate efficiency of the Fermi energy change in graphene (ΔEF) is enhanced. In our device, ΔEF as a function of ΔVg is plotted in the inset of Figure 2b using capacitance−voltage measurements (S8 of Supporting Information), resulting in ΔEF = 240 meV for ΔVg = 5 V and five decades of current modulation in Figure 2b. For the on-current density (Jon) at Vg = 3 V, the GSM device exhibited ohmic behavior, indicating a 5968

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where DG(E) and DM(E) are available density of states in graphene and metal, respectively, f(E) is the Fermi-Dirac distribution, and T(E) is the tunneling probability. If a triangular barrier with uniform field is assumed for thin amorphous IGZO layer, T(E) ≈ exp(−(4(2m*)1/2(ΔWM)3/2)/(3eℏε)), where e is the electric charge, m* is the effective mass of an electron in the barrier, ℏ is the reduced Planck constant, and ε is the electric field across the barrier. As Vg is varied, the tunneling current density, J, is modulated by the change of the density of states in graphene, that is, explicitly by the change of DG(E) in J and also by the change of tunneling probability, T(E). Although DG(E) = 2E/ π(ℏvF)2 goes to zero at Dirac point, there often exist electron− hole puddles, and typical residual carrier density is n = 1011 to 1012 cm−2 caused by adjacent charge impurities, so DG(E) has a finite value throughout. More dominantly, T(E) is changed through the exponent, ε = ((ΔWM + eVd + ΔWG)/t) = ε0 + Δε, where Δε = ΔWG/t due to the increased or decreased graphene workfunction. We study the barrier-dependent device characteristics by comparing statistical measures: the average of Jon, Joff, and Ion/ Ioff ( Jon , Joff , and Ion /Ioff ). First, we observed the variation of Jon , Joff , and Ion /Ioff with WM, that is, a different metal. We tested 100 devices for each Mo, Ni, Au, and Pt drain with t = 10 nm (Figure 4a), which have WM in increasing order, roughly 4.6, 5.2, 5.4, and 5.9 eV, respectively22 (Figure S6 of Supporting Information). When a nearly ohmic contact is made with Mo,14,23,24 the maximum Ion/Ioff is ∼50 with an average of 7, which follows from band modulation of the semiconductor by the gate electric field that penetrates the graphene monolayer. We find that Jon (Vd = 0.1 V, red squares in Figure 4a) is reduced by one order of magnitude for each increase in the barrier height when varying from Mo, Ni, Au, to Pt. However, there is no significant difference in Joff (Vd = 0.1 V, blue circles in Figure 4a) for Ni, Au, and Pt, possibly owing to universal leakage current (order of 10 pA/μm2) through the defect sites of the IGZO film14,25−27 when t is fixed. Differences in Jon for each metal are also specified by the values Ion /Ioff in Figure 4a and representative J versus Vg (Vd = 0.1 V) characteristics for each median Ion/Ioff are plotted in Figure 4b. For graphene−IGZO−Pt junctions, the t dependence of Jon , Joff , and Ion /Ioff is measured (Figure 4a, inset) and shows a reduction in both Jon and Joff within a factor of three as t varies from 10 to 20 nm, while Ion /Ioff remained almost the same. Such a trend is expected owing to the decreased electron injection efficiency by the moderate electric field and suppressed leakage current via increased junction distance. However, J−Vg characteristics for two samples with different t (t = 10, 20 nm) at various temperatures (T) reveal significant differences (Figure 4c,d). We find that for t = 10 nm (Figure 4c), the thermal variation of J is within one order of magnitude, and Ion/Ioff remains almost constant throughout the range of T = 100− 300 K (Figure 4c, inset), implying that the temperatureindependent tunnelling component of the total current significantly contributes. Joff for the thicker sample (t = 20 nm) is dominated by thermal activation above 160 K, and Ion/Ioff varies with T by three orders of magnitude (Figure 4d; Figure S10 of Supporting Information), similar to barristors6 and other work.9,10 Thus far, we have discussed n-type devices at low bias; however, a complementary p-type GSM device is necessary for low-power logic operation. We use an electron-beam (e-beam) evaporated Ge thin film on top of Al to fabricate graphene−Ge−Al junctions (Figure 5a) for p-type operation (J decreases with Vg). From the

Figure 3. Schematic band diagram of GSM vertical transistors. (a) Schematic band diagram of heterojunctions (graphene−IGZO−metal) at equilibrium. A triangular energy barrier between graphene and the drain metal has a width t and height ΔWM. Vg and Vd are applied with respect to graphene connected to the ground. (b,c) Band diagram at negative Vd. For negative Vg (b), WG increases to suppress electron injection from the drain metal, whereas for positive Vg (c), the injection is dramatically increased owing to the enhanced electric field between graphene and the metal, where the enhancement is caused by both the decreased WG and the band bending of IGZO.

A designed asymmetric barrier (Figure 3a) causes an asymmetry in J between negative and positive Vd at negative Vg (Figure 2a) because positive Vd compensates for the built-in barrier to allow for relatively enhanced current flow. For an electron injected from the metal side (negative Vd), the electron injection is suppressed if WG is increased by applying negative Vg (Figure 3b). This results in the Ioff state because the effective barrier width remains the same and the charge carriers in the semiconductor are depleted. When Vg is positive (Figure 3c), the effective electric field between graphene and the metal is enhanced according to a lowered WG and band bending in the semiconductor,10 resulting in increased electron injection leading to the Ion state. This explains the n-type operation (J increases with Vg) of graphene−IGZO−Ni devices in Figure 2b. Ion/Ioff is thus derived from the modulation of the electric field across the junctions and, more importantly, can be optimized by varying the barrier defining parameters t and ΔWM because these parameters determine the band profile for various bias conditions that influences the device performance. To explain the modulation of total current by gate modulation of the density of states in graphene, we consider tunneling current between graphene and metal through the barrier, and the current density is described by J(Vd) ∝

∫

dE · DG(E)· DM(E − eVd)·[f (E − eVd) − f (E)]·T (E) 5969

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Figure 4. Barrier dependence of device characteristics. (a) Jon (red squares) and Joff (blue circles) with standard errors as a function of ΔWM = 0.1, 0.7, 0.9, and 1.4 for Mo, Ni, Au, and Pt of drain metal, respectively and as a function of t (10, 15, 20 nm, inset) for Pt. One hundred devices (graphene−IGZO(10 nm)−metal) were measured for each metal. Ion/Ioff is also specified. (b) J−Vg characteristics for the median Ion/Ioff samples in each metal. (c,d) Semilogarithmic J−Vg characteristics of graphene−IGZO−Pt devices at various temperatures T ranging from 77 to 300 K. The thickness of IGZO and Vd is 10 nm and 0.3 V, respectively, in panel c and 20 nm and 1 V, respectively, in panel d. Insets: Ion/Ioff as a function of T. The thickness of Al2O3 is 20 nm. The device area is 10 μm2.

Figure 5. Complementary inverter with a p-type GSM device. (a) Cross-sectional TEM image of a graphene−Ge (10 nm)−Al device. Scale bar: 10 nm. (b) J−Vd characteristics of the device at various Vg = −3 to 3 V in steps of 1 V. Inset: J−Vg characteristic at Vd = 0.1 V. The device area is 10 μm2. (c) Vin−Vout characteristics for a complementary inverter combining p-type [graphene−Ge(10 nm)−Al] and n-type [graphene−IGZO(10 nm)−Ni] devices. VDD varies from 1 to 0.1 V in steps of 0.1 V. Inset: Schematic circuit diagram for the inverter. (d) Inverter gain as a function of Vin at different fixed VDD from 1 to 0.1 V in steps of 0.1 V. Inset: Inverter gain as a function of VDD. The gains are 2.7, 1.1, and 0.24 at VDD = 1, 0.5, and 0.1 V, respectively.

Another advantage of the GSM architecture originates from tailoring of the triangular energy barrier for a given TFS; therefore, the device performance in this work was optimized such that high Ion/Ioff at a low bias voltage was obtained. An SS of 1 V/dec here represents the state of the current process engineering rather than the intrinsic limit of our device. Furthermore, the demonstration of an inverter operating at low bias shows promise that our approach is a viable option for future low-power electronics.

J−Vg characteristics shown in Figure 5b, Ion/Ioff ≈ 10 (Figure 5b, inset) and ohmic behavior at Vg = −3 V (Jon state) is present, but Joff at Vg = 3 V is on the order of 5 nA/μm2 at Vd = 0.1 V, which is two orders of magnitude larger than ∼10 pA/μm2 for the n-type device (Figure 4a). The relatively large leakage current is likely due to conduction through defects in the amorphous Ge thin film, which can be reduced after improving the deposited film quality.28 Because Jon for Vd < 0.5 V is comparable to that of the n-type device, a logic inverter combining two complementary GSM devices is operational. Figure 5c shows the Vin versus Vout characteristics of a fabricated inverter at various drain bias voltages (VDD) from 1.0 to 0.1 V in steps of 0.1 V. A maximum gain of 2.7 at VDD = 1 V is obtained and monotonically reduced to 1.1 at VDD = 0.5 V (Figure 5d). Thus, the inverter operation at the lowest reported VDD of 0.5 V for graphene devices is demonstrated and attributed to the triangular barriers present in our GSM devices. Note that a gate voltage should be matched with low bias voltage for cascading low-power operation of logic gates and with the low gate voltage, Ion/Ioff would be reduced much, but we believe this can be improved by reducing oxide thickness or employing high-κ material like HfO2. In the present work, we have developed a new technological method for wafer-scale integration of VFETs by implementing a TFS in GSM heterostructures. The fabrication fully exploited standard semiconductor processes and enabled the statistical assessment of device characteristics at a wafer level, as required for practical application. With this scheme, a variety of materials including compound semiconductors can be explored and implemented for enhanced device performance in the future; in particular, a p-type device still needs further development.

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ASSOCIATED CONTENT

S Supporting Information *

Schematic illustration of vertical GSM transistor fabrication. Optical image and Raman spectroscopy of graphene on semiconductor−metal junctions. Electrical characterization of a graphene−IGZO (10 nm)−Ni device. Statistical distribution of Ion/Ioff in conventional graphene devices. Electrical characterization of an IGZO thin-film transistor. Work-function measurement and estimation for graphene, Mo, Ni, Au, and Pt by ultraviolet photoelectron spectroscopy and X-ray diffraction. Statistical Ion/Ioff of the GSM devices with Mo, Ni, Au, and Pt drains. J−V characteristics of a graphene−IGZO (10 nm)−Mo device and an estimation of Ion/Ioff and C−V measurement information. Temperature-dependent J−V characteristics of a graphene−IGZO−Pt device. This material is available free of charge via the Internet at http://pubs.acs.org.

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AUTHOR INFORMATION

Corresponding Author

*Phone: +82-031-280-9479. Fax: +82-031-280-9308. E-mail: [email protected]. 5970

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†

H.-J.C.: Department of Physics, Konkuk University, Gwangjin-gu, Seoul 143−701, South Korea. ‡ S.J.: Department of Display and Semiconductor Physics, Korea University Sejong Campus, Sejong 339−700, South Korea. Author Contributions

J.H. and S.P. conceived this work. J.H. designed the experiment. J.H. carried out the device fabrication, characterization, and data analysis. S.J. advised on the fabrication. S.P., K.-E.B., J.L., and H.-J.C. contributed to the analysis and interpretation of the results. J.H. wrote the manuscript. S.P. and S.H. supervised the project. All authors discussed the results and commented on the manuscript. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors are grateful for assistance provided by colleagues at Samsung Advanced Institute of Technology: X. Li for TEM analysis, B. Anass for UPS analysis, and Nano Fabrication group for process assistance. We are also grateful to P. Kim at Columbia University for useful discussions.

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