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High-Conversion-Rate Electronic Integrator with Digital Readout for Flameless Atomic Absorption Spectrometry Frank Bertram, Jr., John E. Taphorn 111, Wayne B. Robblns, Edgar J. Younginger, and Joseph A. Caruso* Department of Chemistry, University of Cincinnati, Cincinnati, Ohio 4522 I
The application of flameless atomic absorption spectrometry (AA) to trace metal analyses has in some instances posed difficulties in evaluating the analytical response, particularly in obtaining reproducible peak heights. These difficulties and possible solutions to them have been discussed by Sturgeon et al. in a recent authoritative study (1).As noted by Schramel and others, for certain volatile elements the integrated area technique is superior to the peak height measurement ( 1 , 2 ) . Various types of integrators have been used and are appropriately described elsewhere (1-6). Digital integration may be accomplished in numerous ways, many of which are carefully described by Malmstadt, Enke, and Crouch (7).Graeme, Tobey, and Huelsman describe a reactance oscillator integrator (8). Recently a single component chip has been described which provides an output frequency proportional to the input voltage over a range of six decades (9). This study describes a digital integrator where the voltage-to-frequency conversion (V-F) is accomplished by firing a unijunction transistor (UJT). A detailed description of the analog signal conditioning and the peak detection circuitry is provided. The implementation of this device for flameless AA is discussed. GENERAL DESCRIPTION The integrator consists of 4 printed circuit boards: 1) a regulated power supply board, 2) an analog board, 3) a digital board containing the V-F converter, 4)a display control board. For convenience, the seven-segment Apollo displays are contained on a separate small board. The complete assembly was mounted by means of Plexiglas supports in a Bud Compucab Instrument Cabinet Model SC-13101. BENCH TESTING T o simulate the atomic absorption (AA) experiments, a 1.5-V dc source was connected to the input of the integrator. This effectively simulated a 100% T signal. The integrator was then set up to count (as is later described) upon a decrease in the 1.5-volt input (less than 100% T ) .After the instrument performed satisfactorily in this mode, it was tested with the Jarrell-Ash Maximum Versatility Model 82-500 spectrometer, equipped with a Varian Techtron Model 63 Carbon Rod Atomizer and a Hewlett-Packard Model 7101B strip chart recorder. Further details on this instrumentation and its operations are found elsewhere (IO). All standard solutions were prepared from Fisher Certified atomic absorption standards with appropriate dilutions. ELECTRONIC CIRCUIT DESCRIPTION Board No. 1-Power Supply Board. The f15-V dc section can be of any practical design with good regulation and capable of providing approximately 1A. The +5-V dc section must be able to provide between 2 to 3 A because of the heavy load presented by the T T L integrated circuitry and the incandescent 7-segment displays. CMOS counterparts are
available as substitutes for the 7400 T T L family, which could greatly reduce the high current requirement on the +5-V dc power supply. Board No. 2-Analog Board. This board, as shown in Figure 1, is used to amplify the incoming signal, balance the background, sense the apex of the peak, and set levels for the start and termination of the integration. The quiescent signal, in our case +1.515 V with a battery source, is applied to the signal input jack (SI, upper left of Figure 1).One half of IC1, a dual operational amplifier, is used to amplify the input signal to a maximum output of 10 V or less. The potentiometer, R3, is then adjusted as necessary to zero the quiescent voltage output. This condition is monitored a t TP1. The above condition corresponds to the maximum (100% T ) signal condition and, as the battery voltage decreases, the output signal changes from zero to a positive 10 V or less. The signal output from the first half of IC1 is connected to the peak detecting circuit, consisting of the second half of IC1 and IC2; also it is connected to a comparator, IC3, and a quad, bilateral, CMOS analog electronic switch, IC5. The signal can be monitored a t TP8. The peak-detecting circuit utilizes the first half of IC2 and diodes D1 and D2 as a comparator. Capacitor C1 charges through D1 as the signal output of IC1/1 goes positive. The voltage across C1 is applied to the non-inverting input of IC2/1 through follower Q6, while the output of IC1/1 is applied directly to the inverting input of IC2/1. Balance of the inputs to IC2/1 is adjusted by R8 and is monitored at TP7 (the output a t TP7 remains high until the slope of the peak reverses). The second half of IC2 also acts as a comparator for the signals from IC1/2 and IC2/1. Any change in the output from IC2/1 is reflected by IC2/2 and causes a nonreversible change in the state of the flip-flop, made by using two sections of IC4. The state of this flip-flop can be observed at TP4. A dual comparator (IC3) is used to control threshold limits. One threshold starts the integration, and the other terminates it. When the signal into IC3 exceeds the threshold established by R20 (adjusted while monitoring TP2), the common comparator output goes high, is inverted by one section of IC4, and turns off Q2. This enables the electronic switch, IC5 and permits the signal to be applied to the integrator input. The strobe of IC3 is enabled through zener diode ZD4 (5.6 V), which is irrelevant at this time because IC3/1 has established the output. However, when the apex of the peak is detected, as described above, IC3/1 is disabled by its strobe going low, and IC3/2 assumes control of the comparator output. When the terminating threshold, established by R22 (adjusted by monitoring TP3), is crossed, the comparator output goes low, is inverted and turns on Q2. This action disables IC5 and causes integration to cease. The +lo-V dc and -5-V dc required for IC3 and the +lo-V dc required for IC5 are generated from the f15-V dc by means of two zener diodes, ZDl(5.6 V) and ZD2 (10 V). This circuitry is shown in the upper right-hand corner of Figure 1.
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Figure 1. Circuit diagram of analog board
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-is Flgure 2. Circuit diagram of digital board
Zener diode ZD3 (4 V) is placed in this circuit to protect the input to IC3 from excessive voltage, which can cause it to cease functioning. Resistor R12, in turn, prevents excessive current drain from the output of IC1/1 at higher voltages which can result in a reduction of linear response. Board No. 3-Digital Board. The digital board is shown schematically in Figure 2. The input to the digital board is the processed analog signal from board No. 2 and is directed into the integrator and V-F converter via R28. This signal can be monitored a t TP5. T o understand the operation of the V-F converter, first consider R28, C2, and IC6. These comprise a standard integrator. If a voltage is applied to R28 at TP5, C2 will charge to the maximum voltage level which can be provided by IC6. If a switch is used to discharge C2 at a certain voltage level lower than maximum, a cyclic sawtooth waveform would be generated at a frequency proportional to the voltage applied to R28. The unijunction transistor is such a switch. When a positive voltage is applied to R28, the output of IC6 will go negative to charge C2. The summing junction a t the 2272
3. Generalized schematic of display control board
inverting input to IC6 will remain a t 0 V. The emitter of the unijunction transistor is held at 0 V, while base 2 goes negative. When the voltage between the emitter and base 2 reaches the intrinsic standoff ratio, the unijunction transistor will fire, causing C2 to discharge. During this discharge, current in the primary of the transformer creates a pulse which, after suitable amplification by Q4 and Q5, is applied to the decimal counters. The circuitry including Q3 provides a means by which the peak point can be varied to some extent. Also when T P 5 is grounded, IC6 can be balanced by R34 using TP6 to verify this condition. A switch, SW5, and associated counters are provided to decrement the displayed count by powers of 10 if desired. The digital circuitry following SW5 is necessary to provide pulses compatible with the display control counters and to control the count direction. The monostable (74121) is wired internally to give a nominal 30-ns pulse width. The NAND gates (7400) are utilized as an input selector switch (multiplexer). The configuration for this is shown on page 571 of Ref. 7. Board No. 4-Display Control Board. Six Apollo DA2300 seven-segment incandescent displays are controlled by the display control board. This circuit diagram is not shown as T T L decade counting logic is widely known. However, a
ANALYTICAL CHEMISTRY, VOL. 48, NO. 14, DECEMBER 1976
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Figure 4.
Completed integrator in cabinet T,SEC
Table I. Major Parts List a No. Parts 2 558 Dual Operational Amplifiers (IC1 and IC2) 1 741 Operational Amplifier (IC6) 2 7400 Quad Nand Gates (IC41 1 SN72811 Dual Comparator (IC31 1 4016 CMOS Switch (IC5) 5 2N5225 NPN Transistor ($1-5) 2 MPFll2 Field Effect Transistors (Q6-7) 1 2N4871 Unijunction Transistor (Q8) 4 1N914 Diodes (Dl-4) 3 7490 Decade Counters 1 74121 Monostable Multivibrator 6 74192 Presetable upldown counter 6 7475 Bistable Latch 6 7447 DecoderIDriver 6 DA2300 Apollo Displays 0 A complete parts list, as well as additional information, can be obtained by contacting the authors.
general representation is shown in Figure 3. I t consists of six decades with each decade composed of a 74192 presetable, up-down decade counter, a 7475 latch, a 7447 decoder driver, and seven-segment display. The latch is incorporated into the system to hold the display momentarily, since it is possible that this feature might be desirable. External Controls a n d Test Points. Those switches, adjustments, and associated test points which require more frequent adjustment are placed on the external portion of the cabinet. A picture of the completed unit is shown in Figure 4, and front panel controls may be seen as described below. On the front of the cabinet are the following switches: 1)SW1, upldown count; 2) SW2, manual auto (disables peak detecting in manual); 3) SW3, reset; 4) SW4, display latch; 5) “divide by” (decrements the displayed count); 6) SW6, input gain; 7) SW7, master power. Switch SW3 is normally closed to chassis ground (logic “0”). When opened, all counters, Q1, and IC4 are reset. Switch SW6 is shown with 4 positions for simplicity. I t is actually a 12-position rotary switch providing gains from 1 to 1000. The test points are useful for setting up the instrument for specific voltage levels, as well as for troubleshooting. Those potentiometers and test points on the front are: 1)R3 and TP1, balance; 2 ) R20 and TP2, threshold 1;3) R22 and TP3, threshold 2; 4) TP4, the flip-flop state; 5) common. On the back of the cabinet are placed R34, integrator balance; TP5
Figure 5. Plot of
counts vs. Tat various simulated % absorption
i ABSORPTION
Figure 6. Plot of
CPS vs. simulated % absorption
and TP6, integrator input and output; TP7, FET balance; TP8, switch input; common, and the input signal jack. Component List. A list of the major components, excluding those in the power supply, are given in Table I. RESULTS AND DISCUSSION The linearity of the digital count rate vs. time was compared. A constant voltage signal of +1.515 V was presented to the integrator input. This then was balanced as previously discussed. A series of “simulated” % absorption (100 - % T ) measurements were taken as a function of time with experiments lasting from 1 to 20 s. The simulated % absorption was achieved as follows: The +1.515-V signal was decreased by 0.038,0.076,0.151,0.227,0.303,0.379,0.455,0.530,0.606,0.682, and 0.833 V, corresponding to simulated % absorptions of 2.5,
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5, 10, 15, 20, 25, 30, 35, 40, 45, and 55%, respectively. The general effect here was to present a negative going square wave of varying duration to the integrator input. Since the integrator was balanced at +1.515 V, any signal level less than that would cause counting to occur. These count vs. time experiments showed linear behavior as given in Figure 5 by representative data taken from 1to 10 s a t 2.5 to 40% absorption. The data taken for counts vs. time as a function of various fixed voltages were further utilized to simulate a typical atomic absorption experiment where % absorption increases as the photomultiplier output decreases. It is believed that elimination of bias from additional instrumentation is important in evaluating the merits of the integrator. For a flameless AA experiment, the time interval of such an experiment would be fixed. Thus, a plot of counts per second (CPS) vs. % absorption (var,yingbattery voltages simulating varying phototube output) should indicate the best response available from the integrator. Such a response is independent of the quality and performance of any instrument(s1 the integrator might eventually be coupled to, and a better response should be impossible. By plotting the slopes (CPS as determined by linear regression) of the lines in Figure 5 vs. the % absorption (voltage decrement), the AA experiment is simulated as absorption is a function of concentration. Such a plot is shown in Figure 6, and the response is linear up to 35% absorption (-16 000 counts per second or -32 000 counts for a typical flameless AA experiment; normally measurements yield a smaller count rate as shown below). From 35 to 55% absorption, the slope of Figure 6 drops somewhat into a second linear region. This is not unexpected, since the integral of % absorption would not necessarily be linear over a wide range. However, it would be expected that the integral of absorbance would be linear over the indicated range. By calculating the absorbance, A , from the simulated % absorption values, it was possible to prepare a plot similar to Figure 6 using these calculated data, which was linear to 0.3 absorbance unit (-50% absorption). By varying SW5 and SW6 and adjusting R31, the count rate may be slowed considerably-an important consideration if a slower experiment such as chromatography is considered. The integrator was coupled to the atomic absorption spectrometer and preliminary data were taken for copper and cadmium standard solutions. The 100% T (0%A ) input voltage provided the integrator was balanced as previously discussed. The AA instrument was run in the "undamped" mode allowing both recorder and integrator adequate response time for the ca. 2-s duration of the carbon rod flash. Somewhat troublesome was a 300-mV sawtooth wave riding on the selected 1.8-Voutput of the AA instrument (the recorder output was at a different point and no problems were noted with it). While this could be compensated for by adjusting the
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threshold, it apparently contributed to an offset in the calibration curves obtained. Thus both the cadmium and copper calibration curves were linear up to 50 pg and 500 pg, respectively, but were offset from zero, although no counts were observed at 0% absorption. In addition to the ac noise, this offset may be partially caused by the general irreproducibility associated with the carbon rod atomizer at low (
