NANO LETTERS
High-Current Nanotube Transistors Robert Seidel,* Andrew P. Graham, Eugen Unger, Georg S. Duesberg, Maik Liebau, Werner Steinhoegl, Franz Kreupl, and Wolfgang Hoenlein
2004 Vol. 4, No. 5 831-834
Infineon Technologies AG, Corporate Research, 81730 Munich, Germany
Wolfgang Pompe Institut fu¨r Werkstoffwissenschaft, Technische UniVersita¨t Dresden, 01062 Dresden, Germany Received February 10, 2004; Revised Manuscript Received March 25, 2004
ABSTRACT Planar field effect transistors (FET) consisting of a large number of parallel single-walled carbon nanotubes (SWCNT) have been fabricated that allow very high on-currents of the order of several milliamperes and on/off ratios exceeding 500. With these devices it is demonstrated, for the first time, that SWCNTs can be used as transistors to control macroscopic devices, e.g., light emitting diodes and electromotors. Those transistors were fabricated by a very simple process that is based on the catalytic chemical vapor deposition (CCVD) growth of SWCNTs at low temperatures, a single lithographic step to define the source and drain contacts, and a bias pulse to eliminate the metallic SWCNTs.
There has been tremendous interest in carbon nanotubes in the past decade1 due to their superior electronic properties and the possibility that they could replace silicon in future nanoelectronic devices if the integration challenges can be solved. However, carbon nanotubes are also interesting for applications where larger currents have to be switched or detected, e.g., power transistors, flexible electronics, or sensors. Since the maximum current per individual SWCNT is limited to about 25 µA,2 a parallel arrangement of a large number of SWCNTs is required. Fabrication of such an arrangement requires a process to grow or deposit SWCNTs uniformly on a substrate. Catalytic CVD allows the growth of very clean, amorphous carbon-free SWCNTs on substrates and the control over the density of active catalytic sites and, therefore, the density of the SWCNTs. Control of the SWCNT density is very important in order to achieve transistors with uniform performance, for reasons discussed below. Extensive studies of the CVD growth have shown that this can be achieved by varying the catalyst material, catalyst layer thickness, and the growth parameters. Those results have been published elsewhere.3,4 The substrate for the SWCNT transistors was p-type silicon with a 50 nm thick atomic-layer-deposited (ALD) Al2O3 with a k-value of about 11. Nickel was chosen as the catalyst metal, since it has been shown that Ni catalyzes the thermal CVD growth of SWCNTs at temperatures as low as 600 °C.5 Ni layers with a nominal thickness of less than 0.2 nm were deposited by a high-precision ion-beam deposition system with a quartz crystal microbalance or by spin* Corresponding author. Phone: (+49) 89 234-52755, E-mail: robert.seidel @infineon.com. 10.1021/nl049776e CCC: $27.50 Published on Web 04/10/2004
© 2004 American Chemical Society
Figure 1. SEM image of a parallel SWCNT transistor. The gap between the outer frame and the square defines the gate.
on deposition of an ethanol-based nickel-acetate solution.4 The SWCNTs were grown in a preheated quartz tube furnace at 650 °C. After 5-10 min hydrogen pretreatment the growth was initiated by filling the furnace with pure methane to a pressure of 0.3-0.4 bar. After 10 min the growth was stopped by evacuating the furnace and the samples were removed from the furnace after cooling-down to room temperature. Subsequently, the transistors, shown in Figure 1, were defined by e-beam lithography whereby the gap between source and drain, which defines the gate length, was varied (Figure 2). The smallest gate length was about 90 nm. The total gate width, which is equal to the circumference of the inner contact square, was always kept constant at 200 µm. The source and drain contacts were formed by depositing
Figure 2. Magnified SEM image showing the gate region (230 nm gate length) of a transistor consisting of a large number of SWCNTs.
30-40 nm palladium by e-beam evaporation. Recently it has been shown that Pd yields very good contacts to SWCNTs because of its high work function and corrosion resistance.2,6 The resulting field-effect-transistors were controlled using the Si substrate as a back-gate. The electronic measurements were performed using a Keithley 4200 semiconductor characterization system under ambient conditions. Scanning electron microscopy (SEM) studies were carried out using a LEO 1560. Due to the simultaneous growth of a mixture of metallic and semiconducting SWCNTs, the initial on/off ratio of the parallel SWCNT-FET is only between 2 and 4. This correlates roughly with the statistically expected ratio of 1/3 metallic SWCNTs and 2/3 semiconducting tubes, if no particular chirality is preferred during the growth and all tubes conduct equally well. To increase the on/off ratio we selectively burn the metallic SWCNTs using the method proposed by Collins et al.7 Since the as-grown semiconducting SWCNTs show p-type characteristics in air, the metallic tubes can be burned if the semiconducting ones are switched off by a positive gate voltage. A back-gate voltage of +20 V was applied before burning the SWCNTs with short (1 ms) bias pulses of increasing amplitude from 2 to 9 V. A gate voltage dependent transistor measurement was performed after every voltage pulse, as shown in Figure 3. The results after burn pulses of 2 and 3 V have been omitted for clarity, since they do not differ considerably from the measurement prior to the application of the voltage pulses. It can be clearly seen that the on/off ratio increases with increasing pulse amplitude. The results from devices with different gate lengths are presented in Figure 4. Figure 4a shows the decrease of the on-current with increasing pulse amplitude, and Figure 4b gives the evaluated on/off ratio at an applied drain-source voltage, Vds, of 1 V. For gate lengths between 90 and 230 nm, a pulse amplitude of at least 4 V is necessary to increase the on/off ratio. Ideally, if only the metallic SWCNTs are eliminated, the on-current should decreases to a level defined by the semiconducting SWCNTs and the on/off ratio should reach 104 to 106, as observed for individual semiconducting SWCNTs. Unfortunately, a certain 832
Figure 3. Logarithmic Id vs Vg plot of a parallel SWCNT transistor measured after application of the burn pulses shown on the righthand side (Vds ) 1 V). The curve labeled 0 V shows the behavior prior to burning.
Figure 4. Development of the on-current (a) and the on/off ratio (b) with increasing burn pulses of transistors with different gate lengths. During the burn pulse a gate voltage Vg of +20 V was applied to deplete the semiconducting SWCNTs and to preferentially eliminate the metallic SWCNTs. The Id vs Vg measurements that yielded these results were performed with Vds ) 1 V.
number of semiconducting SWCNTs and probably most of the ambipolar SWCNTs are burned through this process. Thus, there is a tradeoff between maximum on-current and on/off ratio. Nevertheless, Figure 4 demonstrates that oncurrents of up to 1 mA at Vds ) 1 V can be achieved with an on/off ratio of about 500 for a channel width of 200 µm. These results already show that simple parallel SWCNT devices are superior to organic FETs.8 Comparing the results for different gate lengths it can be seen that devices with a shorter gate length show a much Nano Lett., Vol. 4, No. 5, 2004
Figure 5. Dependence of the initial on and off-currents on the gate length (gap between source and drain metallization). The oncurrent was measured at Vg ) -20 V and the off-current at Vg ) +20 V, (Vds ) 1 V).
Figure 7. An electromotor and a LED can be switched on and off by changing the gate voltage of the high-current nanotube transistor.
Figure 6. The density of the SWCNTs is critical for the performance of the parallel SWCNT transistors. Ideally, growth occurs without any bundle formation (a). Bundles (b) will complicate the selective burning of the metallic SWCNTs.
steeper decrease of the conductance with pulse amplitude. This can be attributed to the power dissipated by the length dependent resistance R(l) of the nanotubes and the bias field between source and drain. The dissipated power (P ) V2/ R(l)) favors the destruction of short tubes. At constant bias the electric field is enhanced in shorter tubes, leading to Nano Lett., Vol. 4, No. 5, 2004
Zener-type tunneling, involving tunneling between noncrossing subbands of the tube.9 This causes a higher current and, thereby, destruction of the SWCNTs. Furthermore, it is important to prevent the semiconducting SWCNTs from breakdown. This can occur if semiconducting SWCNTs with small band gaps, showing an ambipolar behavior, are turned on at high positive gate voltages or if the semiconducting SWCNTs are not sufficiently turned off due to charging effects caused by adsorbed water molecules.10 On the other hand, relatively short source-to-drain distances are desirable to achieve high conductance through the directly contacted SWCNTs and to obtain transistors that do not operate by percolation mechanisms.11 If the sourcedrain distance becomes too large, the conductance of the device will be dominated by the properties of the SWCNT network, such as tunneling and hopping between the SWCNTs, especially if the source-drain distance is larger than the length of the SWCNTs (∼1 µm).11 The on-currents of the devices before the burn procedure decrease approximately linearly with increasing gate length (Figure 5). This length dependence is related to the reduced number of SWCNTs that are properly contacted at both sides as the source and drain electrodes are moved further apart. In addition, some length dependence caused by scattering processes within the SWCNTs will contribute to the length dependence.12-13 In addition to the influence of the source-drain separation, the SWCNT density is crucial to the performance and the burn behavior. If the density of the SWCNTs is too high, bundles will inevitably form. It is much more difficult to burn a metallic SWCNTs in a bundle than to burn an isolated 833
metallic SWCNT, since the metallic SWCNTs within a bundle might be shielded by the surrounding SWCNTs (Figure 6a). It is also likely that by burning a metallic SWCNT in a bundle the adjacent semiconducting SWCNTs are destroyed by local overheating. The best performance can be expected for growth with almost no bundle formation but with a large number of SWCNTs, as shown in Figure 6b.4 The performance can also be significantly improved if the effective oxide thickness of the gate is reduced and changes to the design of the gate are made so that the semiconducting SWCNTs can be better turned off at lower gate voltages. SWCNT-based transistors that can deliver currents of the order of milliamperes combined with on/off ratios of more than 100 have been successfully fabricated. It has been demonstrated that those transistors can switch currents high enough to power light-emitting diodes or electromotors, as shown in Figure 7. These devices open up a new range of applications for SWCNTs in transistors where larger currents have to be switched. Devices of this kind are also ideal for sensors, since they are easy to fabricate and the SWCNTs can be chemically functionalized. Finally, it should be pointed out that further improvements of the performance of parallel SWCNT transistors should result from a directed and more regular deposition of predominantly semiconducting SWCNTs, e.g., after separation in solution14 or more selective growth conditions.15 Acknowledgment. The authors are grateful to W. Palmer for technical support, to T. Do¨rrmann for the Al2O3 ALD,
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and to B. Panzer for metal deposition. This work has been supported by the German Ministry of Science and Technology (BMBF) under Contract No. 13N8402. References (1) Avouris, Ph. Acc. Chem. Res. 2002, 35, 1026-1034. (2) Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Nature 2003, 424, 654-657. (3) Seidel, R.; Liebau, M.; Duesberg, G. S.; Kreupl, F.; Unger, E.; Graham, A. P.; Hoenlein, W.; Pompe, W. Nano Lett. 2003, 3, 965968. (4) Seidel, R.; Duesberg, G. S.; Unger, E.; Graham, A. P.; Liebau, M.; Kreupl, F. J. Phys. Chem. B 2004, 108, 1888-1893. (5) Murakami, Y.; Miyauchi, Y.; Chiashi, S.; Maruyama, S. Chem. Phys. Lett. 2003, 377, 49-54. (6) Mann, D.; Javey, A.; Kong, J.; Wang, Q.; Dai, H. Nano Lett. 2003, 3, 1541-1544. (7) Collins. P. G.; Arnold, M. S.; Avouris, Ph. Science 2001, 292, 706709. (8) Zhang, Y.; Petta, J. R.; Ambily, S.; Shen, Y.; Ralph, D. C.; Malliaras, G. G. AdV. Mater. 2003, 15, 1632-1635. (9) Anantram, M. P. Phys. ReV. B 2000, 62, R4837-4840. (10) Kim, W.; Javey, A.; Vermesh, O.; Wang, Q.; Li, Y.; Dai, H. Nano Lett. 2003, 3, 193-198. (11) Snow, E. S.; Novak, J. P.; Campbell, P. M.; Park, D. Appl. Phys. Lett. 2003, 82, 2145-2147. (12) Park, J.-Y.; Rosenblatt, S.; Yaish, Y.; Sazonova, V.; U ¨ stu¨nel, H.; Braig, S.; Arias, T. A.; Brouwer, P. W.; McEuen, P. L. preprint, cond-mat/0309641. (13) Yaish, Y.; Park, J.-Y.; Rosenblatt, S.; Sazonova, V.; Brink, M.; McEuen, P. L. preprint, cond-mat/0305108. (14) Krupke, R.; Hennrich, F.; Lohneysen, H. v.; Kappes, M. M. Science 2003, 301, 344. (15) Li, Y.; Mann, D.; Rolandi, M.; Kim, W.; Ural, A.; Hung, S.; Javey, A.; Cao, J.; Wang, D.; Yenilmez, E.; Wang, Q.; Gibbons, J. F.; Nishi, Y.; Dai, H. Nano. Lett. 2004, 4, 317-321.
NL049776E
Nano Lett., Vol. 4, No. 5, 2004
