High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a

Nov 22, 2016 - Revenant , C.; Benwadih , M.; Maret , M. Self-Organized Nanoclusters in Solution-Processed Mesoporous In–Ga–Zn–O Thin Films Chem...
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High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process M. Benwadih,*,† R. Coppard,† K. Bonrad,‡ A. Klyszcz,‡ and D. Vuillaume§ †

University Grenoble Alpes, CEA, F-38000 Grenoble, France Merck TU-Darmstadt Laboratories, 64287 Darmstadt, Germany § Institute for Electronics Microelectronics and Nanotechnology, University of Lille, CNRS, 59652 Villeneuve d’Ascq, France ‡

S Supporting Information *

ABSTRACT: Amorphous, sol−gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm2/(V s), as well as a mobility of 7 cm2/(V s) on solid substrate (Si/ SiO2) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol−gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates. KEYWORDS: IGZO, UV annealing, sol−gel, plastic substrate, semiconductors reported.6 The obtained electron mobilities are on a par with performances of transistors (on solid substrates) produced by conventional thermal anneal (10−20 cm2/(V s)).6 However, the procedure is relatively restrictive, especially with regard to its sensitivity to humidity. The annealing must be performed under argon.6 In addition, the annealing time required with this type of lamp is relatively long, around 90 min but it is nevertheless a step forward in the research on innovative annealing. UV annealing is a solution to be focused on, especially deep UV radiation, which breaks the metal alkoxide bonds and promotes the formation of metal−oxide−metal network.6−8 Here, we report on a new type of photonic annealing, using short-time light pulses generated in the UV range by a xenon lamp. Such pulsed radiation rapidly heats exposed materials. Unlike conventional technologies, which use hot plates or furnaces, the pulsed nature of this heating brings thin films to a high temperature (>800 °C) for a short time without thermal damage to their substrates (such as polymers).9 It is a very versatile system. Parameters such as pulse duration, power, frequency and number of flashes, can be tuned for process optimization. In this study, these parameters have been optimized to process low thermal budget sol−gel IGZO

1. INTRODUCTION Metal oxide semiconducting compounds have attracted considerable interest as the active layer for thin film transistors (TFTs) in large area displays because of their high electron mobility, good uniformity, and high transparency. Zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO) are representative of such metal oxide semiconductors compounds.1−3 In addition to their good electrical properties, the metal oxides may be prepared using various techniques. In most studies on these materials, they are deposited by physical deposition, either evaporation or sputtering. However, these techniques need high vacuum, are relatively expensive and difficult to implement. A more innovative technique is the solution-processed material approach, which is less expensive and allows a better control of the composition of the material, while having good homogeneity.4 In addition, solution processes facilitate deposition over large areas. Both the semiconductors and the dielectric layers of the transistors can be synthesized by the sol−gel route. In sol−gel processes, annealing at high temperatures (>450 °C) is needed to turn the gel film into an oxide compound through chemical reactions,5 which may be a drawback for devices on plastic substrates. To overcome this problem, the ultraviolet (UV) low temperature annealing process begins to give very satisfactory results. For example, functional transistors (with electron mobility of 7 cm2/(V s)) containing an IGZO layer annealed by continuous exposition to UV lamp have been © 2016 American Chemical Society

Received: August 10, 2016 Accepted: November 22, 2016 Published: November 22, 2016 34513

DOI: 10.1021/acsami.6b09990 ACS Appl. Mater. Interfaces 2016, 8, 34513−34519

Research Article

ACS Applied Materials & Interfaces

2.7. TGA/DSC Measurement. Thermogravimetric analysis (TGA/DSC) on the metal oxide solution to check the behavior of the Kapton in temperature (see Figure S3). TGA were performed on 40−45 mg of materials by using a Pegasus Netzsch thermal analysis instrument under air with a flow rate of 10 mL/min and a heating ramp rate of 10 °C/min from 25 to 500 °C. 2.8. Interferometric Profilometry. The surface roughness of the Kapton and Kapton/PI was measured with a WYKO NT8000 optical profiler (see Figure S4). 2.9. Fabrication of IGZO Transistors on Kapton. Polyimide substrates (PI) “DuPont Kapton” and derivatives from polyarylate are described in the literature.6,19,20 These plastic substrates have viscoelastic properties depending of the temperature, and if the annealing temperature is higher than the glass transition, Tg, the polymer becomes rubbery and nonusable. We used Kapton KJ from DuPont. We carried out a thermogravimetric analysis (TGA/DSC) to determine the behavior of Kapton with temperature and to identify maximum annealing conditions. A maximum of 350 °C during 1 h was determined (see Figure S3). The surface of Kapton is indeed very rough, and has many defaults with very large peak heights (typically 2 μm in height) and large areas (diameters larger than 5 μm). This feature makes this substrate not suitable for deposition of a thin (20 nm) IGZO films. The deposition of a smoothing polyimide layer PI2611 from “HD MicroSystems” covered the major defects and greatly reduced the rms roughness to 11 nm (see Figure S4). Source and drain electrodes (10 nm Ti/30 nm Au) were fabricated on Kapton and were patterned by optical lithography and lift-off technique defining channel length L = 20 μm and W = 10000 μm. IGZO films were deposited as previously for TFTs on solid substrate, followed by a hot-plate annealing (1 min) and pulsed UV light annealing. Vinyl ether polyperfluoroalkenyl (CYTOP), polystyrene (PS), and polyvinylphenol (PVP) were tested as gate dielectrics. Solutions of the three dielectrics were deposited by spin coating on top of the annealed IGZO layers and cured at 100 °C (15 min) to eliminate the solvents. To limit the occurrence of leakage current densities below 0.1 μA/cm2 (see Figure S6), we used a dielectric thickness of 400 nm. Finally, silver gate electrodes (70 nm) were deposited trough a shadow mask by evaporation. (Ti/Au)/organic dielectric/metal (Au) capacitors were also fabricated. Different devices were fabricated to study the electrical properties of the organic dielectrics. These devices have surface areas of S = 0.785 mm2. A 30 nm gold layer (Au) was deposited by physical vapor deposition (PVD) on a Kapton substrate (125 μm thick), the different polymers were deposited by spin coating on top of the gold electrode. All dielectric films were annealed at 60 °C during 5 min and then at 100 °C during 15 min. The layer thickness (same as for TFTs, 400 nm) was measured by a Dektak profilomètre. The dielectric characteristic were first analyzed for the different dielectric polymers by measuring the capacitance of the fabricated devices as a function of the oscillating voltage frequency between 20 Hz and 2 MHz. Measurement were performed with an Agilent E4980A LCR meter under an AC voltage level of 0.1 V. We have investigated two samples for each polymers. The dielectric constant ε εS were extracted using the definition of a plane capacitance is C = 0e r where ε0 is the permittivity of the vacuum taken at 8.85 × 10−12 F/m, C is the electrical capacitance, εr is the relative permittivity of the polymer, and S is the area of the capacitance and e: the polymer film thickness (400 nm).

TFTs on plastic substrate (Kapton) with a high electron mobility values (4.5 cm2/(V s)). This value is on a par with, or even slightly better than those reported for plastic IGZO fabricated by other techniques.6−14

2. EXPERIMENTAL SECTION 2.1. Fabrication of IGZO Transistors on Si/SiO2. We started with a n-type doped silicon substrate (ND ≈ 3 × 1017 cm−3) covered with a 100 nm thick, thermally grown, silicon dioxide (SiO2) layer. Source and drain electrodes (10 nm Ti/30 nm Au) were patterned by optical lithography and lift off technique. Channel length (L) and width (W) are L = 20 μm and W/L = 500. The substrates were cleaned by ultrasonication in acetone and propane-diol for 10 min each to obtain a clean and residue free surface. The substrates were dried and UV ozone treated for 5 min, which significantly improves the wetting of the sol−gel precursor formulation onto the substrate. The IGZO precursor solutions (from Merck KGaA) were prepared by dissolving organo-metallic zinc oxymates,15 indium oxymates,16 and gallium oxymates,17 in 2-methoxyethanol. The details of the chemical composition of these precursors are given in refs 15−17. The chemical composition ratio of IGZO precursor solution was In:Ga:Zn = 3:0.4:2 at a single layer concentration of 30 mg of precursor in a total of 1 g of solvent (2-methoxyethanol). This formulation was spin coated onto the substrate at 2000 rpm for 30s, which was subsequently placed onto a hot plate in air at temperatures in the range of 100 to 350 °C for 1 min to evaporate the solvent, and then submitted to UV annealing to form the metal-oxide layer. The typical IGZO layer was 5 nm. Several layers are successively deposited by the same method. The IGZO TFTs measured in this work have 4 layers with a total thickness of the IGZO film around 20 nm (measured from SEM on a cross-section, see Figure S7).18 2.2. Pulsed UV Light Annealing. We used a photonic annealing equipment “Sinteron 2000”, from XENON Company, to anneal the thin films of sol−gel IGZO. This technology of flash lamp can provide adjustable light pulses, giving energies between 500 and 2070 J for a pulse time between 200 μs and 2 ms. The principle of this technique is based on charging an electric capacitance with a continuous voltage (several kV), which is then discharged in the lamp containing xenon gas. This discharge can generate a high light intensity with wavelength ranging from UV to the near-infrared (see Figure S1). To check the good match between the UV lamp spectrum and the IGZO optical properties, we also deposited IGZO solution directly onto a quartz substrate to measure the optical properties of the IGZO film (see Figure S1). 2.3. Optical UV−vis Transmittance Spectra Analysis. IGZO films deposited on glass substrates were used for optical measurements. A baseline measurement, of the substrate transmittance was carried out using an ultraviolet−visible (UV−vis) spectrophotometer PerkinElmer LAMBDA 950. We analyzed the optical properties of the solution processed IGZO and IGZO films in the 250−1500 nm wavelength range (see Figure S2). 2.4. Electrical Measurements. Transistor characteristics were measured using an Agilent 4156 semiconductor parameter analyzer. The saturation field-effect mobility μ is commonly evaluated from the slope of the square root of the drain current against the gate voltage √(IDS−VG) and the threshold voltage Vth from the intercept of the extrapolated √(IDS−VG) plot with the horizontal, VG axis. 2.5. SEM Measurement. The microstructure of the IGZO on flat Si/SiO2 substrates was analyzed by field-effect scanning electron microscopy (FE-SEM) on a Hitachi 5500. 2.6. XPS Measurement. X-ray photoelectron spectroscopy (XPS) measurements were carried out to establish the chemical and local bonding configuration and structural details of the studied ternary oxides. XPS was performed on a Thermo Electron Scientific ESCALAB 250 spectrometer (the source Al Kα 1486.6 eV) at pressure of 4.5 × 10−10 Torr (UHV), XPS spectra were obtained immediately after film fabrication in order to minimize surface contamination.

3. IGZO TRANSISTORS ON SOLID SUBSTRATES First, the parameters of the photonic annealing were optimized on sol−gel IGZO TFTs fabricated on Si/SiO2 substrates (bottom gate, bottom contacts configuration, see details in the Experimental Section). Typical parameters for the TFTs are SiO2 thickness 100 nm, channel length L = 20 μm, and channel width W = 10 000 μm. IGZO films, with a thickness of 20 nm were deposited from metal-oxymates precursors (from Merck KGaA) according a sol−gel process described elsewhere15−17 and summarized in the Experimental Section. The films were 34514

DOI: 10.1021/acsami.6b09990 ACS Appl. Mater. Interfaces 2016, 8, 34513−34519

Research Article

ACS Applied Materials & Interfaces

electron microscope (SEM) and X-ray photoelectron spectroscopy (XPS) measurements on sol−gel IGZO films deposited on flat Si/SiO2 substrates (i.e., without source/drain electrodes) (see Experimental Section). It was shown that solution processed IGZO transistors with a high mobility of 8 cm2/(V s),4 having undergone a thermal annealing at 450 °C for 1 h, present a microstrutured IGZO film.21 SEM images revealed a dense network of pores (Figure 2a, and ref 21). These pores

preannealed on a hot plate in air at temperatures in the range 100 to 350 °C for 1 min in order to evaporate the solvent, and then submitted to UV annealing in order to form the metaloxide layer (see Experimental Section). Figure 1 shows the

Figure 1. (a) Transfer characteristic curves IDS−VG (channel length L = 20 μm, VDS = 20 V) for TFTs submitted to preannealing (hot plate, 1 min) at various temperatures and 50 UV pulses (200 μs) at 2000J (Inset: IDS−VG in linear scale). (b) Evolution of the average electron mobility (averaged on 8 TFTs).

typical IDS−VG curves in the saturation region of IGZO TFTs on Si/SiO2 substrate and the evolution of the corresponding measured electron mobility (see Experimental Section for details) for an UV photonic annealing of 50 pulses (pulse duration 200 μs) of 2000J, with different preannealing temperatures. The IGZO TFTs cured with a thermal preannealing step higher than 200 °C exhibit a clear transistor effect (Figure 1a), we clearly observe two current regions (“on” with current up to 10−2 A and “off” with current below 10−8 A) for positive and negative gate voltages, respectively. The TFTs having undergone a preanneal step at 325 and 350 °C have a mobility of 6.5 and 7 cm2/(V s) (Figure 1b). To obtain the same mobility (i.e., 7 cm2/(V s)), the hot-plate annealing process requires a temperature of 450 °C,4 which it is not compatible with plastic substrates. The TFTs preannealed at 300 °C have a mobility of 4 cm2/(V s), four times higher than sol−gel processed IGZO transistors only annealed on hot plate at the same temperature but for a longer time (1 h).4

Figure 2. SEM images of IGZO thin films annealed at (a) 450 °C/1 h, (b) 300 °C/1 min and with 50 UV pulses at 2000 J, and (c) preannealed only 300 °C/1 min.

come from the evaporation of the solvents and the selforganization of nanoclusters into the films as revealed elsewhere by GISAXS (grazing incidence small-angle X-ray scattering).21 For comparison, Figure 2b shows the SEM image, of IGZO film after the preannealing (300 °C/1 min) and the photonic annealing (50 UV 200 μs pulses at 2000J). The average diameter of the pores are distributed between 2 and 5 nm for both the 450 °C/1h and photonic (350 °C/1 min, 50 UV pulses) and the surface occupancies are 26−28% in both cases. On the contrary, a very small density of pores (about 2% of surface coverage) is observed for IZGO film having undergone only the preannealing step (Figure 2c).

4. IGZO FILMS: PHYSICOCHEMICAL CHARACTERIZATION To gain more insights and establish correlations between the electrical properties of the IGZO transistors and the physicochemical properties of the films, we did some scanning 34515

DOI: 10.1021/acsami.6b09990 ACS Appl. Mater. Interfaces 2016, 8, 34513−34519

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electron mobility is related to the IGZO stoichiometry (oxygen vacancy),6 these XPS results are consistent with the fact that both devices have almost the same mobility (8 cm2/V·s for IGZO 450 °C/1 h)4 and 4 cm2/V·s for the pulsed UV light annealed IGZO TFT (see Figure 1b) and that the device only preannealed at 300 °C/1 min, which contains more hydroxide and carbon-related species does not exhibit any transistor behavior.

These results are consistent with the fact that both the 450 °C/1 h annealed IGZO TFTs and 300 °C/1 min/50 UV flashes) have a high mobility (8 cm2/(V s) 4 and 4 cm2/(V s), Figure 1b), while no transistor behavior is observed with the preannealing step alone. To investigate the effect of the annealing process on chemical and structural changes in the films after annealing. XPS was used to analyze the metal−oxygen (M-O) bonding in IGZO films. Figure 3 shows the results of a deconvolution of the oxygen O 1s peaks of IGZO films to estimate the different forms of O2− ions in the films.

5. IGZO TRANSISTORS ON PLASTIC SUBSTRATE To take advantage of the low-thermal budget photoactivation of IGZO by pulsed UV light annealing, we fabricated IGZO TFTs on commercially available polyimide (DuPont Kapton KJ Polyimide Film) substrates. The UV flash anneal process optimized above on Si/SiO2 substrate was transferred to sol− gel IGZO TFTs made on plastic substrates. The IGZO TFTs on Kapton have bottom contacts, top gate configuration as described in the Experimental Section. Before the IGZO deposition, the surface of Kapton is planarized using a smoothing polyimide layer (see Figure S4). IGZO films were deposited from solution and annealed as previously described for Si/SiO2 substrates, since Kapton can sustain annealing temperatures up to 350 °C (see Figure S3).22 Then, on top of annealed IGZO films, we deposited solution processed gate dielectrics, which can be printed. Several polymers, such as vinyl ether polyperfluoroalkenyl (CYTOP), polystyrene (PS) and polyvinylphenol (PVP), were tested to determine the most suitable to be used with the solution IGZO annealed by pulsed UV light. It is known that the electrical properties of TFTs, such as mobility, threshold voltage, and the subthreshold slope, do not only depend on the nature of the organic semiconductor but also on chemical and physical properties of the organic gate insulator.23 We started with a set of measurements to define the best gate dielectric. Figure 4a shows the values of the relative dielectric permittivity as a function of the frequency obtained from capacitance measurements on metal (Ti/Au)/organic dielectric/metal (Au) capacitors (see Experimental Section). CYTOP and polystyrene films have a stable frequency behavior and quite similar relative permittivity values (εr ≈ 2.2), while PVP shows a permittivity decreasing with frequency. The permittivity of the bilayer PS/PVP remains stable as frequency changes, and is approximately εr ≈ 3. For all these gate dielectrics, the leakage current densities are lower than 0.1 μA/ cm2 (Figure S6) in the gate voltage of interest, that is, Ioff of the IZGO transistor is lowest (Figure 4b). Figure 4b shows the characteristic curves IDS−VG of the IGZO transistors on Kapton with the different gate insulators and processed with a thermal annealing of IGZO (hot plate) step only, at 350 °C for 1 h. These curves are significantly influenced by the nature of the insulating layer. The presence of dipoles at the interface between the dielectric and the IGZO is critical and can induce differences in the mobility depending on the nature of the organic dielectrics.24 Polystyrene (PS), an insulating polymer with the less reactive chemical structure, provides low off-current Ioff (∼10−10 A) and a subthreshold slope (1.7 V/decade) better than those of PVP and CYTOP (3.2 and 2.9 V/decade, respectively). In the case of PVP, the presence of hydroxyl groups and adsorbed water molecules can create traps, thereby degrading the subthreshold slope of the IDS−VG curves. Inserting a thin layer of 50 nm-thick polystyrene (PS) between the IGZO and PVP layers improves the interface between the semiconductor

Figure 3. XPS spectra of oxygen 1s for IGZO films annealed at (a) 300 °C/1 min and (b) 300 °C during 1 min and 50 UV pulses (200 μs) at 2000 J.

The O 1s peaks were fitted by three nearly Gaussian curves attributed to (i) a peak centered at 530.2 eV, which represent the O2− ion bonded with metal ions (In, Ga, and Zn) with oxygen vacancies (M−O−M); (ii) a peak at 531.5 eV attributed to bulk and surface metal hydroxide (M−OH) and containing nonstoichiometric oxide species; and finally, (iii) the weakly bound (M−OR) species such as surface adsorbed carbon species, at 532.5 eV.11 The main feature is that the hydroxide M−OH and M−OR peaks still have a significant contribution after the preannealing at 300 °C/1 min (Figure 3a), while they are strongly reduced with the pulsed UV light annealing (Figure 3b). Note that the XPS spectrum shown in Figure 3b is similar to the one for a solution processed IGZO film classically annealing at 450 °C for 1 h (see Figure 2c in ref 4). For instance, the ratios of the peak maximum amplitudes [M−O]/ [M−OH] and [M−O]/[M−OR] are ∼2.7 and ∼3.3 for IGZO 450 °C/1 h4 and ∼2.8 and ∼3.4 in the present case. Since the 34516

DOI: 10.1021/acsami.6b09990 ACS Appl. Mater. Interfaces 2016, 8, 34513−34519

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Table 1. Electrical Parameters of IGZO Transistors Fabricated on Plastic Substrate: Electron Mobility (μ), Threshold Voltage (Vth), Subthreshold Slope (SS), and off Current (Ioff)

PS 350 °C (1 h) PVP 350 °C (1 h) CYTOP 350 °C (1 h) PS/PVP 350 °C (1 h) PS/PVP 350 °C (1 min) + UV flash PS/PVP 300 °C (1 min) + UV flash

μ (cm2/(V s))

Vth (V)

SS (V/ decade)

Ioff (A)

1.9 2.7 0.1 3.8 4.5

6 10 8 5 4

1.7 3.2 2.9 1.1 1.2

2 × 10−10 6 × 10−8 2 × 10−8 2 × 10−10 ∼10−9

7

2.3

∼10−10

1

We therefore tested UV photonic annealing with this optimized gate dielectric configuration (PVP/PS) with various preannealing steps. Figure 5 shows the measured IDS−VG curves, and the extracted transistor parameters (electron mobility, threshold voltage, subthreshold slope) are given in Table 1. An electron mobility around 4.5 cm2/(V s) is obtained in the case of a preannealing at 350 °C for 1 min, followed by 50 flashes (200 μs) at 2000 J. This result is slightly higher than the one obtained for conventional “hot plate” thermal annealing (Table 1) for 1 h at the same temperature. The threshold voltage and the subthreshold slope are comparable in both cases. The combination of the preannealing process step and UV flash annealing step also provides a marked improvement of the mobility (1 cm2/(V s)) of the transistors preannealed at 300 °C, while a purely “hot plate” thermal annealing at 300 °C/1 h is insufficient to obtain a transistor effect (not shown). However, decreasing the preannealing step below 300 °C does not allow us to obtain a transistor behavior (Figure 5, see preannealing at 250 °C). Note that we have observed a larger dispersion of the mobility for the TFTs on Kapton, compared to those on solid substrates. For 16 samples (preanneal 350 °C/1 min + 50 UV flashes) the mobility is in the range 1 to 4.5 cm2/(V s). Out of these 16 measured samples, 10 have a mobility higher than 2 cm2/(V s) and 2 showed the maximum mobility of 4.5 cm2/(V s) (see Figure S5). It is likely that this larger dispersion is due to the more important roughness of the smoothed Kapton substrate (about 11 nm, see Figure S4), compare to the very flat SiO2 surface (rms roughness of about 0.1 nm), which makes more difficult obtaining a homogeneous IGZO film. Further improvement of the surface treatment of Kapton will probably allow reaching higher mobility or a lower dispersion of the IGZO TFTs properties. These results are comparable or even slightly better than those reported in the literature for various amorphous oxide semiconductor transistors (IGZO, ZnO, In2O3, etc.) on plastic substrates, as well as on solid substrates with vacuumdeposited inorganic high k gate dielectric.6−14,18,19,25−28

Figure 4. (a) Relative dielectric permittivity of gate insulators PS, CYTOP, PVP, PS/PVP. (b) IDS−VG curves (channel length L = 20 μm, VDS= 20 V) of IGZO TFTs on Kapton substrate with various dielectrics.

and the organic dielectric, and therefore allows to obtain transfer curves IDS−VG with a smaller threshold voltage (5 V, while values >12.5 V, Figure 5, are observed for lower

Figure 5. Characteristic curves IDS−VG of IGZO TFTs (channel length L = 20 μm, VDS= 20 V) on plastic substrate with PS/PVP gate dielectric and the photonic annealing.

6. CONCLUSION In conclusion, using the combination of a short time (1 min) thermal preannealing step at 350 °C and a pulsed UV light anneal, we have developed high-performance, solution-process IGZO transistors on both a solid substrate (Si/SiO2) with an electron mobility of 7 cm2/(V s), and on a plastic substrate, incorporating a printable gate dielectric, with an electron mobility of 4.5 cm2/(V s). These results represent a real progress for an integration IGZO transistors on plastic

preannealing temperatures), the lowest subthreshold slope (1.1 V/decade), and a low off-current Ioff (2 × 10−10 A). The main properties of IGZO transistors fabricated on a plastic substrate with these different gate dielectrics are summarized in Table 1: the highest mobility (3.8 cm2/(V s)) is obtained (for a thermal annealing at 350 °C during 1 h) for transistors with a bilayer dielectric PS/PVP, thanks to the good quality of the PS/ IGZO interface. 34517

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(7) Kang, C. M.; Kim, H.; Oh, Y. W.; Baek, K. H.; Do, L. M. HighPerformance, Solution-Processed Indium-Oxide TFTs Using Rapid Flash Lamp Annealing. IEEE Electron Device Lett. 2016, 37, 595−598. (8) Kim, D. W.; Park, J.; Hwang, J.; Kim, H. D.; Ryu, J. H.; Lee, K. B.; Baek, K. H.; Do, L. M.; Choi, J. S. Rapid Curing of Solution-Processed Zinc Oxide Films by Pulse-Light Annealing for Thin-Film Transistor Applications. Electron. Mater. Lett. 2015, 11, 82−87. (9) Kim, H. S.; Dhage, S. R.; Shim, D. E.; Hahn, H. T. Intense Pulsed Light Sintering of Copper Nanoink for Printed Electronics. Appl. Phys. A: Mater. Sci. Process. 2009, 97, 791−798. (10) Kim, K. M.; Kim, C. W.; Heo, J. S.; Na, H.; Lee, J. E.; Park, C. B.; Bae, J. U.; Kim, C. D.; Jun, M.; Hwang, Y. K.; Meyers, S. T.; Grenville, A.; Keszler, D. A. Competitive Device Performance of LowTemperature and All-Solution-Processed Metal-Oxide Thin-Film Transistors. Appl. Phys. Lett. 2011, 99, 242109. (11) Kim, M. G.; Kanatzidis, M. G.; Facchetti, A.; Marks, T. J. LowTemperature Fabrication of High-Performance Metal Oxide Thin-Film Electronics Via Combustion Processing. Nat. Mater. 2011, 10, 382− 388. (12) Meyers, S. T.; Anderson, J. T.; Hung, C. M.; Thompson, J.; Wager, J. F.; Keszler, D. A. Aqueous Inorganic Inks for LowTemperature Fabrication of ZnO TFTs. J. Am. Chem. Soc. 2008, 130, 17603−17609. (13) Jeong, S.; Lee, J. Y.; Lee, S. S.; Oh, S. W.; Lee, H. H.; Seo, Y. H.; Ryu, B. H.; Choi, Y. Chemically Improved High Performance Printed Indium Gallium Zinc Oxide Thin-Film Transistors. J. Mater. Chem. 2011, 21, 17066−17070. (14) Su, B. Y.; Chu, S. Y.; Juang, Y. D.; Chen, H. C, HighPerformance Low-Temperature Solution-Processed InGaZnO ThinFilm Transistors via Ultraviolet-Ozone Photo-Annealing. Appl. Phys. Lett. 2013, 102, 192101−192104. (15) Schneider, J. J.; Hoffmann, R. C.; Engstler, J.; Dilfer, S.; Klyszcz, A.; Erdem, E.; Jakes, P.; Eichel, R. A. Zinc Oxide Derived from Single Source Precursor Chemistry under Chimie Douce Conditions: Formation Pathway, Defect Chemistry and Possible Applications in Thin Film Printing. J. Mater. Chem. 2009, 19, 1449−1457. (16) Kuegler, R.; Schneider, J. J.; Hoffmann, R. (Merck). Organometallic Zinc Compound for Preparing Zinc Oxide Films. Patent No. WO/2009/010142, 2009. (17) Hoffmann, R. C.; Kaloumenos, M.; Heinschke, S.; Erdem, E.; Jakes, P.; Eichel, R. A.; Schneider, J. J. Molecular Precursor Derived and Solution Processed Indium−Zinc Oxide as a Semiconductor in a Field-Effect Transistor Device. Towards an Improved Understanding of Semiconductor Film Composition. J. Mater. Chem. C 2013, 1, 2577−2584. (18) Walker, D. E.; Major, M.; Baghaie Yazdi, M.; Klyszcz, A.; Haeming, M.; Bonrad, K.; Melzer, C.; Donner, W.; von Seggern, H. High Mobility Indium Zinc Oxide Thin Film Field-Effect Transistors by Semiconductor Layer Engineering. ACS Appl. Mater. Interfaces 2012, 4, 6835−6841. (19) Jeong, S.; Moon, J. Low-Temperature, Solution-Processed Metal Oxide Thin Film Transistors. J. Mater. Chem. 2012, 22, 1243−1250. (20) Chien, C. W.; Wu, C. H.; Tsai, Y. T.; Kung, Y. C.; Lin, C. Y.; Hsu, P. C.; Hsieh, H. H.; Wu, C. C.; Yeh, Y. H.; Leu, C. M.; Lee, T. M. High-Performance Flexible a-IGZO TFTs Adopting Stacked Electrodes and Transparent Polyimide-Based Nanocomposite Substrate. IEEE Trans. Electron Devices 2011, 58, 1440−1446. (21) Revenant, C.; Benwadih, M.; Maret, M. Self-Organized Nanoclusters in Solution-Processed Mesoporous In−Ga−Zn−O Thin Films. Chem. Commun. 2015, 51, 1218−1221. (22) Jang, J.; Choi, M. H.; Kim, B. S.; Lee, W. G.; Seok, M. J.; Ryu, D. S. Robust TFT Backplane for Flexible AMOLED. Dig. Tech. Pap. - Soc. Inf. Disp. Int. Symp. 2012, 43, 260−263. (23) Liu, C.; Xu, Y.; Li, Y.; Scheideler, W.; Minari, T. Critical Impact of Gate Dielectric Interfaces on the Contact Resistance of HighPerformance Organic Field-Effect Transistors. J. Phys. Chem. C 2013, 117, 12337−12345. (24) Boudinet, D.; Benwadih, M.; Altazin, S.; Verilhac, J. M.; DeVito, E.; Serbutoviez, C.; Horowitz, G.; Facchetti, A. Influence of Substrate

substrate. This performance is all the more interesting that the deposition on our substrate is still rough, and there is room to improve these interfaces. We note that a combination of this flash photonic annealing and a vacuum pumping which can help evaporation of solvents and organic precursor molecules need for IGZO deposition as well as all other volatile species is likely to allow decreasing the temperature (or even suppressing) of the thermal preannealing step. This work is under optimization and will be reported elsewhere. By pursuing the development of plastic electronics based on IGZO, the performance improvements, especially in terms of power and speed, will reinforce its potential in various applications, such as sensor control electronics (pressure, temperature, ...), plastic display systems, or radio frequency identification (RFID).



ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b09990. Spectral emission of the UV, UV−vis absorption of IGZO film, thermal stability of Kapton, surface morphology of Kapton and smoothing, histograms of electron mobilities, electrical characteristics of Ti-Au/ polymer/Au capacitors, and SEM of IGZO thin films (PDF)



AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. ORCID

M. Benwadih: 0000-0002-9550-5356 Notes

The authors declare no competing financial interest.



ACKNOWLEDGMENTS We thank Dr A. Aliane for helpful discussions about UV annealing techniques and Tournon Laurent. Dr Gareth P. Keeley is also acknowledged for proof-reading the manuscript.



REFERENCES

(1) Nomura, K.; Ohta, H.; Takagi, A.; Kamiya, T.; Hirano, M.; Hosono, H. Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors. Nature 2004, 432, 488−492. (2) Hoffman, R. L.; Norris, B. J.; Wager, J. F. ZnO-Based Transparent Thin-Film Transistors. Appl. Phys. Lett. 2003, 82, 733− 735. (3) Jeong, J. K.; Jeong, J. H.; Yang, H. W.; Park, J. S.; Mo, Y. G.; Kim, H. D. High Performance Thin Film Transistors with Cosputtered Amorphous Indium Gallium Zinc Oxide Channel. Appl. Phys. Lett. 2007, 91, 113505. (4) Benwadih, M.; Chroboczek, J. A.; Ghibaudo, G.; Coppard, R.; Vuillaume, D. Impact of Dopant Species on the Interfacial Trap Density and Mobility in Amorphous In-X-Zn-O Solution-Processed Thin-Film Transistors. J. Appl. Phys. 2014, 115, 214501. (5) Jeon, H.; Song, J.; Na, S.; Moon, M.; Lim, J.; Joo, J.; Jung, D.; Kim, H.; Noh, J.; Lee, H. J. A Study on the Microstructural and Chemical Evolution of In−Ga−Zn−O Sol−Gel Films and the Effects on the Electrical Properties. Thin Solid Films 2013, 540, 31−35. (6) Kim, Y. H.; Heo, J. S.; Kim, T. H.; Park, S.; Yoon, M. H.; Kim, J.; Oh, M. S.; Yi, G. R.; Noh, Y. Y.; Park, S. K. Flexible Metal-Oxide Devices Made by Room-Temperature Photochemical Activation of Sol−Gel Films. Nature 2012, 489, 128−132. 34518

DOI: 10.1021/acsami.6b09990 ACS Appl. Mater. Interfaces 2016, 8, 34513−34519

Research Article

ACS Applied Materials & Interfaces Surface Chemistry on the Performance of Top-Gate Organic ThinFilm Transistors. J. Am. Chem. Soc. 2011, 133, 9968−9971. (25) Banger, K. K.; Yamashita, Y.; Mori, K.; Peterson, R. L.; Leedham, T.; Rickard, J.; Sirringhaus, H. Low-Temperature, HighPerformance Solution-Processed Metal Oxide Thin-Film Transistors Formed by a ‘Sol−Gel on Chip’ Process. Nat. Mater. 2011, 10, 45−50. (26) Cobb, B.; Rodriguez, F. G.; Maas, J.; Ellis, T.; van der Steen, J. L.; Myny, K.; Smout, S.; Vicca, P.; Bhoolokam, A.; Rockelé, M.; Steudel, S.; Heremans, P.; Marinkovic, M.; Pham, D. V.; Hoppe, A.; Steiger, J.; Anselman, R.; Gelinck, G. Flexible Low Temperature Solution Processed Oxide Semiconductor TFT Backplanes for Use in AMOLED Displays. Dig. Tech. Pap. - Soc. Inf. Disp. Int. Symp. 2014, 45, 161−163. (27) Rockelé, M.; Pham, D. V.; Hoppe, A.; Steiger, J.; Botnaras, S.; Nag, M.; Steudel, S.; Myny, K.; Schols, S.; Müller, R.; van der Putten, B.; Genoe, J.; Heremans, P. Low-Temperature and Scalable Complementary Thin-Film Technology Based on Solution-Processed Metal Oxide n-TFTs and Pentacene p-TFTs. Org. Electron. 2011, 12, 1909−1913. (28) Xu, X.; Cui, Q.; Jin, Y.; Guo, X. Low-Voltage Zinc Oxide ThinFilm Transistors with Solution-Processed Channel and Dielectric Layers below 150 °C. Appl. Phys. Lett. 2012, 101, 222114.

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DOI: 10.1021/acsami.6b09990 ACS Appl. Mater. Interfaces 2016, 8, 34513−34519