High-Performance Complementary Transistors and Medium-Scale

Mar 23, 2017 - However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stabilit...
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High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films Yingjun Yang, Li Ding, Jie Han, Zhiyong Zhang,* and Lian-Mao Peng* Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China S Supporting Information *

ABSTRACT: Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs. KEYWORDS: carbon nanotube, complementary metal-oxide semiconductor, field-effect transistors, medium-scale integrated circuits, network film

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and this has hindered the development of CMOS ICs based on CNT films. Recently, many methods have been developed for the fabrication of n-FETs, mainly relying on the doping of channels using chemical dopants or coverage with an insulator such as Al2O3 or Si3N4,16,18−27 similar to the reported work based on a single CNT.28 However, all such n-FETs have suffered from poor performance and stability, high process complexity, or incompatibility with a top-gate structure. In addition, ambipolar CMOS technology has been developed in which all FETs are the same and can act as either n-type or ptype devices.29 However, ambipolar CMOS technology is not true CMOS technology because both n-type and p-type FET performances are compromised.29 As a result, such CMOS FETs have only been used to realize fundamental logic gates or SRAM,16,18,19,21−26 which are of a much smaller scale than the pure p-FET ICs that can be fabricated on CNT network films. It is well-known that only relatively large-scale ICs of high

ecause of their beneficial electrical and mechanical properties, carbon nanotube (CNT) network thin films are considered to be promising channel materials for the fabrication of field-effect transistors (FETs) and integrated circuits (ICs), especially for certain special applications, such as flexible, transparent, and transient electronics.1−4 The development of advanced techniques for material and device fabrication has enabled the batch fabrication of FETs with high uniformity and high yield based on high-quality CNT thin films of high semiconducting purity,5−8 and many kinds of ICs have been demonstrated, including fundamental logic gates, ring oscillators, D latches, D flip-flops, and several medium-scale ICs such as 4-bit full adders and 4-bit decoders.9−16 However, most of these ICs have been designed based solely on p-type FETs.9−15 As is well-known, complementary metal-oxide semiconductor (CMOS) technology, which comprises both p- and n-type FETs working complementarily, is the most common circuit paradigm for modern ICs because of its low static power dissipation and high noise margin, and thus, it is also the preferred circuit technology for CNT film electronics.17 However, the fabrication of stable and high-performance nFETs based on CNT network films is famously challenging, © 2017 American Chemical Society

Received: February 8, 2017 Accepted: March 23, 2017 Published: March 23, 2017 4124

DOI: 10.1021/acsnano.7b00861 ACS Nano 2017, 11, 4124−4132

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Figure 1. Characteristics of complementary FETs based on CNT films. (a) Schematic illustration of CNT-network-film-based CMOS FETs. (b) Transfer characteristics of p-FETs (blue curves) and n-FETs (red curves) with a gate length and channel width of 5 and 25 μm, respectively. The solid lines represent |VDS| = 0.1 V, and the dotted lines represent |VDS| = 1.0 V. (c) Output characteristics of the p-FET (blue lines) and n-FET (red lines). From bottom to top, |VGS| ranges from 0 to 2 V with a step size of 0.05 V. (d) Band diagrams of a p-FET and an n-FET in the on and off states. Statistical distributions of the (e) peak transconductance gm and (f) threshold voltage VTH for CMOS FETs with a gate length and channel width of 5 and 25 μm, respectively, as measured at |VDS| = 2 V.

CMOS FETs on CNT films still have not yet been realized using a doping-free process. In this work, we developed a doping-free CMOS fabrication process based on solution-derived CNT network films, in which the polarity of the FETs was determined by using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices as well as high yields and good performance uniformity. Several types of ICs, including typical logic gates, sequential circuits such as D latches and flip-flops, and even a 4-bit full adder consisting of 132 transistors, were constructed using CNT-film-based CMOS FETs, and all produced rail-to-rail outputs by virtue of the high noise margin of CMOS circuits. High yields of up to 100% were achieved even for mediumscale ICs, indicating that this CMOS technology has the potential to advance the development of CNT-network-filmbased ICs to a large scale.

complexity are suitable for actual applications, even in flexible or transparent electronics. Therefore, a reliable CMOS technology is urgently required for the further development of CNT-network-film-based electronics. The polarity of FETs based on individual CNTs can be controlled by manipulating the injection of carriers at the source/drain contacts; that is, Pd and Sc contacts can be used to realize p-FETs and n-FETs, respectively, with highperformance symmetry.30 A doping-free CMOS technology based on individual CNTs has been developed, which has enabled the fabrication of high-performance CMOS FETs and ICs based on individual CNTs.31−34 However, this doping-free CMOS technology is considered unsuitable for use on CNT network films, whose transport properties are mainly determined by the junctions between CNTs rather than by contact characteristics. Recently, n-type FETs based on CNT network films have been demonstrated by using low-workfunction metals such as yttrium as contacts.35,36 However, 4125

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Figure 2. Explorations of the scaling behavior of CNT-network-film-based CMOS FETs. (a) Transfer characteristics at different |VDS| values (0.1 or 1 V) and (b) output properties of typical CNT CMOS FETs with a gate length of 1 μm. From bottom to top, VGS varies from −0.80 to −2 V for the p-FET and from 0.2 to 2 V for the n-FET with a step size of 0.2 V. (c,d) Statistical on-current densities and (e,f) on/off ratios for p-FETs and n-FETs with gate lengths of 1, 2, and 5 μm under |VDS| = 1 V.

tional CNT network film are based on a percolation mechanism and are mainly determined by the inter-CNT junctions rather than the CNT/metal contacts. The situation changes when a CNT film with a high semiconducting purity (>99.9%) is used for FET fabrication, as in this work. First, short-channel FETs with a high on/off current ratio can be constructed as multiple inter-CNT junctions are no longer necessary. Second, almost all of the CNTs in contact with the source and drain are semiconducting, meaning that the contacts play a more important role than they do in conventional CNT-networkfilm-based devices. Third, the inter-CNT junctions in the channel are mainly of the semiconductor−semiconductor (S− S) type, meaning that the channel resistance is further reduced because the resistance of an S−M junction is much larger than that of an S−S or M−M junction.37 Therefore, in our CNTnetwork-film-based FETs with short channels and a high semiconducting purity, the source/drain contacts begin to dominate the transport properties of the devices, and thus, in principle, we can control the polarity of our CNT-network-filmbased FETs with a relatively short channel by choosing metals with different work functions to determine whether electrons or holes are injected into the channels, as shown in the band diagram in Figure 1d. Since Pd can inject holes in a barrier-free manner into the valence band of the CNT film, a Pd-contacted

RESULTS AND DISCUSSION Complementary FETs with a self-aligned top-gate structure (Figure 1a) were fabricated based on solution-processed CNT network films using the process illustrated in Figure S1a. The scanning electron microscope (SEM) image of a typical fabricated CNT FET is shown in Figure S1b. These devices exhibited typical CMOS FET characteristics, as shown in Figure 1b,c. The polarity of our FETs was controlled by the selection of the source/drain contacts; that is, Pd and Sc contacts were adopted to realize p-FETs and n-FETs, respectively, based on the same CNT film. This type of doping-free CMOS technology has previously been demonstrated based on individual CNTs30−34 but, in principle, is not suitable for conventional CNT network films without semiconducting selectivity.12,14,15 In the conventional CNT-network-film-based FETs developed by Rogers et al., a channel must be much longer than its component CNTs to avoid the formation of metallic CNT pathways between the drain and source;12 that is, multiple inter-CNT junctions are required in the channel of a FET with a high on/off ratio. In addition, approximately 1/3 of the CNTs in contact with metal (source or drain) are metallic CNTs, which results in reduced contact resistances. Therefore, the transport properties of a conven4126

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Figure 3. Fabrication and characterization of fundamental logic gates based on CNT-film-based CMOS FETs. (a) Circuit diagram and microphotograph of an inverter. (b) Voltage transfer characteristic (VTC) curves of a fabricated inverter for VDD values varying from 2 to 0.1 V. (c) VTC curves (blue lines) and their mirrors (red lines) at VDD = 1 and 2 V. The shaded “eye” area represents the noise margin of the inverter. (d) VIN-dependent voltage gains of an inverter at VDD = 0.2, 1, and 2 V. (e) Circuit diagrams of CNT CMOS logic gates of the NAND, NOR, and XOR types. (f) Microphotographs and (g) output characteristics of the fabricated CNT CMOS logic gates, including NAND, AND, NOR, OR, XOR, and XNOR gates, under VDD = 2 V.

1c; these findings illustrate the excellent symmetry between the n- and p-FETs fabricated using the proposed CNT-film-based CMOS technology. Ambipolar CMOS technology also produces symmetric n- and p-type branches, but the performances of both n- and p-FETs are compromised because of the existence of Schottky barriers at the contacts.29 Compared with previously reported CNT-film-based CMOS FETs,12,16,18,19,21−27 our CMOS FETs simultaneously exhibit higher symmetry and high performance (high on-currents), and thus, they can be considered to be true CMOS devices. The symmetry between the n- and p-FETs reported in this work is further demonstrated by the statistical distributions of the key parameters among the fabricated devices. Figure 1e,f shows the statistical distributions of the peak transconductance (gm) and threshold voltage (VTH) for 194 p-FETs and 190 nFETs with the same gate length and channel width. The statistical results show that the p-FETs exhibit gm values of 6.14 ± 0.40 μS/μm, similar to the gm distribution of the n-FETs,

device acts as a high-performance p-type FET. Similarly, since Sc can inject electrons in a barrier-free manner into the conduction band of the CNT film, a Sc-contacted device can act as an excellent n-type FET. Therefore, we have demonstrated a doping-free CMOS technology based on CNT network films. Because of the highly transparent barriers for carriers at the contacts, the fabricated CMOS FETs can act as high-performance FETs of both the pand n-types with highly symmetrical main properties, as shown by their transfer (Figure 1b) and output (Figure 1c) characteristics. Both p-FETs and n-FETs present on/off current ratios of higher than 104 and small subthreshold slope swings (90 mV/dec for p-FET and 115 mV/dec for n-FET) comparable to those of the best-reported FETs based on CNT network films.19,26 In particular, the output curves for a pFET within its operating range (VDD = −2 V) almost perfectly mirror the output curves of its n-type counterpart within the corresponding operating range (VDD = 2 V), as shown in Figure 4127

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Figure 4. Fabrication and characterization of CNT-CMOS-based MUX2_1, D latch, and T flip-flop circuits. (a) Microphotograph and circuit diagram of a fabricated MUX2_1 circuit and (b) its functional measurements under VDD = 2 V. A and B are input signals with frequencies of 100 and 50 Hz, respectively, and S controls whether A or B is chosen as the output signal. (c) Microphotograph of a fabricated CNT CMOS D latch and (d) its functional measurements under VDD = 2 V. D is the input signal, with a frequency of 100 Hz, and clk is the clock pulse, with a frequency of 40 Hz. Q and Q̅ are the output signals. (e) Microphotograph and circuit diagram of a fabricated T flip-flop and (f) its functional measurements under VDD = 2 V. VIN is the input signal, with a frequency of 100 Hz.

which is characterized by values of 5.24 ± 1.15 μS/μm. The distribution of on−off ratio and subthreshold swing of the FETs are shown in Figure S2a,b, which show that the performance variation of n-FETs is larger than that of pFETs. The large performance variation in n-FETs is likely originated from the unstable Sc contacts in air and can be suppressed through effective passivation.16,38 The threshold voltages VTH are −0.87 ± 0.04 V for the p-FETs and 0.60 ± 0.21 V for the n-FETs. Both the p- and n-FETs are enhanced FETs, and the VTH distribution ranges of the two types of FETs are completely separated. Therefore, the p-FETs and n-FETs in a CMOS IC will not be open simultaneously; this behavior contributes to lower power dissipation in CMOS ICs because no direct path exists between the supply voltage and the ground under steady-state operating conditions. Furthermore, the hysteresis of IDS−VGS is typically smaller than 0.1 V for pand n-FETs, as shown in Figure S1d,e. These uniform CMOS FETs, with their high performance, good symmetry, and small hysteresis, should serve as excellent building blocks for ICs based on CNT network films. As is well-known, scaling effects are the main motivations driving the development of CMOS FETs, and the scaling down of the gate length can result in improved performance and decreased device areas for FETs.17,39 The scaling potential of the proposed CNT-film-based CMOS technology will

determine the limitations on the performance and integration density that can be achieved for CMOS ICs developed using this technology. To explore the scaling behavior of the CNTnetwork-film-based CMOS FETs, we fabricated CMOS FETs with gate lengths varying from 5 to 1 μm. The scaled CMOS FETs demonstrated obvious performance improvements while maintaining the symmetry between the n- and p-FETs, as shown in Figure 2a,b, which presents the transfer and output characteristics of a pair of typical scaled CMOS FETs with a gate length of 1 μm. As shown in Figure 2c,d, the driving current Ion of these CMOS FETs markedly increases with the scaling down of the gate length, which reflects the performance improvement induced by the scaling. In particular, for CMOS FETs with Lg = 1 μm, the typical Ion and gm values reach 15 μA/μm and 20 μS/μm, respectively, 5 times larger than those of CMOS FETs with Lg = 5 μm. The minimum on/off current ratio decreases as the gate length decreases (Figure 2e,f) and even reaches 104 for p-FETs and 103 for n-FETs with a gate length of 1 μm. However, this dimensional scaling of the transistors also causes the on-current fluctuations to increase and lowers the on/off ratio, which is the primary factor that limits the further scaling down of our CNT-film-based CMOS FETs. Using our high-performance CNT-film-based CMOS FETs, we explored the construction of various kinds of CMOS ICs, 4128

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Figure 5. Fabrication and characterization of medium-scale CNT-CMOS-based ICs. (a) Circuit diagram and (b) microphotograph of a CNT CMOS 1-bit full adder and (c) its functional measurements under VDD = 2 V. (d) Microphotograph and (e) circuit diagram of a fabricated 4bit adder. (f) Functional measurements of the eight fabricated 4-bit adders under VDD = 2 V. A3, A2, A1, and A0 as well as B3, B2, B1, and B0 are the input signals to the 4-bit adders. S3, S2, S1, S0, and C are the output sums and the carry. The eight adders were tested in sequence using a series of input combinations (A, B) in the following order: (1111 + 1111, 0100 + 0001, 1011 + 1110, 0000 + 0000), (0010 + 0011, 1101 + 1100), (0100 + 0011, 1011 + 1100), (0110 + 0011, 1001 + 1100), (0111 + 0010, 1000 + 1101), (1100 + 0011, 0011 + 1100), (1110 + 0011, 0001 + 1100), (0110 + 0001, 1001 + 1110).

S3a,b.19 Specifically, the power consumption of an inverter can be reduced to less than 10 pW when VDD is lowered to 0.1 V (see Figure S3b). Second, a high noise margin can be achieved in a wide VDD range from 2 to 0.1 V, as shown in Figure 3c and Figure S3c. The low-level noise margin (NML) and high-level noise margin (NMH) are 0.78 and 0.70 V, respectively, at VDD = 2 V and remain at 0.41 and 0.37 V, respectively, at VDD = 1 V. Third, the inverters exhibit a high voltage gain, which increases with increasing VDD, as shown in Figure 3d, and reaches 60 at VDD = 2 V. Finally, the CMOS inverters were fabricated with a high yield and a high uniformity of performance. All 15 of the fabricated inverters function correctly, as shown in Figure S3d, indicating a yield of 100%. Moreover, the statistical distributions of the voltage gain and transition voltage (see Figure S3e,f) confirm the performance uniformity of the CMOS inverters. The high yield and uniformity of the CMOS

including fundamental logic gates, arithmetic circuits, and sequential circuits. For all of the CMOS ICs investigated in this work, both the p- and n-FETs were designed with the same gate length and channel width of 5 and 25 μm, respectively, for reasons of device uniformity.11 As the most basic type of CMOS ICs, inverters were the first circuits to be constructed (see the circuit diagram and microphotograph presented in Figure 3a) to demonstrate the advantages of these CMOS circuits, and they were found to present at least four advantages, as follows. First, the fabricated inverters exhibit full rail-to-rail voltage transfer characteristics (Figure 3b) under a wide range of operating voltages from 2 to 0.1 V, and the transition voltage is located at almost VDD/2 because of the symmetry between the n- and p-FETs. The scaling down of VDD will reduce the switching currents in an inverter, which, in turn, will lead to a significant decrease in power dissipation, as shown in Figure 4129

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into the input “D” of the first D latch. The state of the T flipflop changes at the falling edge of the “clk” signal, and the output consequently has a frequency of precisely half that of the input signal, as shown in Figure 4f. Therefore, a digital frequency divider was successfully realized. As one of the most important types of arithmetic circuits, adders are always used in the critical paths of microcomputers and digital signal-processing circuits.17,39 A 1-bit full adder was designed and fabricated based on our CNT CMOS FETs, as shown in Figure 5a,b, for which a standard 28-T CMOS 1-bit full adder circuit design was adopted. The fabricated 1-bit full adder produces the correct rail-to-rail outputs (for “S” and “Co”) for all possible input combinations with a supply voltage of 2.0 V, as shown in Figure 5c. Benefiting from our high-performance CMOS FETs with high uniformity and symmetry, the constructed logical ICs, including NOT, NAND, NOR, AND, OR, XOR, and XNOR gates as well as a D latch and even a 1-bit full adder, produce ideal rail-to-rail outputs at a single supply voltage of 2 V. These ICs can function well even under a supply voltage as low as 1 V, as shown in Figures S4 and S5. Notably, an XOR gate, an XNOR gate, a D latch, a T flip-flop, and a 1-bit full adder have been realized as CMOS logical circuits based on CNT network films. To estimate the speed of our CMOS circuits based on CNT film, we have fabricated three-stage ring oscillators based on CMOS inverters (with Lg of p- and n-FETs at approximately 1 μm), and the typical data of the three-stage ring oscillator are shown in Figure S6. The oscillation frequency is approximately 100 MHz under VDD = 4 V, and the gate delay per stage is estimated to be 1.67 ns. Our CMOS FETs based on CNT network films offer the possibility of fabricating complicated ICs at large scales and with high yields. In this study, we also demonstrated the realization of a 4-bit ripple adder, which can be characterized as a medium-scale CMOS IC, based on a CNT network film. It is well-known that a multibit adder can be designed by placing multiple 1-bit full adders in parallel, as shown in Figure 5e, where the carry-out of the ith bit, “Co,i”, is used as the carry-in of the next bit, “Ci,i+1”. We simultaneously fabricated eight 4-bit adders, and a top-view image of an as-fabricated 4-bit adder containing 132 FETs is shown in Figure 5d. All eight of the 4bit adders were tested using various input combinations, and the output results presented in Figure 5f show that all of the eight adders function well, indicating a yield of 100%. The successful fabrication of CMOS-type 4-bit adder based on a CNT film demonstrates that CMOS ICs based on CNT films have begun to expand into the medium-scale regime. In addition, the high yield of even these medium-scale CMOS ICs reflects the uniformity of our CNT CMOS FETs and the advantages of the CMOS technology. Therefore, this CMOS technology based on solution-derived CNT network films will provide the foundation for the wafer-scale fabrication of largescale CNT ICs and will promote the application of CNT-based ICs in flexible, transparent, and transient electronics.3,4,12

inverters can be partially attributed to the high noise margin of CMOS circuits, and they also benefit from the high reliability and symmetry of our doping-free CMOS FETs. Using CNT-film-based CMOS FETs, we constructed twoinput NAND and NOR gates, each consisting of two n-FETs and two p-FETs, as shown in Figure 3e. Subsequently, other kinds of logical ICs, including AND, OR, XOR, and XNOR gates, could be designed as combinations of NAND, NOR, and NOT gates. In particular, an XOR gate was designed using the standard CMOS paradigm, as shown on the right-hand side of Figure 3e; this circuit contains fewer FETs (10 FETs) than does an XOR gate that consists solely of p-FETs (13 FETs).11,17 This decrease in the number of transistors required in our CMOS ICs should be helpful for improving speed and reducing device area. In this study, six of the most popular types of CMOS combinational logic gates, including NAND, NOR, AND, OR, XOR, and XNOR gates, were realized based on CNT network films, as shown in Figure 3f. All of the gates were found to exhibit the correct logical functions (see Table S1 in Supporting Information) with rail-to-rail outputs, as shown in Figure 3g, by virtue of the high noise margin of CMOS circuits and the relatively high-performance uniformity of our FETs. A multiplexer (MUX) is a typical combinational IC that is often used as a basic building block for arithmetic logic units (ALUs).39 A 2-to-1 multiplexer (MUX2_1) was designed using a combination of CMOS logic gates, including two AND gates, one OR gate, and one NOT gate, as shown in Figure 4a. In such a MUX, the output “Y” is chosen from two inputs “A” and “B” by a selector “S”:

Y = (A· S)̅ + (B·S)

(1)

Functional measurements (Figure 4b) show that the fabricated MUX2_1 exhibits the correct logical functions (Table S2); that is, the selector signal “S” determines which input (“A” or “B”) is chosen as the output “Y”. When “S” is “0”, the input “A” is selected to be transferred to the output “Y”, whereas when “S” is “1”, the input “B” is transferred to the output. In addition to combinational logical gates, sequential circuits are equally important in practical digital systems.17,39 Flip-flops or latches are the basic storage elements in sequential ICs and are fundamental building blocks of the digital electronic systems used in computers, communications, and many other types of systems.39 In this study, we demonstrated the fabrication of a D latch, which contains 1 NOT gate and 4 NAND gates, based on our CNT CMOS FETs (see the top view of the fabricated D latch in Figure 4c). As shown in the logical demonstration of the fabricated CNT D latch, for which the measured results are presented in Figure 4d, the output signal “Q” follows the input signal “D” when the enable signal “clk” is “1”. In such a case, the latch is in the “open” state, and the path from the “D” input to the “Q” output is transparent. When “clk” is set to “0”, “Q” retains its previous value (at “clk” = 1) instead of following “D”. In such a case, the path from the “D” input to the “Q” output is closed. The output signal “Q̅ ” is the complement of “Q”. Both “Q” and “Q̅ ” behave as rail-to-rail outputs, indicating that this ideal D latch can serve as a reliable element with which to construct complicated sequential ICs. A toggle (T) flip-flop is a widely used type of sequential circuit; in particular, it is often used as a counter or a frequency divider.39 Here, we realized CNT T flip-flop circuits using two connected D latches, as shown in Figure 4e; the output “Q” of the first D latch is connected to the input “D” of the second D latch, whereas the output “Q̅ ” of the second D latch feeds back

CONCLUSIONS We developed a doping-free CMOS technology based on solution-derived CNT network films. The polarity of the FETs was controlled by using either Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. Topgated CMOS FETs were fabricated that showed high symmetry between the characteristics of n- and p-type devices as well as high yields and good performance uniformity. Various ICs, 4130

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ACS Nano including typical logic gates, sequential circuits such as D latches and flip-flops, and even a 4-bit adder consisting of 132 transistors, were fabricated based on our CNT-film-based CMOS FETs, and all showed 100% yields and rail-to-rail outputs by virtue of the high noise margin of CMOS circuits. The developed CMOS technology has the potential to advance the development of CNT-network-film-based ICs to larger scales and will promote the application of CNT-film-based ICs, especially in flexible and transparent electronics.

Additional discussions about the fabrication, characteristics, and statistics of key performances of as-fabricated CMOS FETs, the characteristics of fabricated inverters, the characteristics of fabricated logic gates with supply voltage of 1 V, and the characteristics of the ring oscillator based on CMOS FETs (PDF)

AUTHOR INFORMATION Corresponding Authors

*E-mail: (Z.Y.Z.) [email protected]. *E-mail: (L.M.P.) [email protected].

METHODS Preparation of the CNT Solution and Thin Films. Raw arcdischarged CNTs were purchased from Carbon Solutions Inc., and the polymer 9-(1-octylonoyl)-9H-carbazole-2,7-diyl (PCz), which was prepared via Suzuki polycondensation, was used as a highly effective dispersant. First, 200 mg of PCz and 100 mg of CNTs were mixed into 100 mL of toluene. The solution was ultrasonicated using a top-tip dispergator (Sonics VC500) for 30 min at an amplitude level of 50%. Then, the solution was centrifuged at 30 000g for 0.5 h (Allegra X64R) to remove most of the bundles and insoluble materials, followed by centrifugation at 30 000g for 2 h to avoid trace contents of metallic nanotubes. Finally, the supernatant was collected for use as the CNT solution. The CNT films were fabricated using the dip-coating method. In preparation for the deposition of a CNT film, a Si/SiO2 substrate was sequentially washed with toluene, acetone, and isopropyl alcohol. Then, the substrate was immersed for 24 h in the CNT solution, in which the CNT concentration was estimated to be 20 μg/ mL based on its absorption spectrum. After deposition, the substrate was blow-dried with 99.999% N2 and then baked at 120 °C or 30 min using a hot plate. Fabrication of the FETs and ICs. Consider that the separated carbon nanotube thin film covers the entire wafer; to achieve accurate gate length and channel width and to remove the possible leakage between the transistors, an electron beam lithography (EBL) process followed by an O2 plasma etching (inductively couple plasma etch) removed the unwanted CNTs outside the device channel region. Then, p-type FETs with a self-aligned gate structure were fabricated. The substrate is first covered with PMMA 200k (AR-P 641, 4000 rpm, 60 s) and baked for 3 min at 170 °C. Then the source and drain contacts were patterned via EBL. A Ti/Pd film with a thickness ratio of 0.3 nm/80 nm was then deposited via electron beam evaporation (EBE), followed by a standard lift-off process. Subsequently, the wafer was coated with PMMA 50k (AR-P 631, 6000 rpm, 60 s) and baked at 150 °C for 3 min. Next, the second resist (MMA 8.5 EL6) is spun on the wafer (6000 rpm, 60s) followed by the baking at 180 °C for 3 min. The gate window was then patterned via EBL, and an 18 nm HfO2 film was grown via atomic layer deposition at 90 °C, followed by the EBE deposition of a 15 nm Pd film. The sample was dipped into acetone for more than 12 h, and then a lift-off process was carried out. After this lift-off process, the self-aligned HfO2/Pd gate stack was formed and then the p-FET was finished. Subsequently, n-FETs were fabricated using a process similar to that for the p-FETs, but a Sc film was used instead of a Pd film to form the source and drain contacts. Finally, we applied a Ti/Au film with a thickness ratio of 20 nm/100 nm to serve as the interconnects and pads for the circuits. A schematic diagram of the process flow is shown in Figure S1a. Characterization of the FETs and ICs. Optical images of the ICs were captured using an optical microscope (Olympus DSX 510). The electrical performances of the FETs and the ICs were measured using a Keithley 4200 system and a probe station (Summit 11000, Cascade Microtech.). For the IC measurements, the input signal was generated by a signal generator (Agilent MXG N5181A), and the output was measured using an oscilloscope (Agilent DSO7054A).

ORCID

Zhiyong Zhang: 0000-0003-1622-3447 Author Contributions

Z.Z. and L.M.P. proposed and supervised the project. Y.Y. and L.D. designed the integrated circuits. Y.Y. performed the deposition of the CNT films as well as the fabrication and characterization of the CNT transistors and integrated circuits. H.J. prepared the CNT solution. Y.Y., Z.Z., and L.M.P. analyzed the data and co-wrote the manuscript. All authors discussed the results and commented on the manuscript. Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS This work was supported by the National Key Research & Development Program (Grant Nos. 2016YFA0201901 and 2016YFA0201902), the National Science Foundation of China (Grant Nos. 61376126, 61321001, and 61427901), and the Beijing Municipal Science and Technology Commission (Grant No. D161100002616001-3). REFERENCES (1) Tulevski, G. S.; Franklin, A. D.; Frank, D.; Lobez, J. M.; Cao, Q.; Park, H.; Afzali, A.; Han, S.-J.; Hannon, J. B.; Haensch, W. Toward High-Performance Digital Logic Technology with Carbon Nanotubes. ACS Nano 2014, 8, 8730−8745. (2) Peng, L.-M.; Zhang, Z.; Wang, S. Carbon Nanotube Electronics: Recent Advances. Mater. Today 2014, 17, 433−442. (3) Park, S.; Vosguerichian, M.; Bao, Z. A Review of Fabrication and Applications of Carbon Nanotube Film-Based Flexible Electronics. Nanoscale 2013, 5, 1727−1752. (4) Jin, S. H.; Shin, J.; Cho, I.-T.; Han, S. Y.; Lee, D. J.; Lee, C. H.; Lee, J.-H.; Rogers, J. A. Solution-Processed Single-Walled Carbon Nanotube Field Effect Transistors and Bootstrapped Inverters for Disintegratable, Transient Electronics. Appl. Phys. Lett. 2014, 105, 013506. (5) Lee, H. W.; Yoon, Y.; Park, S.; Oh, J. H.; Hong, S.; Liyanage, L. S.; Wang, H.; Morishita, S.; Patil, N.; Park, Y. J.; Park, J. J.; Spakowitz, A.; Galli, G.; Gygi, F.; Wong, H.-S. P.; Tok, J. B.-H.; Kim, J. M.; Bao, Z. Selective Dispersion of High Purity Semiconducting Single-Walled Carbon Nanotubes with Regioregular Poly(3-Alkylthiophene)S. Nat. Commun. 2011, 2, 541. (6) Wang, C.; Zhang, J.; Ryu, K.; Badmaev, A.; De Arco, L. G.; Zhou, C. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications. Nano Lett. 2009, 9, 4285−4291. (7) Liyanage, L. S.; Lee, H.; Patil, N.; Mitra, S.; Bao, Z.; Wong, H.-S. P.; Park, S. Wafer-Scale Fabrication and Characterization of Thin-Film Transistors with Polythiophene-Sorted Semiconducting Carbon Nanotube Networks. ACS Nano 2012, 6, 451−458. (8) Brady, G.; Way, A. J.; Safron, N. S.; Evensen, H. T.; Gopalan, P.; Arnold, M. S. Quasi-Ballistic Carbon Nanotube Array Transistors with Current Density Exceeding Si and GaAs. Sci. Adv. 2016, 2, e1601240.

ASSOCIATED CONTENT S Supporting Information *

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DOI: 10.1021/acsnano.7b00861 ACS Nano 2017, 11, 4124−4132

Article

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