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High-Performance Flexible Thin-Film Transistors Based on Single-Crystal-Like Silicon Epitaxially Grown on Metal Tape by Roll-to-Roll Continuous Deposition Process Ying Gao, Mojtaba Asadirad, Yao Yao, Pavel Dutta, Eduard Galstyan, Shahab Shervin, Keon-Hwa Lee, Sara Pouladi, Sicong Sun, Yongkuan Li, Monika Rathi, Jae-Hyun Ryou, and Venkat Selvamanickam ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b06770 • Publication Date (Web): 13 Oct 2016 Downloaded from http://pubs.acs.org on October 20, 2016

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ACS Applied Materials & Interfaces

High-Performance Flexible Thin-Film Transistors Based on Single-CrystalLike Silicon Epitaxially Grown on Metal Tape by Roll-to-Roll Continuous Deposition Process Ying Gao,§,‡,┴ Mojtaba Asadirad,§,┴ Yao Yao,§,‡ Pavel Dutta,†,‡ Eduard Galstyan,‡ Shahab Shervin, §

Keon-Hwa Lee,† Sara Pouladi,§ Sicong Sun,§ Yongkuan Li,§ Monika Rathi,†,‡ Jae-Hyun Ryou*,†,

§,‡

and Venkat Selvamanickam*,†,§,‡

†

Department of Mechanical Engineering, §Materials Science and Engineering Program, and

‡

Texas Center for Superconductivity at the University of Houston (TcSUH), University of

Houston, 4726 Calhoun Rd Rm N207, Houston, Texas 77204-4006. ABSTRACT: Single-crystal-like silicon (Si) thin films on bendable and scalable substrates via direct deposition are a promising material platform for high-performance and cost-effective devices of flexible electronics.

However, due to thick and unintentionally-highly-doped

semiconductor layer, the operation of transistors has been hampered.

We report the first

demonstration of high-performance flexible thin-film transistors (TFTs) using single-crystal-like Si thin film with a field-effect mobility of ~200 cm2/V-s and saturation current, I/lW >50 µA/µm, which are orders-of-magnitude higher than the device characteristics of conventional flexible TFTs. The Si thin films with a (001) plane grown on a metal tape by “seed and epitaxy” technique show nearly-single-crystalline properties characterized by x-ray diffraction, Raman spectroscopy, reflection high-energy electron diffraction, and transmission electron microscopy. The realization of flexible and high-performance Si TFTs can establish a new pathway for extended applications of flexible electronics such as amplification and digital circuits, more than currently-dominant display switches. KEYWORDS: single-crystal-like Si, flexible electronics, thin-film transistors, epitaxial growth, roll-to-roll process

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1. INTRODUCTION Group-IV silicon (Si) is the most important material in electronics and optoelectronics with diode and metal-oxide-semiconductor (MOS) structures thanks to its earth abundance, excellent thermal stability, promising carrier mobility, and high compatibility with oxide materials.1,2 Among the different types of devices including photovoltaic solar cells,3,4 light emitting diodes,5 high power transistors,6 bipolar junction transistors,7 photodiodes,8 etc., a majority of efforts have been focused on field-effect transistors (FETs).9,10 The Si material for FETs is classified into single-crystalline, polycrystalline (poly-Si), and amorphous (a-Si) materials, depending on its crystallinity. Single-crystalline Si delivers the highest performance in the devices, as it does not contain crystalline defects that act as traps, scattering sources, and leakage paths of charged carriers.11,12 However, the materials and fabrication process of the single-crystalline devices are expensive and not easily scalable, limited by the size of starting single-crystal wafer substrates. In addition, single-crystalline semiconductor wafers lack mechanical flexibility.

Hence,

economical and bendable devices are mostly made of amorphous or polycrystalline thin-film materials. However, their performance characteristics are inferior, including low switching speed and high power consumption, mainly due to their low mobility (µ). Besides non-singlecrystalline Si thin films,13,14 organic and oxide semiconductors15,16 have been developed for flexible TFTs. Even after decades of research and development, however, the mobility values of most devices17,18 still remain in the range of µ = 0.1−20 cm2/V-s (ref. 19),19which is significantly lower than the typical values of single-crystalline Si with µ > 400 cm2/V-s. The low mobility values of current flexible TFTs impose limitations in their use usually to switches of individual pixels in display systems. State-of-the-art mobility value of ~300 cm2/V-s for poly-Si TFTs was recently achieved.20 However, the devices still show major technical challenges associated with

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random orientations and various sizes of the crystal grains in polycrystalline films, resulting in non-uniform mobility values and threshold voltages among devices, which makes the application of devices in the system less practical.21

Flexible single-crystalline Si devices have been

developed via layer-transfer technigues.22,23

In these methods, semiconductor films are

epitaxially grown on semiconductor wafers and are transferred onto bendable substrates followed by the removal of the non-flexible wafers. The technique requires complicated fabrication processes and is based on wafer materials, which is expensive and limited in process scale-up. Although extensive efforts have been made, no TFT with mechanical flexibility, high performance, stable device characteristics, and low processing cost has been demonstrated. A nearly-single-crystalline Si thin film on a bendable substrate by direct deposition using continuous roll-to-roll (R2R) process potentially provides a material platform for better performance, lower cost, stable, and flexible thin-film devices.

Nearly-single-crystalline

materials contain crystal grains whose crystallographic orientations are well aligned in both outof-plane (c axis) and in-plane (a and b axes) directions. The materials should offer better electrical performance in devices because of their small grain-to-grain misorientations, which helps the transport of free charged carriers with less scattering. The first oriented Si film grown on metal substrates was developed by Findikoglu, et al.24 γ-Al2O3 was employed as a template layer for Si epitaxy. The electrical characteristics of the Si film were severely limited by high density of dislocations and stacking faults due to structural mismatches between the layers. CeO2 (fluorite structure) has better structural compatibility and closer lattice match with Si. However, epitaxial growth of Si on CeO2 was hindered by the formation of amorphous SiO2 at the interface.25 CaF2 (the same structure with CeO2 without oxygen anion) can also be used as a template layer. However, CaF2 buffer layer was not fully textured, resulting in relatively low

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conversion efficiency in photovoltaic devices.26 Device-quality materials (i.e., accurate control of thickness and doping concentration of the channel as well as good crystallinity) and working devices based on nearly-single-crystalline Si have not been demonstrated.

Most films are

relatively thick (several micrometer) for defect annihilation and improvement of crystalline quality. Furthermore, they suffer from auto-doping via diffusion of unwanted elements from underneath layers at elevated temperatures, making them heavily-doped semiconductor films. In the buffer structure,27 Ce from the reduction of CeO2 could diffuse into semiconductor film during the following deposition at elevated temperatures and may act as an acceptor in group IV materials. In fact, Ge buffer layer without intentional doping grown atop CeO2 generally showed high p-type conductivity, indicative of such diffusion.

These materials issues have been

addressed in this paper, presenting the demonstration of the transistor operation using a nearlysingle-crystalline Si thin film grown on a flexible substrate by direct deposition. In the present study, we developed device-quality flexible Si thin films for high-performance transistors on a polycrystalline metal tape. The Si films show nearly-single-crystalline nature with full-width at half-maximum (FWHM) of ω = 1.2° and φ = 1.8° from x-ray diffraction (XRD) out-of-plane and in-plane measurements, and have controlled phosphorus (P) doping (n ~ 1016 cm-3).

The single-crystal-like (nearly-single-crystalline) Si, while not a perfect single

crystal without crystalline defects, are made of crystal grains in a well-aligned crystallographic orientation with low-angle grain boundaries, in contrast to polycrystalline semiconductors containing various-size grains with random orientations. We also developed the new device architecture and fabrication process of TFTs to mitigate the effect of the auto-doping and to enhance the performance characteristics including field-effect mobility (µFE ~ 200 cm2/V-s) and saturation current.

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2. EXPERIMENTAL SECTION 2.1. Thin-film material structure design and characterizations. The materials in multilayer structures, as shown Figure 1a, were directly grown on a metal substrate. Most layers in this study, except the Si layer, were deposited by continuous R2R deposition processes.28,29 This study employed electro-polished Hastelloy C-276 tapes with a dimension of 12 mm ×50 µm (width × thickness), as a substrate. Hastelloy is chemically stable at relatively high temperatures for the epitaxy of Si and Ge. Polymeric substrates, which are commonly used in flexible devices, have limitations in film growth and device fabrication due to their low maximum processing temperature, e.g., ~220 °C. Flexible glass tapes can also be used as a substrate; however, when single-crystal-like semiconductor materials were deposited, minor polycrystalline features were observed in the films30 due to limited deposition temperatures up to ~650 °C, which is a glasstransition temperature. Heat treatment above this temperature can cause loss of flexibility in the substrate.

The

Hastelloy

tapes

offer

mechanical

flexibility,

lightweight,

thermal/mechanical/chemical stability (up to ~1000 °C), and compatibility with R2R deposition for the scale-up of manufacturing processes. However, diffusion of substrate metal components such as Ni, Cr, and Mn into the buffer and semiconductor films may occur during the high temperature process. Therefore, the metal tape was initially coated with Al2O3 (~80 nm) by radio-frequency (RF) sputtering as a diffusion-barrier layer to prevent the detrimental effects from the diffusion. Further increase in the Al2O3 thickness does not help to reduce the substrate diffusion. Then, a nucleation layer of Y2O3 (~5 nm) was deposited by RF sputtering to assist highly-oriented biaxially-textured MgO formation. The MgO deposition was carried out in an ion-beam-assisted deposition (IBAD) system with Mg target and a reactant gas of O2. For the assist-ion beam, Ar+ was accelerated with energy of 1000 eV at an incident angle of 45° to align

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the beam in channeling direction. The thickness of MgO was approximately 10 nm, after 80 seconds of the IBAD process. When the MgO film fabricated by IBAD becomes thicker, the (001) plane begin to tilt away from the ion beam direction, which makes the channeling effect along the direction less effective and deteriorating the biaxial alignment of grains. Then, homo-epitaxial MgO film (~60 nm) and subsequent buffer layers of LaMnO3 (~50 nm), CeO2 (~160 nm), and Ge (~800 nm) were deposited in an RF magnetron sputtering R2R system. The selected thickness for buffer layers is based on our previous optimization. In-situ reflection high-energy electron diffraction (RHEED, STAIB Instruments with a kSA 400 detector) was used to evaluate the progression of the surface structure of the IBAD-MgO and other layers. Thin-film growth of Si was carried out in a plasma-enhanced chemical vapor deposition system (PECVD, Oxford Instruments) using inductively-coupled plasma operated at 13.56 MHz radio frequency. Before the Si growth, the flexible template with a Ge layer on top was first annealed for 10 min in vacuum at 600 °C to remove native oxides on the surface. Then, plasma was started at a pressure of 75 mTorr with H2 to passivate the Ge dangling bonds for 1 min. Si films were deposited at an optimized plasma power of 300 W and a temperature of 750 °C. The base pressure was below 10-7 Torr. Hydrogen (H2) dilution was used (SiH4-to-H2 ratio was 1:4) to passivate the Si dangling bonds. After deposition for 20 minutes for an unintentionally-doped Si layer (~2 µm), PH3 (10 ppm balanced in H2) was introduced as a donor precursor to form an n-Si layer doped with P. The total thickness of Si layers was ~2.2 µm and the channel thickness was ~200 nm with a free electron concentration, n ~ 1×1016 cm-3. Si thin film and buffer layers were characterized using a high-resolution XRD (Bruker Instrument). Raman scattering measurements were performed on a triple spectrometer (Horiba Jobin Yvon HR-800) equipped with a liquid-nitrogen cooled CCD detector using a 514.5 nm line of Ar+ laser

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as an excitation source. Microstructure of the layers was further characterized by field-emission transmission-electron microscopy (TEM, JEOL JEM 2010F). 2.2. Fabrication and evaluation of TFT. TFT devices were fabricated using a single-crystallike Si channel on a hybrid structure. A SiO2 gate dielectric layer was deposited on Si by PECVD (Plasma-Therm). The thickness was ~80 nm as measured by ellipsometry. Device patterns were defined by photolithography using an i-line UV light (λ = 365 nm) in a mask aligner (ABM). Selected regions of SiO2 film were partially etched for source (S) and drain (D) with an etching depth of ~20 nm using inductively-coupled plasma reactive-ion etching (ICPRIE, Oxford Instruments) with a mixture of CHF3:O2 gases. P+ ions were implanted on S/D regions at two energies of 50 and 80 keV with dose of 1×1014 cm-2 for both energies. Heavilydoped S/D regions (peak carrier concentrations of 1‒2×1019 cm-3) were formed after recovery annealing by rapid thermal annealing (RTA). Remaining SiO2 of the S/D area was etched before the metal electrode formation.

Nickel/gold (Ni/Au, 30/300 nm) metals were deposited by

electron-beam evaporation at a base pressure of ~8×10-7 Torr for S/D electrodes, followed by annealing. Aluminum (Al, 300 nm) was deposited by thermal evaporation at a base pressure of ~2×10-5 Torr for gate (G) electrode. I-V characteristics of the fabricated devices were measured using a semiconductor parameter analyzer (Keithley 4200) at room temperature. Transfer-length method was used to evaluate series resistance components including sheet and contact resistances. Dielectric material quality was evaluated via Igs-Vgs measurements. Effective fieldeffect mobility, µFE was extracted from the linear region in the Ids-Vds curve at Vds = 0.5 V. Saturation mobility was calculated from the Ids-Vds family curves in the saturation region using saturation current using following equation, where Cox, VT, W, and L are capacitance of gate, a threshold voltage, a channel width, and a channel length, respectively:

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I ds =

W × Cox × µ sat × Vgs − VT 2L

(

)2

Figure 1. Flexible multilayered material structure and its structural properties: (a) Schematic illustration of multilayer architecture consisting of single-crystal-like Group-IV semiconductors and oxide buffer layers deposited on a Hastelloy tape for the transformation of crystallinity from a polycrystalline substrate to a nearly-single-crystalline semiconductor thin film. (b) Photograph of metal tape used as a substrate for high-temperature growth of oxides and semiconductor layers. (c) Disordered RHEED pattern of an amorphous Al2O3 layer (~80 nm) deposited on Hastelloy as a diffusion barrier. (d) RHEED pattern of the second MgO layer (~60 nm) homoepitaxially grown by sputtering on the first IBAD-MgO layer (~10 nm) to form a cube-textured crystal structure as a seed for the epitaxial growth of subsequent layers. (e) RHEED pattern of a LaMnO3 layer (~50 nm) on MgO. (f) RHEED pattern of a CeO2 layer (~160 nm) on LaMnO3. (g) RHEED pattern of a Ge layer (~800 nm) for a high-quality single-crystal-like Si thin film. The buffer layers (LaMnO3, CeO2, Ge) are deposited by R2R sputtering and act as a new template for next layer with improved crystalline quality. (h) RHEED pattern of an n-type Si layer (~200 nm) on a relatively thick p-type Si layer (~2 µm), both of which are deposited by PECVD.

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3. RESULTS AND DISCUSSION 3.1. Single-Crystal-Like Si Thin Films 3.1.1. Direct deposition of thin film on flexible substrate. The direct deposition of singlecrystal-like semiconductor films on the flexible substrates critically requires the transformation of crystallinity from poly-crystals of substrates to near-single-crystals of semiconductor layers. The

deposition

of

biaxially-textured

buffer

layers

where

the

crystal

grains

are

crystallographically aligned in both in-plane and out-of-plane directions is an important step for the transformation. Recently, the demonstration of single-crystal-like thin films on non-singlecrystalline substrates via direct deposition has been reported.30 A majority of these thin films were obtained via a “seed and epitaxy” technique. In this technique, a biaxially-textured layer (e.g., CaF2, MgO, CeO2, etc.) serves as the seed of following layers for epitaxial growth. Various combinations of materials were designed to achieve single-crystal-like thin films. For example, single-crystal-like Ge layer has been demonstrated using a CaF2 seed layer deposited by oblique-angle deposition. However, the resulting buffer structure was porous, which requires an additional thick capping layer deposited at a very slow rate;31 hence, the layer was not suitable for a channel of transistor devices. New buffer layers are developed in this study to achieve a high-crystalline-quality Si layer for the transistor channel. The first and second layers (Al2O3 and Y2O3) are not textured and generally amorphous. Biaxially-textured MgO (~10 nm) was grown by IBAD. In the IBAD process, the substrate is bombarded with an ion beam to sputter away unfavorably-oriented crystallites, resulting in biaxially-textured thin films.

In-situ RHEED pattern during the

deposition of Al2O3 (Figure 1c) indicates a disordered surface, as expected from the amorphous layer. High-quality cube texture is observed by the sharp spots in the RHEED pattern of the 9



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MgO layer, as shown in Figure 1d. After the formation of biaxially-textured MgO, LaMnO3 (orthorhombic perovskite structure) and CeO2 (fluorite structure) layers were deposited to provide structural compatibility with semiconductor (diamond structure) layers and to mitigate the detrimental effects from the lattice mismatch between semiconductor and MgO (rock-salt structure) layers (Figure S1 in SI for projected atomic arrangement on a basal plane of unit cell for each structure). In-plane lattice mismatch on a (001) plane between MgO (a = 4.212 Å) and Ge (a = 5.658 Å) is –0.256, using a formula (as–al)/al, where as and al are lattice parameters of substrate (underlayer) and layer (upper-layer), respectively. The lattice mismatch decreases by introducing CeO2 (a = 5.41 Å) to –0.044 between CeO2 and Ge. However, the lattice mismatch between MgO and CeO2 is still large (–0.221). LaMnO3 plays a critical role to accommodate the mismatch as a transition layer for the epitaxial growth of CeO2 on MgO. A pseudo-cubic lattice parameter of LaMnO3 is 3.91 Å, which is closely matched to the lattice parameter of MgO. Domain epitaxy occurs in the growth of LaMnO3 on MgO, where 13 unit cells of LaMnO3 match with 12 unit cells of MgO. To mitigate the effect of large lattice mismatch between LaMnO3 (3.91 Å) and CeO2 (5.41 Å), the epitaxial CeO2 layer is grown with in-plane 45° rotation with respect to the LaMnO3 unit cell. In this case, closer lattice match is achieved between the pseudo-cubic lattice parameter of LaMnO3 (3.91 Å) and the half of the diagonal distance of the CeO2 unit cell (3.81 Å). This unit cell rotation results in the epitaxial growth with only 0.026 mismatch, where two corner Ce atoms match with the two center La atoms, as shown in Figure S1a and S1b for 3Dand top-view atomic configurations of projected (001) basal planes in SI. Also, the rotational relation between LaMnO3 and CeO2 is shown in Figure S1c. Now, Ge can be grown on CeO2 with reduced lattice mismatch (–0.044) and structural compatibility. Atomic configuration of the

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Ge (and Si) basal plane with diamond structure perfectly matches with that of CeO2 basal plane. A continuous improvement in the RHEED pattern from MgO to Ge, as shown in Figure 1d‒g, confirms subsequent epitaxial growth of LaMnO3, CeO2, and Ge layers. It starts with a strong electron diffraction pattern of cubic lattice MgO (Figure 1d), then the pattern for CeO2 (Figure 1f) rotates 45° with the assistance of LaMnO3 (Figure 1e) transition layer. The RHEED patterns of Si (Figure 1h) and Ge (Figure 1g) are similar to that of CeO2 without rotation. Corresponding (110) plane pole figures for the buffer layers in Figure S2a‒S2d show another strong evidence of the epitaxial relationship. The pole figure of CeO2 displays four peaks which rotate 45° with respect to four peaks of LaMnO3. For the epitaxy of semiconductor channel layer, Si could be deposited directly on CeO2, as the lattice mismatch (–0.004) between CeO2 and Si (a = 5.431 Å) is smaller than that between CeO2 and Ge (–0.044). However, a Ge layer is inserted between CeO2 and Si as a chemically-stable transitional buffer layer. Without the Ge buffer layer, epitaxial growth is disrupted due to the preferential formation of amorphous SiO2 at the CeO2/Si interface during the growth.25 Si was grown on the Ge buffer by PECVD. Sharp spots in the RHEED pattern for Si thin-film in Figure 1h suggest that single-crystal-like semiconductor is formed. Not even weak diffraction rings are observed in the Si RHEED pattern, confirming no randomly-oriented polycrystalline grains formed in the Si layer.

3.1.2. Structural characterizations of single-crystal-like Si thin film. In addition to in-situ characterization of the surface by RHEED, further characterization of the films by XRD was performed. Figure 2a shows 2θ-θ scans of the structures before and after the growth of Si layers. Red and blue curves show scans for a Ge template structure and a structure of Si grown on the Ge template, respectively. Only a high intensity peak at 2θ = 69.14° corresponding to (004) diffraction is found among Si diffraction peaks. No other diffraction peak from Si is observed.

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This result indicates that out-of-plane direction of the Si film is well aligned in a [001] direction. Also, only diffraction peaks associated with c-axis orientations for most buffer layers, including CeO2 (002), MgO (002), LaMnO3 (002), Ge (004), and CeO2 (004), are measured, suggesting epitaxial layer relationships between the Si thin-film and underlying buffer layers. Out-of-plane tilts of single-crystal-like Si and Ge were characterized by rocking curve (ω scan), as shown in Figure 2b.

The FWHMs of Si-(004) and underlying Ge-(004) peaks are 1.20° and 1.48°,

respectively. Narrowing of the Si-(004) peak is attributed to further improvement in crystallinity of the Si layer, compared to that of the Ge layer. Doping with PH3 precursor may generate additional crystalline defects, resulting in a broader FWHM of Si-(004) peak.32 Pole figures and rotational scan (φ scan) were used to study in-plane orientation alignment. The pole figure of the Si film in Figure 2c displays four-fold-symmetry of the (111)-poles at ~55° with respect to a caxis, indicating biaxial alignment in the Si films. Low-intensity Si-(111) peaks which lie at 16° with respect to a c-axis (four faint dots near the center of pole figure in Figure 2c) are also observed. We speculate that these (111) poles at 16° may be related to the crystal twinning which occurs at the interface between Si and Ge layers by lattice mismatch. The existence of twinning near the interface is also observed by TEM, shown in Figure 3 later. An integrated φ scan of Si-(111) peaks reveals four peaks separated by 90° as shown in Figure 2d, further confirming in-plane alignment of the Si crystals. The FWHM of the peaks in φ-scan is 1.8°, suggesting that the spread in the in-plane orientation of crystals is minimized. characterizations confirm that the Si film is a nearly single-crystalline material.

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Figure 2. Structural properties of single-crystal-like n-type Si thin-film material: (a) 2θ-θ scans of single-crystal-like Si film (blue curve) grown by PECVD on a Ge template (red curve) by XRD, showing a strong preferred c-axis out-of-plane orientation. (b) Sharp peaks in rocking curves by XRD ω scan around (004) peaks of Si film (blue curve) and underlying Ge template (red curve), showing narrower linewidth for the peak of Si thin film. (c) (111) pole figure of Si film with four-fold symmetry showing near single crystal features with strong crystallographic alignment in in-plane and out-of-plane directions. (d) Rotational scan (φ-scan) by XRD around Si (111) peak showing four sharp peaks 90° apart. (e) Raman spectra of flexible single-crystallike Si film (blue curve) and single-crystalline Si wafer (green curve), showing a sharp and strong transverse optical Raman mode. The shift of peak for flexible Si is due to compressive stress in the film. The crystal structure of the Si thin film was also analyzed by Raman spectroscopy in comparison with single-crystalline Si wafer.

Raman peak widths and positions can reveal

substantial amount of information about the crystalline quality of the semiconductor films. The

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film with narrower FWHM of the Si transverse optical (TO) peak represents better quality of the Si with less crystalline imperfections due to a longer phonon lifetime.33,34 In Figure 2e, a strong TO mode peak positioned at 525.8 cm-1 was observed for the flexible Si thin film. The FWHM of 4.5 cm-1 for the Si thin film is only slightly wider than that of the Si wafer (3.4 cm-1), suggesting a high crystalline quality of the single-crystal-like Si films.

Features of nano-

crystalline (a peak at 500 cm-1) and amorphous (a peak at 480 cm-1) materials35 are not detected in the single-crystal-like Si. Compared to other Si films deposited on foreign substrates (glass, stainless steel, and plastics) which are typically composed of a mixture of amorphous and polycrystalline phases, the Si film in this study is completely crystalline. The peak of the Si films (525.8cm-1) is shifted with respect to single-crystal Si wafer (520.7 cm-1). Compressive stress generally leads to a shift to higher wavenumbers. In the case of a Si film on a Ge substrate, tensile stress should be induced in the film due to smaller lattice constant of Si than that of Ge, which is not consistent data shown in Figure 2e. For the stress analysis in the Si layer, the effects of the underneath oxide buffer layers and substrate may need to be considered too. The Ge buffer layer itself may be under the compressive stress due to the smaller lattice constant than that of underlying oxide layers.

This compressive stress can

consequently be transferred to Si. In addition, thermal mismatch between semiconductors and metal will play a role. The relatively high in-plane coefficient of thermal expansion (CTE) of Hastelloy (>1×10-5 K-1) will induce large compressive stress in Si with thermal expansion coefficient of 3.77×10-6 K-1 during cooling-down from the growth temperature to room temperature.36

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Figure 3. Microstructural characterization of flexible heterostructure by TEM: (a) Micrograph of the cross-section of the heterostructure consisting of single-crystal-like Si layer, Ge buffer layer, and oxide buffer layers on a metal tape. Density of threading dislocations, which is high near the Si/Ge interface, decreases, as Si grows to a thicker film, and eventually approaches to a lower value in the active device region for a channel of transistors. (b) High-magnification view of the area near n-type Si channel showing threading dislocations in the selected area of Figure 3a. (c) High-magnification view of the Si and Ge interface, showing misfit dislocations and twins. (d) SAED pattern of Si, confirming diamond structure of single-crystal-like Si. (e) SAED pattern of Ge. Microscopic characterization of the thin-film structure was carried out by high-resolution TEM.

Figure 3a‒3c show dark-field cross-sectional TEM micrographs of the flexible

heterostructure. Corresponding selected-area electron diffraction (SAED) patterns of Si and Ge thin films are shown in Figure 3d and 3e, respectively. Both SAED patterns show spotty diffraction, confirming epitaxial growth and single-crystalline nature of the Si and Ge films. TEM results are in a good agreement with RHEED, XRD, and Raman spectroscopy analysis described earlier. The high densities of misfit dislocations and {111} twin defects running at an

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angle of 54.7° to the interface (shown in Figure 3c) are possibly due to lattice mismatch (–4.4%) and the difference in the CTE between the layers. Features of the undulation/buckling at the Ge/Si interface in Figure 3a can be attributed to the rough surface (rms roughness >5 nm) of Ge. For the growth of Ge in this study, we observed surface smoothness and crystalline quality are a trade-off. In general, higher deposition temperature of Ge results in a narrower linewidth in XRD rocking curve peak but with compromised surface morphology. The density of defects decreases significantly, as the Si thickness increases. Only a few threading dislocations are observed in top region of the Si film, as shown in Figure 3a and 3b. This may be attributed to gliding and annihilation of threading dislocations under strain as the films grow thicker, as previously reported for Si films grown on sapphire and biaxially textured semiconductor films on metal substrates.24,37 The reduction in dislocation density is expected to improve the mobility of charged carriers in the Si thin film.

3.2. Flexible High-Mobility Transistors 3.2.1. Device architecture and design. We employed a vertical p-n junction structure using the flexible single-crystal-like Si to form a channel layer with an optimum thickness and doping. Numerical study by two-dimensional technology computer-aided design (2D TCAD) simulation was used to design the optimum transistor device structure with a vertical n-p structure. Device simulation results confirmed no transistor behavior for an as-deposited heavily-doped Si thin film as a channel (for example, thickness >1 µm, p-type conductivity with NA > 1018 cm-3), as expected (Figure S3 in SI for device simulation of a non-working transistor). This situation is similar to unintentionally doped semiconductor layers that are typically high p-type. The p-type auto-doping presumably originates from the diffusion of Ce (Group III) during the epitaxy of

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semiconductor layers at elevated temperatures. Also, other elements in the buffer layers (such as Mg and Mn) could contribute to p-type doping of the semiconductor layers. TFT structure was modified by adding a Si p-n junction with a lightly-doped thin layer of n-Si on top. The vertical p-n junction is intended to electrically isolate a thin lateral channel from underlying layers. A TFT device structure was developed using additional Si p-n junction on the flexible template (Figure S4 in SI for device simulation of a working transistor with a p-n junction on an oxide layer).

3.2.2. TFT device development and characterization.

Top-gate TFTs were fabricated

employing an n-Si channel with a carrier concentration of n ~1×1016 cm-3 (measured by Halleffect using van-der-Pauw geometry at room temperature).

Figure 4 shows a schematic

fabrication process and device structure of the TFTs. The gate dielectric shows a very good insulating characteristic with low leakage currents (Figure S5 in SI for gate leakage data). Heavy doping in S/D regions of a channel by P+ ion implantation is vital for optimum current spreading through a well-defined channel and simultaneously to lower specific contact resistivity (ρc) (Figure S6 in SI for ion energies and dose for the implantation calculated by SRIM (stopping and range of ions in matter) Monte Carlo simulation). A thin layer of Ni metal was employed for low ρc by the formation of nickel silicide with a low Schottky barrier height at the Ni-Si interface (Figure 4c). Figure 4d shows top-gate geometry of the TFT device. The gate width/length (W/L) ratio of the device is ~2 with a channel length of 14 µm and a gate width of 30 µm. Figure 4e shows a schematic cross-sectional illustration of the flexible TFT when the device is bent. A photograph of the fabricated flexible single-crystalline-like Si TFTs on a metal tape is shown in Figure 4f.

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Figure 4. Device fabrication process and structure of flexible Si-TFTs: (a) Schematic layer structure for TFTs including oxide buffer, Ge buffer, and Si layers grown on a Hastelloy tape. A SiO2 layer (~80 nm) is deposited as gate dielectric by PECVD. (b) Selected area of SiO2 is dryetched using reactive ion etching (RIE) for phosphorus (P) ion implantation to define source (S) and drain (D) regions. (c) NiSi metallization for S/D contact formation on n-Si. (d) Top-gated Si-TFT fabrication is completed with S/D contacts and Al gate metal. The device dimension includes channel width and length, W/L = 30/14 µm, gate dielectric thickness, tox = 80 nm, gate to S/D metal gap is ~ 5 µm, and channel depth, tch ~200 nm. (e) A schematic illustration of the flexible TFT in a bend-down condition. (f) A photograph of the Si-TFTs showing mechanical flexibility of the devices. Figure 5a shows family curves of source-to-drain currents and voltage (Ids-Vds) characteristics of a typical device without bending. 6 devices with the same size and same geometry from different locations of the samples were successfully measured and all the devices show nearly

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indistinguishable characteristics in family curves and transfer characteristics. The change in Ids shows a typical enhancement-mode n-type channel with higher current by more positive gate bias. The channel can handle saturation currents, Ids,sat ~ 1.5 mA at a gate bias of Vgs = 20 V. A plot of Ids-Vgs (transfer characteristics) at Vds = 15 V is shown in Figure 5b. A high field-effect mobility (µFE) of ~200 cm2/V⋅s is achieved for the unbent devices. The saturation mobility (µsat) is also calculated to be ~160 cm2/V⋅s using the Ids-Vds family curves in the saturation regime, which is close to the µFE. The channel is switched off at a negative gate bias and the on/off ratio (Ion/Ioff) is ~106. The threshold voltage (VT) is ~-0.7 V, as shown in Figure 5f. The devices were also characterized in bent conditions. A slight degradation of performance characteristics is observed in a bent condition with a curvature radius, R = 3 cm, shown in the inset of Figure 5c. The saturation current decreases by ~7% when the TFT is bent (Figure 5d), while the threshold voltage stays the same (Figure 5f), which confirms the stability of the flexible Si TFTs during the operation. No noticeable reduction in the on/off ratio occurs, when the TFTs are bent (Figure 5c and 5e). As compared to other developed flexible TFTs, the TFTs in the present work show an excellent transistor behavior with high mobility owing to its superior crystalline quality of the single-crystal-like Si used in the channel. Especially, saturation current per unit gate width, I/lW at the same gate bias (I/lW > 0.05 mA/µm at Vgs = 20 V) is significantly higher than reported values of TFTs based on a-indium gallium zinc oxide (~0.75 µA/µm at Vgs = 20 V and µ = 9.1 cm2/V-s),38 organic materials (~0.05 µA/µm at Vgs = -20 V and µ = 3 cm2/V-s),39 and a-Si (~0.1 µA/µm at Vgs = 20 V and µ = 0.8 cm2/V-s).40 The current value of mobility certainty has a room for further improvement approaching that of single-crystalline Si with further optimization of seed and epitaxy and device fabrication process. µFE∼200 cm2/V-s is not significantly lower

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than the value of state-of-the-art single-crystal Si used in CMOS, having n-type channel (∼425 cm2/V⋅s).2,41

Figure 5. Characteristics of Si-TFTs: Characteristics of top-gate geometry flexible TFTs using single-crystal-like n-type Si epitaxially grown on a polycrystalline Hastelloy. (a) Family curves of Ids-Vds for a typical TFT in a no-bending condition. (b) Transfer characteristics of a TFT in Ids (logarithmic scale) and

I ds vs. Vgs in a no-bending condition. (c) Transfer characteristics

comparison of TFTs in Ids (linear scale) vs. Vgs in no-bending and bend-down conditions. (d) Family curves of Ids-Vds for a typical TFT in a bend-down condition with a curvature radius R of ~3 cm. (e) Transfer characteristics of a TFT in Ids (logarithmic scale) and

I ds vs. Vgs in a

bend-down condition with a curvature radius R of ~3 cm. (f) Transfer characteristics comparison of TFTs in

I ds vs. Vgs in no-bending and bend-down conditions.

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4. CONCLUSIONS In summary, we have demonstrated flexible single-crystal-like Si on metal substrates by direct deposition and confirmed crystallographic evolution from poly- to nearly single crystalline structure using several characterization methods.

Thickness and doping control that were

previous long-standing issues with single-crystal-like Si thin films have been overcome. TFT devices have been fabricated with these Si films through a p-n junction having thin and low phosphorus-doped Si for channel isolation. Flexible TFT devices made using the single-crystallike Si show exceptional performance characteristics, including µFE ~200 cm2/V-s. Threshold voltage and current on/off ration are VT ~ -0.7 V and Ion/Ioff ~ 106, respectively.

These

groundbreaking results are a significant enhancement in performance in comparison with conventional TFT devices. The R2R thin film growth processes and device fabrication used in this work are completely compatible with low-cost thin film electronics processes. Large-area direct deposition of (001)-oriented Si thin films on flexible substrates with high mobility and availability of both n- and p-type Si enables flexible CMOS technology. This approach – i.e., direct epitaxy and device fabrication – can also be employed for nearly-single-crystalline thin films of other semiconductor materials and devices such as III-V thin film photovoltaics42,43 on metal tape via R2R deposition.

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ASSOCIATED CONTENT Supporting information (1) Schematic illustration of atomic configurations projected on (001) basal planes for crystal structures of Si and Ge (diamond structure), CeO2 (fluorite structure), LaMnO3 (orthorhombic perovskite structure), and MgO (rock-salt structure) (Figure S1); (2) X-ray diffraction pole figures (PFs) of planes parallel with (110) plane for the buffer layers of MgO, LaMnO3, CeO2, and Si (Figure S2); (3) Simulated transfer characteristics (Ids-Vgs) of nonworking transistor assuming a heavily auto-doped single-crystal-like Si thin-film channel using 2-dimensional technology computer aided design (2D TCAD) (Figure S3); (4) Simulated family curves (IdsVds) of a working transistor based on a single-crystal-like Si thin-film channel using 2-D TCAD (Figure S4);

(5) Current-voltage (I-V) characteristics of gate and source representing gate

leakage current (Figure S5); (6) 1-dimensional SRIM (stopping and range of ions in matters) simulation and fabrication process for optimization of ion implantation process in source and drain region using P+ ions in Si film with a SiO2 cap layer (Figure S6).

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AUTHOR INFORMATION Corresponding authors *E-mail: [email protected] (J.-H.R.) *E-mail: [email protected] (V.S.) Present address University of Houston, Department of Mechanical Engineering, University of Houston N207 Engineering Bldg 1, 4726 Calhoun Rd, Houston, TX 77204-4006

Author contributions These authors contributed equally to this work

┴

Notes The authors declare no competing financial interests.

ACKNOWLEDGMENTS This study was supported partly by the Texas Center for Superconductivity at the University of Houston (TcSUH).

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