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High-Performance Polymer Semiconductor-Based Nonvolatile Memory Cells with Nondestructive Read-Out Jia Sun, Min Je Kim, Myeongjae Lee, Dain Lee, Seongchan Kim, Jong-Hyun Park, Sungjoo Lee, BongSoo Kim, and Jeong Ho Cho J. Phys. Chem. C, Just Accepted Manuscript • DOI: 10.1021/acs.jpcc.7b08798 • Publication Date (Web): 06 Oct 2017 Downloaded from http://pubs.acs.org on October 16, 2017

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The Journal of Physical Chemistry

High-Performance Polymer Semiconductor-Based Nonvolatile Memory Cells with Nondestructive Read-Out Jia Sun,1,3† Min Je Kim,1† Myeongjae Lee,4 Dain Lee,1 Seongchan Kim,1 Jong-Hyun Park,4 Sungjoo Lee,1 BongSoo Kim,5,* Jeong Ho Cho1, 2* 1

SKKU Advanced Institute of Nanotechnology (SAINT), 2School of Chemical Engineering, Sungkyunkwan University, Suwon16419, Korea 3 Hunan Key Laboratory for Super Microstructure and Ultrafast Process, School of Physics and Electronics, Central South University, Changsha, Hunan 410083, P. R. China 4 Department of Chemistry, Korea University, Seoul 02841, Republic of Korea 5 Department of Science Education, Ewha Womans University, Seoul 03760, Republic of Korea †

J. Sun and M. J. Kim contribute equally to this work.

*Corresponding authors: J. H. Cho ([email protected]) and B. Kim ([email protected]) Abstract In this manuscript, the fabrication of polymer nonvolatile memory cells based on one-transistorone-transistor (1T1T) device geometries is reported. A spin-coated diketopyrrolopyrrole (DPP)-based polymer semiconductor was used as the active channel layer for both the control transistor (CT) and memory transistor (MT); thermally-deposited gold nanoparticles (Au NPs) were inserted between the tunneling and blocking gate dielectrics as a charge-trapping layer of the MT. In the 1T1T memory cell, the source electrode of the CT was connected to the gate electrode of the MT, while the drain electrode of the MT was connected to the gate electrode of the CT. The reading and writing processes of the memory cells operated separately, which yielded a nondestructive read-out capability. The fabricated 1T1T polymer memory cells exhibited excellent device performances with a large memory window of 16.1V, a high programming-erasing current ratio>103, a long retention of 103s, a cyclic stability of 500 cycles, and a 2bitdata storage capability. The proposed device architecture provides a feasible method by which to achieve high-performance organic nonvolatile memory.

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INTRODUCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Organic electronics have attracted significant attention due to their low manufacturing costs, facile processing, mechanical flexibility, suitability for large-area fabrication, and tunable optoelectronic properties.1-7 Many different types of organic electronic devices have been demonstrated as being very promising for the development of modern electronics including displays,8 logic circuits,9 sensors,10 and memory devices.11-12 In particular, organic transistor-type nonvolatile memory devices are considered to be fundamental information storage components for future electronic systems.13-14 Recently, transistor-type memory devices have been widely investigated due to their excellent device performance, simple device structure, and facile integration into electric circuits.15-20 According to their operating mechanism, transistor-type memory devices are primarily classified as floating-gate (or charge-trapping), polymer electret, and ferroelectric memory devices.21-26 Among these, floating-gate memory devices are considered to be the most promising candidate systems to achieve ultimate nonvolatile memory due to their high speed operation, excellent reliability, and multi-level data storage. The device operation of floating-gate memory is based on charge trapping and de-trapping into a floating-gate, enabling threshold voltage tuning to differentiate between various data storage states.27 Within floating-gate devices, various chargetrapping materials have been introduced for efficient modulation of hysteresis behavior, such as metallic nanoparticles,28-29

organic/oxide

nanoparticles,13,

30-31

bio-molecules,32

and

two-dimensional

nanomaterials.33-34 To enable new functionalities in electronic devices for practical applications, the development of novel semiconducting materials and device architectures is important. Recently, diketopyrrolopyrrole (DPP)-based polymers have been widely used in various electronic device applications such as organic solar cells and field-effect transistors (FETs) due to the highly planar nature of the DPP-polymer backbone allowing for efficient intramolecular and intermolecular charge transport and excellent stability.35 For example, polymeric solar cells with DPP-based copolymers have demonstrated high power conversion efficiency (PCE) over 8%.36-38 Excellent charge carrier mobility over 1 cm2V-1s-1 has been obtained for DPP-based FETs.39-41 With regard to device structure, commercial random access memory (RAM) technologies are based on one-transistor one-capacitor (1T1C) memory cells,16 where the capacitor and transistor are used to store data and control access to memory, respectively. However, the stored data can be gradually destroyed during the read-out process because the writing and reading processes are not seperate.42 Furthermore, memory devices can be unintentionally programmed during the writing of adjacent memory transistors.43 These problems can be solved through integration of a memory transistor (in place of the memory capacitor) into the memory cell.44 In this paper, the fabrication of polymer memory cells with one-transistor-one-transistor (1T1T) structures is demonstrated. The 1T1T memory cells were composed of a control transistor (CT) and a memory transistor (MT). The unique property of this device was that writing and reading processes were operated separately, ensuring nondestructive read-out capability. A DPP-based polymeric semiconductor (PDPPDT-QT) was used as the active channel layer of both transistors, while Au nanoparticles (Au NPs) ACS Paragon Plus Environment

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were inserted into the gate dielectric layer as a charge-trapping layer of the MT. The fabricated polymer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

1T1T memory cell exhibited excellent device performance with a high programming-erasing current ratio, long retention time, and multi-bit information storage capabilities.

EXPERIMENTAL SECTION The polymer 1T1T memory cells were fabricated on Si wafers. The substrates were sequentially cleaned with deionized water, acetone, and isopropanol and were dried using nitrogen gas. Then, 30-nmthick Au bottom gate electrodes were deposited via thermal evaporation through a shadow mask at a pressure of 10-6 Torr. A 50-nm-thick Al2O3 layer was subsequently deposited via ALD. The Al2O3layer was used as the blocking gate dielectric layer for both the CT and MT. The surface of the Al2O3 layer was cleaned via UV/ozone treatment; Au NPs as a floating-gate were deposited onto the MT region via thermal evaporation. Apoly-4-vinylphenol (PVP) precursor solution was prepared by dissolving the PVP (1 wt. %, Mw = 20,000 gmol-1) and poly(melamine-co-formaldehyde) (PMF, 0.5 wt. %, Mw = 511 gmol-1) into propylene glycol monomethyl ether acetate (PGMEA). A 10-nm-thick PVP tunneling layer of the MT was spin-coated and annealed at 180°C for 2 hours in a vacuum oven (~10-3 Torr).The CT region was blocked using Scotch tape during spin-coating of the PVP. The PDPPDT-QT semiconductor solution (5 mg/mL in chloroform) was then spin-coated onto the substrate at 2000 rpm for 30 s. Finally, 40-nm-thick Au sourcedrain electrodes for both the CT and MT were deposited using thermal evaporation. The W and L were 1000 and 100 µm, respectively. The source electrode of the CT was electrically connected to the gate electrode of the MT, while the drain electrode of the MT was electrically connected to the gate electrode of the CT. All electrical properties of the 1T1T memory cells were measured using a Keithley 2400 and 236 source/measure cells at room temperature under darkness.

RESULTS AND DISCUSSION Figure 1a shows the fabrication process for the DPP-based 1T1T memory cells. The 1T1T polymer memory cells were composed of (i) the CT to control MT access and (ii) the floating-gate MT for data storage. Compared to commercial 1T1C memory devices, the memory capacitor (MC) in the 1T1C memory cell was replaced with a floating-gate MT for the 1T1T memory cell.44 First, Au gate electrode patterns were thermally deposited onto the Si wafer via a metallic shadow mask. An Al2O3 blocking gate dielectric layer with a thickness of 50 nm was then formed via atomic layer deposition (ALD) onto the Au-patterned substrate. An Au NP charge trapping layer was deposited thermally onto the Al2O3 surface of the MT. Across-linked poly(4-vinylphenol) (cPVP) was coated onto the Au NP layer of the MT, while the CT region was blocked with Scotch tape. A 0.5 wt. % solution of poly(3-([2,2':5',2''-terthiophen]-5-yl)-2,5-bis(2decyltetradecyl)-6-(thiophen-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione)[PDPPDT-QT]

dissolved

in

chloroform was spin-coated onto the substrate. The chemical structure of PDPPDT-QT is presented in ACS Paragon Plus Environment


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Figure 1b, the synthesis of which is described in the Supporting Information. Finally, the Au source-drain 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

electrodes of both the CT and MT were thermally deposited through a metallic shadow mask. Figure 1c shows the circuit diagram of the 1T1T polymer memory cell. The source electrode of the CT was electrically connected to the gate electrode of the MT, while the drain electrode of the MT was connected to the gate electrode of the CT. Figure 1d illustrates the writing and reading voltages of the 1T1T polymer memory cell. In our device, the writing (programming or erasing) and reading processes were operated separately. In order to perform the writing process, a voltage of -20 V was applied to the word line (VWL), and the CT was turned on. This ensured that the voltage applied to the bit line (VBL) could be transferred to the gate terminal of the MT. Therefore, programming and erasing processes could be performed by applying a VBL of -20 V and +20 V, respectively. In order to perform reading processes, a voltage of +20 V was applied to the word line (VWL), and the CT was turned off. In this case, the VBL was disconnected from the gate terminal of the MT. The programmed states could be read via the word line because the word line was connected to the drain terminal of the MT. As a result, the 1T1T polymer memory cell was not only nonvolatile, but also nondestructive during the reading process, which is in contrast to typical 1T1C cells. In order to investigate the electrical properties of the 1T1T polymer memory cells, the transfer characteristics [drain current (ID) versus gate voltage (VG)] of the CT and MT were measured. All devices were measured in the dark at room temperature. Figure 2a shows the transfer curves of the PDPPDT-QTbased CT. The VG was swept from +30 to -30V at a fixed drain voltage (VD) of -20 V. The device exhibited an increase in ID with an increase in VG (negative), which was typical p-type transport. No obvious hysteresis was observed due to the absence of a floating-gate. The hole mobility (µh) at the saturation region was calculated using the following equation: ID = CS·µh·W·(VG-VTH)2/2L, where L and W are the channel length and width, respectively, CS is the specific capacitance of the gate dielectric layer, and VTH is the threshold voltage. The µh was 0.012 cm2V-1s-1, and the current on/off ratio (ION/IOFF) was 4.9 × 104. The value of VTH was around 4.4 V, which was much lower than those of typical DPP-based FETs due to the use of a high-k Al2O3 layer. These results indicate that PDPPDT-QT could serve as a channel material for the CT. Figure 2b shows the transfer curves of the PDPPDT-QT-based MT. The µh was dramatically enhanced (~0.1 cm2V-1s-1) compared to that of the CT; electron conduction was also observed. These results could be attributed to passivation of the Al2O3 surface with hydrophobic cPVP, which minimized the charge trapping of hydroxyl groups on the Al2O3 surface. Note that obvious hysteresis was observed in the forward and reverse curves, which became enlarged with an increase in the VG sweep range, indicating that charge trapping occurred upon the application of VG. As VG was swept from the positive to negative voltage direction, holes in the PDPPDT-QT channel became trapped in the Au NP floating-gate via tunneling through the cPVP tunneling gate dielectric layer.45 Under negative VG, a component of the charge carriers were accumulated and stored in the Au NPs, which resulted in a “programming state.” Due to the internal electric-field created by the trapped charges, the applied VG was partially screened, resulting in a negative ACS Paragon Plus Environment

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shift of VTH during the reverse sweep (from the negative to positive voltage direction). Under positive VG, the trapped holes were released and transferred back to the PDPPDT-QT channel, resulting in an “erased state.” To evaluate the memory performance of the MT, the memory window, representing the difference of VTH between forward and reverse sweeps, was calculated as shown in Figure 2c. As the VG sweep range increased from ±10 to ±20 V, the memory window gradually increased from 10.7 to 16.1 V due to a larger quantity of trapped charges in the Au NPs. The trapped charges were calculated using n= ∆VTH·CS/e, where ∆VTH is the threshold voltage shift, CS is the specific capacitance of the dielectric, and e is the elemental charge.46 As the VG sweep range was enlarged, the calculated trapped charge density increased from 7.36×1011cm-2(VG = ±10 V) to 1.24×1012cm-2 (VG = ±20 V). Multi-level data storage of the floating-gate MT was achieved by controlling both the amplitude and duration of the VG pulse applied during erasing. First, the erasing voltages were varied from +10 to +20 V, while the duration of the VG pulse was fixed to 1 s. Figure 2d shows the transfer curves of the MT with different erasing voltages, indicating that the ID level was modulated by tuning the erasing voltages. The ID at a certain VG increased as the erasing voltage increased from +10 to +20 V because a large quantity of trapped charges was released to the PDPPDT-QT channel. Second, the duration of the VG pulse for erasing was varied from 0.1 to 2 s, while the VG was fixed to +20 V. Figure 2e shows the transfer curves of the MT with different durations. A clear variation in memory window was observed as a function of duration (Figure 2f). The memory window gradually increased with an increase in the erasing pulse duration and became saturated at over 1 s. These results indicate the successful demonstration of multi-level data storage for our PDPPDT-QT-based floating-gate MT. An important performance parameter of the MT involved reliability during repeated programming and erasing steps, ensuring stable multi-level data storage for practical device applications.26 Static and dynamic current retention tests were thus performed. The retention and multi-level data storage capabilities were examined by applying programming (-20 V) and erasing (+10, +15, and +20V) VG pulses to the gate electrode of the MT. The duration of VG was 1s, and the ID level was measured at VG=0V and VD=-20 V. As shown in Figure 3a, the retention of ID was plotted as a function of time. Four different current levels were achieved and denoted as 0 (programmed at -20 V), 1(erased at +10 V), 2 (erased at +15 V), and 3 (erased at +20 V). Therefore, 2-bit data memory was demonstrated in a single floating-gate memory cell. Both the programming and erasing state currents of the MT were maintained for at least 103 s without significant degradation. During the entire measurement, the programming state current was measured to be ~10-10 A, and the programming (-20 V)-erasing (+20 V) state current ratio was larger than 103. Additionally, the dynamic switching stability was also evaluated by applying continuous programming-erasing cycles (Figure 3b). The four stable current levels of the floating-gate MT were maintained over 500 cycles, indicating good device stability and repeatability. These results demonstrated that the reported PDPPDT-QT-based floating gate MT exhibited great potential with regard to multi-level nonvolatile memory applications. To further investigate the stability and multi-level data storage of the 1T1T polymer memory cells, ACS Paragon Plus Environment


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multiple writing and reading processes were performed as shown in Figure 4. In the reported polymer 1T1T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

memory cell, two independent word lines were not required for operation, although two transistors were integrated. To control access to the MT, a voltage of -20 V (or+20 V) was applied to the word line for writing (or reading) operations (Figure 4a). At VWL= -20 V, the CT was turned on. In this case, the voltage applied to the bit line (VBL) could be transferred to access the MT. However, by applying a VWL of +20 V, the CT was turned off and the MT was unaffected by the VBL. Figure 4b shows the variation in ID of the MT during multiple programming (or erasing) and reading processes. The programming state at the lowest current level was obtained at VBL = -20 V under the VWL application of -20 V for writing. Under the VWL application of -20 V, three different voltages +10, +15, and +20 V were applied to the bit line (VBL) for the erasing states, which generated three distinct data levels in the 1T1T memory cell. All read-out processes of the stored data were performed at VBL = +20 V. Additionally, the four current levels were fully reliable by repeating the same writing and reading processes. In order to confirm the separate operation of writing and reading processes, VBL was applied at +20 V when VWL was biased at +20 V for reading. As shown in the yellow shaded area in Figure 4b, the 1T1T memory cell during reading was completely unaffected by the voltage applied to the bit line. Consequently, writing and reading processes were separated by introducing the MT (instead of the MC), and 2-bit data storage was achieved by precisely controlling the VBL.

CONCLUSIONS In summary, the fabrication of polymer 1T1T memory cells based on a DPP-based semiconducting polymer was successfully demonstrated as a channel layer for both the CT and MT. Writing and reading processes of the polymer 1T1T memory cells could operate separately, enabling non-destructive read-out processes. The fabricated polymer 1T1T memory cells exhibited excellent memory performance with a memory window >16 V, a high programming-erasing current ratio >103, a retention time >103 s, and a high operational stability>500 cycles. The described results demonstrate the large potential of polymer semiconductors as an active material for development of high performance memory cells.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website at DOI: Synthesis of PDPPDT-QT

AUTHOR INFORMATION Corresponding Author ACS Paragon Plus Environment

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*E-mail: [email protected]. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

*E-mail: [email protected]

Notes The authors declare no competing financial interest.

ACKNOWLEDGEMENTS This work was supported by the Center for Advanced Soft Electronics (CASE) under the Global Frontier Research Program, Korea (NRF-2013M3A6A5073177) and the Basic Science Program through the NRF funded by the Ministry of Education (NRF-2015R1D1A1A01058493 and 2017R1A4A1015400), Korea.



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(43) Zhao, Q.; Wang, H.; Ni, Z.; Liu, J.; Zhen, Y.; Zhang, X.; Jiang, L.; Li, R.; Dong, H.; Hu, W. Organic Ferroelectric‐Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half‐Selection Problem. Adv. Mater. 2017, 29, 1701907. (44) Das, S.; Appenzeller, J. Fetram. An Organic Ferroelectric Material Based Novel Random Access Memory Cell. Nano Lett. 2011, 11, 4003-4007. (45) Baeg, K. J.; Noh, Y. Y.; Sirringhaus, H.; Kim, D. Y. Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory. Adv. Funct. Mater. 2010, 20, 224-230. (46) Lee, D.; Hwang, E.; Lee, Y.; Choi, Y.; Kim, J. S.; Lee, S.; Cho, J. H. Multibit MoS2 Photoelectronic Memory with Ultrahigh Sensitivity. Adv. Mater. 2016, 28, 9196-9202.


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Figure 1. (a) Schematic fabrication procedure of a 1T1Tpolymer memory cell consisting of a control transistor and memory transistor based on a PDPPDT-QT semiconductor channel. (b) Chemical structure of PDPPDT-QT. (c) Electrical circuit diagram of the 1T1T polymer memory cell. (d) Table describing writing (programming and erasing) and read-out processes.



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Figure 2. (a) Transfer curve of the control transistor in the 1T1T memory cell. (b) Hysteresis behavior of the memory transistor in the 1T1T memory cell as a function of the VG sweep range from ±10 to ±20 V. (c) Memory window of the transfer curves as a function of VG sweep range. (d) Shift in the transfer curves after the application of various erasing VG for 1 s. (e) Shift in the transfer curves after the application of programming VG = -20 V for various durations. (f) Memory windows as a function of duration.


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Figure 3. (a) Retention times and (b) cyclic endurance tests of the 1T1Tpolymer memory cell.



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Figure 4. Dynamic behavior of the 1T1T polymer memory cells. (a) VWL (for controlling the CT) and VBL (for programming and erasing the MT) as a function of time. (b) Drain current as a function of time.


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