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Functional Inorganic Materials and Devices

High Resolution Inkjet Printed Oxide Thin Film Transistors with Self-Aligned Fine Channel Bank Structure Qing Zhang, Shuangshuang Shao, Zheng Chen, Vincenzo Pecunia, Kai Xia, Jianwen Zhao, and Zheng Cui ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b02390 • Publication Date (Web): 12 Apr 2018 Downloaded from http://pubs.acs.org on April 12, 2018

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ACS Applied Materials & Interfaces

High Resolution Inkjet Printed Oxide Thin Film Transistors with Self-Aligned Fine Channel Bank Structure Qing Zhang1, 4, 5, 6, Shuangshuang Shao1, Zheng Chen*, 1, 2, Vincenzo Pecunia3, Kai Xia3, Jianwen Zhao*, 1, Zheng Cui1 1

Printable Electronics Research Center, Suzhou Institute of Nano-tech and

Nano-bionics, Chinese Academy of Sciences, No. 398 Ruoshui Road, SEID, Suzhou Industrial Park, Suzhou, 215123, Jiangsu, PR China 2

MIIT Key Laboratory of Advanced Display Materials and Devices, Institute of

Optoelectronics and Nanomaterials, College of Material Science and Engineering, Nanjing University of Science and Technology, Nanjing, 210094, PR China 3

Jiangsu Key Laboratory for Carbon-Based Functional Materials & Devices, Institute

of Functional Nano & Soft Materials (FUNSOM), Joint International Research Laboratory of Carbon-Based Functional Materials and Devices, Soochow University, 199 Ren'ai Road, Suzhou, 215123, Jiangsu, PR China. 4

Shanghai Institute of Ceramics, Chinese Academy of Sciences, No. 585, Heshuo

Road, Jiading District, Shanghai, PR China 5

University of Chinese Academy of Sciences, No. 52, Sanlihe Road, Beijing, PR

China 6

Shanghai Tech University, No. 393, Huaxia Middle Road, Pudong New Area,

Shanghai, PR China KEYWORDS: inkjet printing, metal oxide, surface-energy pattern, self-aligned, PMSQ 1 ACS Paragon Plus Environment

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ABSTRACT A self-aligned inkjet printing process has been developed to construct small channel metal oxide (a-IGZO) thin-film transistors (TFTs) with independent bottom gates on transparent glass substrates. Poly(methylsilsesquioxane) (PMSQ) was used to pattern hydrophobic banks on the transparent substrate instead of commonly used self-assembled octadecyltrichlorosilane (OTS). Photolithographic exposure from backside using bottom gate electrodes as mask formed hydrophilic channel areas for the TFTs. IGZO ink was selectively deposited by an inkjet printer in the hydrophilic channel region and confined by the hydrophobic bank structure, resulting in the precise deposition of semiconductor layers just above the gate electrodes. Inkjet-printed IGZO TFTs with independent gate electrodes of 10 µm width have been demonstrated, avoiding completely printed channel beyond the broad of the gate electrodes. The TFTs showed on/off ratios of 108, maximum mobility of 3.3 cm2 V-1 s-1, negligible hysteresis and good uniformity. This method is conductive to minimizing the area of printed TFTs so as to the development of high resolution printing displays.

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1. INTRODUCTION Printable display is gaining momentum recently with the development of solution type of organic light emitting diode (OLED) materials. While the OLED pixels are now printable, it would be ideal if the backplane thin-film transistor (TFT) array can be printable as well. Research works along this direction have been ongoing in recent years.1-7 With the development of novel semiconductor inks, printing methods and post-treatment techniques, performances of printable TFTs based on amorphous metal oxide, organics, carbon nanotubes and two dimension materials, have been significantly improved.7-18 Printed amorphous metal oxide TFTs exhibited high on/off ratios (up to 108), lower off currents (less than 10-14 A) and excellent uniformity, and it is possible to modulate mobility and threshold voltage of printed TFT by tuning the ratios of ingredients in metal oxide inks.19 Printed metal oxide TFTs are now regarded as one of candidates for constructing backplane driving circuits for displays.15 As the driving TFTs occupy part of a pixel in a display, it would be desirable if the TFTs take as less area as possible in order to maximize the OLED emission area. It is known that the operation speed of TFT directly depends on its channel length, so TFTs with shorter channel length have been developed significantly.20-26 Nevertheless, the area of printed TFTs has been rarely concerned.5 If inkjet printing is to be employed for making the TFTs, measures need to be taken to minimize the area of printed active layer in order to reduce the overall size of a TFT. However, inkjet printing is inherently of low resolution with typical printed features at 20-50 µm.6, 27 There is then a conflict between large printed ink drops and required small area TFTs. 3 ACS Paragon Plus Environment


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Some strategies have been proposed to improve the resolution of inkjet printing patterns, including the use of small ink drop volume of 1 picoliter printer nozzles or electrohydrodynamic printing28-30. These approaches have their own limitations such as nozzle clogging and low throughput. There are also strategies employing surface energy contrast prior to printing or utilizing coffee ring effect, etc.27, 31-37 However, most of them usually require extra templates or masks, or complicated fabrication processes in order to accurately deposit semiconductor inks on desired region. Therefore, it is imperative to develop some facile processes to print semiconductor channels with high resolution and high registration accuracy.1 In this work, a new approach has been developed, which utilized pre-deposited gate electrodes as self-aligned mask to form wettability contrast pattern for printed semiconductor channel. Poly(methylsilsesquioxane) (PMSQ) solution, which is stable under high temperature, optically transparent and low cost to produce, was used to pattern bank structures with high hydrophobic contrast to the alumina gate dielectric region. The printed IGZO semiconductor channels were precisely aligned to the gate electrodes of 10 µm width. The inkjet printed TFTs with independent bottom gates were achieved, which exhibited on/off ratios of 108 and maximum effective mobility of 3.3 cm2 V-1 s-1. To the best of our knowledge, this is the first report about printing IGZO TFTs of independent bottom gate with such narrow channel by a standard 10 pL inkjet printer. 2. EXPERIMENTAL SECTION 2.1 Preparation of Inks. 4 ACS Paragon Plus Environment

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The semiconductor ink was based on the indium gallium zinc oxide (IGZO) precursor solution with molar ratio of 6: 1: 2 (In : Ga : Zn). The precursor solution was prepared by dissolving In(NO3)3·xH2O (99.99%, Sigma-Aldrich), Zn(NO3)2·xH2O (98%, Acros Organics), and Ga(NO3)3·xH2O (99.9%, trace metal basis, Sigma-Aldrich) in deionized water. The as-received chemicals were used without any further purification. Before printing, the ink was stirred vigorously for 120 min at room temperature and filtered with a pore size of 0.45 µm. The hydrophobic layer was prepared from PMSQ solution which was synthesized according to the previously reported work.38, 39 Formic acid (5.08 g) was dissolved

in

deionized

water

(19.8

g)

and

added

to

a

solution

of

methyltrimethoxysilane (0.37 mol) in propylene glycol monomethyl ether acetate (PGMEA) (25 g). After 30 min stirring at room temperature, the mixture was heated at 70°C for 60 min to initiate the polycondensation reaction. Finally, highly viscous PMSQ prepolymer was obtained after removing the small molecules including water, formic acid, methanol and solvent by distillation under reduced pressure at 70°C. The PMSQ prepolymer was dissolved in PGMEA solvent and 0.2 g ml-1 solution was used for the fabricating 170 nm PMSQ thin film by spin coating (4000 rpm, 60 s) with annealing at 400°C for 60 min in air. 2.2 Fabrication of Thin Film Transistors. Fig. 1 shows schematically the fabrication sequence for the bottom-gate top-contact TFT. A 150 nm thick MoNb alloy gate electrode was deposited and patterned via magnetron sputtering and photolithography. Then 150 nm thick alumina (AlOx) was 5 ACS Paragon Plus Environment


deposited by atomic layer deposition (ALD) at 250oC as dielectric layer (Fig. 1a). A 170 nm thick PMSQ layer of hydrophobic property was spin-coated on top of the dielectric layer which was patterned from back side of glass substrate by photolithography and dry etching to reveal the underneath alumina surface which was the channel region of TFT (Fig. 1b).

Figure 1. Schematic illustration of the fabrication steps for bottom-gate top-contact thin film transistor of printed channel, utilizing the pre-deposited gate electrode to form self-aligned wettability-contrast patterns: (a) metallic gate electrode/dielectric layer formed on glass substrate; (b) photolithographic exposure from backside using bottom gate electrode as mask; (c) wettability-contrast pattern after etching the hydrophobic film, removing photoresist, 350°C annealing and UV-ozone treatment; (d) depositing oxide semiconductor in hydrophilic region to form channel of TFT; (e) TFT device after deposition of source/drain electrodes. A further annealing in air at 350°C for 60 min and exposure to UV-ozone for 5 6 ACS Paragon Plus Environment

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min improved hydrophilic property of alumina surface, in order to establish the wettability contrast between the channel region and the surrounding PMSQ bank (Fig. 1c). IGZO precursor ink was then printed onto the channel region by an inkjet printer with 10 pL piezoelectric nozzle (Dimatix, DMP 2831) and annealed at 350°C for 120 min in ambient condition (Fig. 1d). Finally, 150 nm MoNb alloy was deposited by sputtering and patterned by photolithography and lift-off to form the source/drain (S/D) electrodes (Fig. 1e). Alternatively, the hydrophobic pattern could be prepared by self-assembled octadecyltrichlorosilane (OTS) which was formed by evaporating OTS in an oven of 120oC for 120 min. The patterning of PMSQ and OTS layer was the same as patterning of SiO2 using optical exposure of photoresist and CHF3 gas reactive ion etching (RIE). 2.3 Material and Device Characterization. The hydrophobicity was characterized by measuring water contact angles using an optical contact angle & interface tension meter (USA KINO). The transparency of PMSQ film was checked by UV-Vis spectrum measurement. The chemical structure of modified AlOx surface was examined by X-ray photoelectron spectroscopy (XPS, Escalab 250Xi spectrometer) using a monochromatic Al Kα X-ray source with an overall energy space of ∆E=0.1 eV. All the XPS peaks were calibrated by taking C 1s reference at 284.6 eV. Atomic force microscope (AFM, Veeco Nanoscope digital instruments) was used to characterize surface morphology of the modified AlOx surface and to measure the length of printed oxide for the actual channel width (W). The channel region of printed oxide active layer was examined using Energy 7 ACS Paragon Plus Environment


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dispersive spectroscopy (EDS) function in Scanning electron microscopy (SEM, Hitachi S-4800). The electrical properties of printed IGZO-TFTs were measured using Keithley 4200 semiconductor analyzer in a dark box at ambient condition. Linear field effect mobility (µlin) and threshold voltage (Vth) were extracted from the TFT transfer curves using the following expression μ =

௅

ௐ

×஼

ଵ

೚ೣ ௏೏ೞ

×൬

ௗூ೏

ௗ௏೒

൰ at Vds of 1 V. The

capacitance per unit area (Cox) of the AlOx dielectric layer is about 0.0606 µF cm−2 measured by Keithley 4200 Capacitance-Voltage Unit. The channel length (L) was set at 5 µm for the bottom gate electrodes of 10 µm width. 3. RESULTS AND DISCUSSION 3.1 Confinement of Semiconductor Ink by Self-Aligned Hydrophobic Banks. The major disadvantage of inkjet printing TFT is the low resolution of inkjet printing itself. Our recent work has demonstrated that the diameter of inkjet printed metal oxide dots can be controlled in the range of 35-40 µm by modifying the surface energy of dielectric layers together with tuning the viscosity of metal oxide inks.5 However, it is not easy to further decrease the size of printed dots using this approach. There have been reports of confining ink drops to a specific region by playing the surface energy of substrates.32-34, 37 The key technology for this approach is to create high contrast between hydrophobic and hydrophilic regions on a substrate prior to inkjet printing, in order to confine the ink drop only in the hydrophilic region. Therefore, the choice of hydrophobic materials is critical. Most hydrophobic polymers, including commonly-used photoresists, are not suitable because they cannot endure 8 ACS Paragon Plus Environment

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the high annealing temperature (350oC) necessary for oxide semiconductor layer. It was found that only the self-assembled OTS and PMSQ were up to the role. Fig. 2 shows the water contact angles of alumina, self-assembled OTS and PMSQ thin film on a glass substrate. Both OTS and PMSQ thin films exhibited high hydrophobicity with water contact angles around 96° (Fig. 2a and 2b), which are originated from the high density of alkyl groups (Fig. S1).38, 40 As-prepared alumina surface is intrinsically hydrophilic with water contact angle less than 10° as shown in Fig. 2c. Inkjet printed metal oxide ink drop can spread well on it, so as to form homogeneous thin film. The wettability contrast could be created between PMSQ, or OTS surface, and the alumina surface, so that the oxide ink drop would be confined to the alumina surface which was the gate dielectric region. However, the gate dielectric layer had to undergo a patterning process which required coating photoresist and photolithography. It was found that the hydrophilicity of alumina surface could change once photoresist (PR) was coated on it, even after the PR layer was removed by solvent wash. Fig. 2d shows water contact angle (~40°) after patterning the alumina layer and washing off the remaining PR. The same was true for simply coating and removing PR on the alumina surface (Fig. 2e), even after 350oC annealing process (Fig. 2f), which means that once the hydrophilic surface of alumina is coated with photoresist tiny residuals remaining on the surface can alter its hydrophilicity no matter how thorough the PR layer is removed. The consequence was that the wettability contrast between alumina and surrounding PMSQ or OTS was greatly reduced. 9 ACS Paragon Plus Environment


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Figure 2. Water contact angles on different surfaces: (a) OTS-assembled AlOx thin film, (b) PMSQ thin film, (c) freshly prepared AlOx thin film, (d) the exposed alumina surfaces undergoing etching and PR removing, (e) the AlOx surface undergoing PR coating and PR removing, without etching process, and (f) the exposed AlOx thin film surface after 350oC annealing. To restore the hydrophilic property of alumina surface, the PR contaminated alumina surface was treated with UV-ozone exposure. The trouble was that the UV-ozone treatment could also make OTS and PMSQ film surface less hydrophobic. Tab. 1 lists the changes of water contact angles at different durations of UV-ozone exposure on alumina, OTS and PMSQ surfaces. After 5 min UV-ozone treatment, the contact angle of alumina surface reduced to ~0° and its hydrophilicity was fully restored, whereas the contact angles of OTS and PMSQ were also reduced to 68°±2° and 80°±1°. After 15 min UV-ozone treatment, the contact angle of OTS decreased to ~0°, whereas it was still ~64° for PMSQ. The endurable hydrophobic property of 10 ACS Paragon Plus Environment

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PMSQ was thought due to its silica-organic hybrid structure which protects the organic groups against high temperature and UV-ozone treatment.41 Table 1. Water contact angles on different surfaces with different durations of UV-ozone treatment. N. D: blow detection limit; Alumina: the alumina surfaces after undergoing etching and PR removing. UV-ozone

0 min

5 min

10 min

15 min

20 min

Alumina

40°±1°

N. D.

N. D.

N. D.

N. D.

OTS

96°±4°

68°±2°

58°±1°

N. D

N. D.

PMSQ

96°±2°

80°±1°

69°±3°

64°±2°

58°±1°

Fig. 3 shows the optical images of IGZO ink drop on gate dielectric channel region of alumina without hydrophobic confinement bank (Fig. 3a), with self-assembled OTS bank plus UV-ozone treatment (Fig. 3b) and with PMSQ confinement bank plus UV-ozone treatment (Fig. 3c). It is obvious that the ink drop spontaneously spread on alumina dielectric layer with the diameter ranged from 60-100 µm if there was no hydrophobic confinement. With OTS confinement the ink drop was mainly in the channel region though not very uniform. The PMSQ confinement gave the best result. The ink drop was completely and uniformly confined within the channel region. When 50 nm PMSQ film was used, there are about 100 nm steps in printed region, but the ink drops were also confined well, as shown in Fig. 3d. It suggested that the confinement was mainly due to the difference in surface energy. The impact of the step can be neglected, because the drop diameter (few tens micrometer) is far larger than the dimension of the step (100 nm). 11 ACS Paragon Plus Environment


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Figure 3. The structures of dielectric layers modified with OTS and PMSQ patterns, and the optical images of printed metal oxide thin films on dielectric layers with different modifications: (a) without hydrophobic confinement bank, (b) with self-assembled OTS bank, (c) with 170 nm and (d) 50 nm thick PMSQ film bank. Besides its stable hydrophobic property, PMSQ has other advantages. The PMSQ solution can be easily produced at low cost through low temperature synthesis. After thermal cross-linking, PMSQ is chemically resistant to most organic solvents (such as methylbenzene, alcohol, chloroform), thus is stable during inkjet printing of solvent-based semiconductor inks.38 Due to its silica-organic hybrid structure, PMSQ can endure high temperature up to 400oC.39 In addition, it is transparent at wavelength over 300 nm (Fig. S2), which makes it suitable for optical exposure of photoresist from backside, hence enabling the self-aligned process in this work. Therefore, PMSQ was chosen to construct the self-aligned hydrophobic banks in order to create wettability contrast for inkjet printing of oxide semiconductor into the TFT channel region. Fig. 4a and 4b show the optical image and SEM image of inkjet printed single TFT, where the confinement of IGZO ink is shown in the inset images. The thickness and morphologies of metal oxide thin film in device channel were also characterized 12 ACS Paragon Plus Environment

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by AFM. As shown in Fig. 4c and 4d, the printed metal oxide is homogeneous with the average thickness of 25.6 nm and length of 57 µm. In order to confirm that the IGZO ink was indeed only deposited within the channel region, energy dispersive spectroscopy (EDS) was used to detect the elements at three points (A, B, C) shown in the inset SEM image of Fig. 4b. Indium and zinc elements were observed at A and B but not at C (see Tab. S1). The result suggested that the printed IGZO ink was precisely restricted within the 10 µm wide region of gate electrode, though an inkjet printer with a 10 pL nozzle was used which generally produces more than 50 µm size of ink drops.

Figure 4. (a) Optical image and (b) SEM image of a printed IGZO TFT, and (c) optical image and AFM image, and (d) topographical profiles of an IGZO thin film in device channel. 13 ACS Paragon Plus Environment


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3.2 Performance of Printed IGZO TFTs with Short Channel Length and Independent Bottom Gates on Glass Substrates. The IGZO precursor ink needs high temperature annealing in order to become amorphous semiconductor. Normally the high temperature annealing takes place after the oxide semiconductor ink is printed into the channel region. However, it was found that photoresist patterning and dry etching on the alumina dielectric layer could introduce contamination which was detrimental to the TFT performance. Fig. 5a shows the transfer curve of a printed IGZO TFT due to the contamination. An additional thermal treatment at 350oC for 60 min prior to UV-ozone exposure of alumina and inkjet printing of oxide semiconductor ink could significantly improve TFT performance as shown in Fig. 5b that printed devices showed small hysteresis, high on/off ratio and mobility of 3.3 cm2 V-1s-1.

Figure 5. Typical transfer curves of printed IGZO-TFT without heat treatment of alumina (a) and with the 350oC annealing prior to UV-ozone exposure of alumina and inkjet printing of oxide semiconductor ink (b). In order to evaluate the effect of additional 350oC annealing on the alumina surface, its morphologies and constituents were studied by AFM and XPS. The 14 ACS Paragon Plus Environment

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root-mean-square (RMS) roughness of freshly prepared alumina dielectric layer was about 1.10 nm (Fig. 6a). However, it increased to 3.45 nm after photoresist patterning and dry etching (Fig. 6b). The annealing at 350oC for 60 min reduced the roughness to 0.7 nm (Fig. 6c). The XPS spectra revealed that fluorine (F) elements were introduced to the alumina surface after dry etching with CHF3 gas, as shown by the F1s peaks in Fig. 6d before and after etching, which agreed well with the previous report.42 After annealing, no obvious F 1s peak was seen, indicating that the fluorine residuals were removed and the surface roughness of alumina were also greatly reduced (Fig. 6c), which was ascribed to surface diffusion at high temperature.43, 44 Fluorine doping in oxide semiconductor has been reported to improve mobility and stability of device.45, 46

In addition, it was also reported that a HfO2 gate dielectric with a fluorinated

surface can suppress carrier trapping. 47, 48 Therefore, we believe that the significantly enhanced TFT performance is due to smoother dielectric layer, which improved the interface property between metal oxide and dielectric layer.



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Figure 6. AFM images of the 5 × 5 µm2 AlOx surface area (a) before and (b) after etching, and (c) after etching and annealing at 350oC for 60 min. (d) XPS F 1s spectra of the AlOx with different treatment. Finally, printed IGZO TFTs with independent bottom gates were fabricated in large scale. All the electrodes were made by photolithography and the oxide semiconductor layer was deposited by inkjet printing. With the aforementioned self-aligned process, the IGZO precursor ink was precisely confined in the channel region above the bottom gate electrode (Fig. S3a and S3b), followed by patterning of source-drain electrodes (Fig. S3c and S3d). Fig. 7 shows the transfer and output characteristics of 30 inkjet printed IGZO-TFTs with gate electrode width of 10 µm and channel length of 5 µm. The TFTs exhibited effective mobility of 2.6-3.3 cm2 V-1 16 ACS Paragon Plus Environment

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s-1, on/off ratio about 108 and threshold voltage of 2-4 V. The statistical data shown in Fig. 7c and 7d demonstrated good uniformity of printed IGZO-TFTs because of the homogeneous channel lengths and smooth metal oxide thin films.

Figure 7. Typical transfer (a) and output curves (b) of the printed IGZO TFTs with independent gate electrodes on a glass substrate; statistical distributions of effective mobility (c) and threshold voltages (d) for 30 TFTs. 3.3 Bias Stability of Printed IGZO TFTs. The stability of printed oxide TFT was tested in air under positive gate bias stress (PBS), negative gate bias stress (NBS) and negative bias illumination stress (NBIS), respectively. The bias stresses on the measured device were 20 V gate voltage plus 1 V drain voltage for PBS, -20 V gate voltage plus 1 V for NBS and NBIS, while source electrode was grounded. A green light (λ = 505 nm) at a power density of 0.2 mWcm-2 was applied in negative bias illumination stress (NBIS) testing. Before a stress test, 17 ACS Paragon Plus Environment


the device recovered in the dark to eliminate the effect of the previous stress test. Transfer characteristics of a printed IGZO-TFT after bias stress are shown in Fig. 8a-c, and the threshold voltage shifts as a function of stress duration extracted from these transfer curves are represented in Fig. 8d.

Figure 8. Transfer characteristics of a printed IGZO TFT without passivation layer: (a) under positive gate bias stress (PBS), (b) under negative gate bias stress (NBS), (c) under negative bias illumination stress (NBIS). The results show that there are negligible changes in mobility under the three kinds of bias stress, but the threshold voltage shifts can be obviously observed. After 2000 s duration of PBS, the shift of threshold voltage has been slow down and is a positive offset of 1.2 V in total. The positive shift of threshold has been attributed to electron trapping in the interface between dielectric layer/channel layer, or electron injection into the gate dielectric layer.49 The shift value is very small as far as a 18 ACS Paragon Plus Environment

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printed TFT without passivation is concerned, suggesting that the printed device has a fairly good interface for PBS stability. The threshold voltage has a reverse offset about -2 V after 2000 s of NBS which is slightly higher than the shift value under PBS. Because the back channel of TFT was not passivated, it was suggested that the negative Vth shift was attributed mainly to the effect of moisture absorption.50 By adding light illumination, a lager threshold voltage offset was observed about -6.1 V in the NBIS testing. The large threshold voltage shift has been investigated in some reports and can be attributed to a plausible mechanism of photogenerated holes trapped in the interface of dielectric layer/channel layer.49 Most reported TFTs by solution process are based on sharing a common bottom gate electrode which in most cases is the highly doped conductive silicon substrate. For such a configuration, many practical circuits which require more than one TFT would not be possible. The self-aligned approach in this work has enabled the fabrication of fine channel oxide TFTs with independent bottom gate configuration, thus opened possibilities of constructing more complicated circuitry by inkjet printed TFTs. It worth noting that the inkjet printing was used to selectively deposit semiconductor ink only onto the channel region of individual TFTs, to avoid leakage current between gate electrode and channel, as well as channels from two TFTs (Fig. S4). As illustrated in Fig. S4, such leakage current would exist if overall hydrophilic region was coated.



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4. SUMMARY A self-aligned inkjet printing process has been developed to construct fine channel metal oxide (a-IGZO) thin-film transistors (TFTs) with independent bottom gate on transparent glass substrates. The process was based on the wettability contrast between

the

TFT

channel

region

and

surrounding

bank

structure.

Poly(methylsilsesquioxane) (PMSQ) was used to pattern hydrophobic banks on a transparent glass substrate, instead of commonly used self-assembled OTS layer. The PMSQ bank structure was patterned by photolithographic exposure from backside using the bottom gate electrode of 10 µm width as mask to form hydrophilic channel areas. IGZO ink was selectively deposited by an inkjet printer into the hydrophilic channel region and confined by the hydrophobic bank structure, resulting in the precise deposition of semiconductor layers just above the gate electrodes. The TFTs showed on/off ratios of 108, maximum mobility of 3.3 cm2 V-1 s-1, negligible hysteresis and good uniformity.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website. Chemical structures of PMSQ and OTS, UV-Vis transmittance of PMSQ on glass substrates, element contents detected in different areas signed in Fig. 4b, optical images of printed IGZO TFT arrays, and an example illustration on leakage current. AUTHOR INFORMATION 20 ACS Paragon Plus Environment

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Corresponding Authors *E-mail: [email protected]. *E-mail: [email protected]. ORCID Zheng Chen: 0000-0002-2538-9142; Jianwen Zhao: 0000-0002-5548-5469 Notes The authors declare no competing financial interest.

ACKNOWLEDGEMENTS This work was supported by the National Key R&D Program of “Strategic Advanced Electronic Materials” (2016YFB0401100), the Basic Research Program of Jiangsu Province (BK20161263, SBK2017041510), the Science and Technology Program of Guangdong Province (2016B090906002), Basic Research Programme of Suzhou Institute of Nanotech and Nano-bionics (Y5AAY21001), and the National Natural Science Foundation of China (61750110517).

REFERENCES (1) Fukuda, K.; Someya, T. Recent Progress in the Development of Printed Thin-Film Transistors and Circuits with High-Resolution Printing Technology. Adv.

Mater. 2017, 29, 1602736. (2) Zou, J. P.; Zhang, K.; Li, J. Q.; Zhao, Y. B.; Wang, Y. L.; Pillai, S. K. R.; Demir, 21 ACS Paragon Plus Environment


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Table of Contents


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Figure 1. Schematic illustration of the fabrication steps for bottom-gate top-contact thin film transistor of printed channel 99x61mm (300 x 300 DPI)

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Figure 2. Water contact angles on different surfaces 86x88mm (300 x 300 DPI)


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Figure 3. The structures of dielectric layers modified with OTS and PMSQ patterns, and the optical images of printed metal oxide thin films on dielectric layers with different modifications 41x11mm (300 x 300 DPI)



Figure 4. (a) Optical image and (b) SEM image of a printed IGZO TFT, and (c) optical image and AFM image, and (d) topographical profiles of an IGZO thin film in device channel. 127x101mm (300 x 300 DPI)


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Figure 5. Typical transfer curves of printed IGZO-TFT without heat treatment of alumina (a) and with the 350oC annealing prior to UV-ozone exposure of alumina and inkjet printing of oxide semiconductor ink (b). 56x20mm (300 x 300 DPI)



Figure 6. AFM images of the 5 × 5 µm2 AlOx surface area (a) before and (b) after etching, and (c) after etching and annealing at 350oC for 60 min. (d) XPS F 1s spectra of the AlOx with different treatment. 130x106mm (300 x 300 DPI)


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Figure 7. Typical transfer (a) and output curves (b) of the printed IGZO TFTs with independent gate electrodes on a glass substrate; statistical distributions of effective mobility (c) and threshold voltages (d) for 30 TFTs. 117x86mm (300 x 300 DPI)



Figure 8. Transfer characteristics of a printed IGZO TFT without passivation layer: (a) under positive gate bias stress (PBS), (b) under negative gate bias stress (NBS), (c) under negative bias illumination stress (NBIS). 117x86mm (300 x 300 DPI)


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High Resolution Inkjet Printed Oxide Thin Film ... - ACS Publications

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