LETTER pubs.acs.org/NanoLett
How Good Can Monolayer MoS2 Transistors Be? Youngki Yoon,† Kartik Ganapathi,† and Sayeef Salahuddin* Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, United States ABSTRACT: Monolayer molybdenum disulfide (MoS2), unlike its bulk form, is a direct band gap semiconductor with a band gap of 1.8 eV. Recently, field-effect transistors have been demonstrated experimentally using a mechanically exfoliated MoS2 monolayer, showing promising potential for next generation electronics. Here we project the ultimate performance limit of MoS2 transistors by using nonequilibrium Green’s function based quantum transport simulations. Our simulation results show that the strength of MoS2 transistors lies in large ONOFF current ratio (>1010), immunity to short channel effects (draininduced barrier lowering ∼10 mV/V), and abrupt switching (subthreshold swing as low as 60 mV/decade). Our comparison of monolayer MoS2 transistors to the state-of-the-art IIIV materials based transistors, reveals that while MoS2 transistors may not be ideal for high-performance applications due to heavier electron effective mass (m* = 0.45m0) and a lower mobility, they can be an attractive alternative for low power applications thanks to the large band gap and the excellent electrostatic integrity inherent in a two-dimensional system. KEYWORDS: Molybdenum disulfide (MoS2), layered materials, field-effect transistor, quantum transport, NEGF, device physics
M
olybdenum disulfide (MoS2), a layered transition metal dichalcogenide, has several interesting electrical, mechanical, and optical properties.1 Apart from being widely used as a dry lubricant for automobiles due to its low friction properties, MoS2 has been explored for applications in photovoltaics2 and photocatalysis3,4 for energy conversion. Structurally, MoS2 is a stack of planes where covalently bonded SMoS atoms are closely packed in a hexagonal arrangement, and the adjacent planes are held together by van der Waals interactions.5 These weak interlayer interactions, in contrast to strong intralayer bonding, make synthesis of monolayers of MoS2 possible by micromechanical exfoliation from bulk crystalline MoS257 identical to the fabrication of graphene from graphite.8 Recent experimental studies on few layers of MoS2 using optical absorption and photoluminescence show that, while bulk MoS2 is an indirect band gap semiconductor with a band gap (Eg) of 1.29 eV,9 at monolayer thickness (0.65 nm),10 MoS2 transitions to a direct band gap semiconductor with Eg = 1.8 eV,5,6 thereby corroborating earlier ab initio based calculations that predicted a similar band gap.11 High thermal stability of MoS2 and the absence of dangling bonds,7 coupled with the presence of significant band gap in a 2-D material render monolayer MoS2 as an attractive candidate for switching applications, unlike graphene wherein the absence of band gap inhibits its use despite large reported mobilities (200000 cm2/(V s)).12 While monolayer MoS2 has previously exhibited poor mobility (107) and subthreshold swing (74 mV/decade) have been demonstrated experimentally.7 While rapid progress in fabrication of short-channel MoS2 transistors can be expected, it is of significant technological relevance to estimate the ultimate performance limit that can be achieved in such devices before an aggressive pursuit of miniaturization begins. In this Letter, we attempt to answer this question by using rigorous quantum transport simulations and view their performance in light of some of the competing nonsilicon technologies to assess the viability of monolayer MoS2 transistors for future electronic applications. The schematic of the atomistic configuration of a monolayer MoS2 and that of the simulated device are shown in Figure 1. To describe electronic transport through MoS2, we perform selfconsistent ballistic quantum transport simulations within the nonequilibrium Green's function (NEGF) formalism using an effective mass Hamiltonian. Transport equations are solved iteratively together with Poisson’s equation until a self-consistency between charge density (calculated by analytical summation of transverse momentum modes within the first Brillouin zone) and electrostatic potential is achieved. Subsequently current is calculated as sffiffiffiffiffiffiffiffiffiffiffiffiffi Z e my kB T μ1 Ekx dE F ID ¼ 2 kx 1=2 kB T 2π3 p μ Ekx ð1Þ F1=2 2 TSD ðEkx Þ kB T Received: May 28, 2011 Revised: July 15, 2011 Published: July 26, 2011 3768
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Figure 1. Device structure of a monolayer MoS2 transistor. (a) Atomistic configuration of two-dimensional MoS2 monolayer, which is a 6.5 Å thick large band gap semiconductor (Eg = 1.8 eV). (b) Schematic cross section of a monolayer MoS2 transistor. The channel is an MoS2 monolayer, and the source and drain contacts can be of a metal like gold (Au), which is believed to make a good contact with small Schottky barrier at the junction (ref 7). The nominal device has the following parameters: Gate length LG = 15 nm, HfO2 (k = 25) gate oxide thickness tox = 2.8 nm, gate underlap of 2 nm at each side, Schottky barrier height of ΦB = 0.1 eV, power supply voltage of 0.5 V.
where F1/2(.) denotes the FermiDirac integral of order 1/2, TSD(.) is the transmission coefficient from source to drain, μ1 and μ2 are source and drain electrochemical potentials, p, m*, y e, kB, T, and Ekx are reduced Planck’s constant, transverse effective mass, elementary charge, Boltzmann constant, temperature, and longitudinal energy, respectively. Gate leakage current is ignored. The conduction band effective mass along the transport direction (x) is calculated to be 0.45m0 (K f Γ), m0 being the free electron mass, from the dispersion relations of monolayer MoS2.11 A calculation of effective mass along K f M yields a similar value to the first order. Hence we assume the transverse effective mass to be identical to that along the transport direction. The Hamiltonian of the metallic regions at source and drain is modeled using an effective mass close to m0 (1.01m0),15 and Dirichlet boundary conditions are imposed at the contacts. We use a dielectric constant of 3.3 for MoS2.16,17 Detailed device parameters used in this work are provided in the caption of Figure 1b. For the simulated device, source and drain work functions are assumed to be the same as that of the gate. A grid spacing as small as 0.1 nm along the x direction ensures the presence of states in both contact and channel regions in the entire energy range of interest within a single band description of effective mass Hamiltonian. A very good Ohmic contact with low contact resistance is essential in optimizing the device performance. However, one of the issues in the fabrication of an Ohmic contact is the difficulty in finding metals with desired work function. Tunneling contacts using narrow Schottky junctions, which is a more practical way to realize Ohmic contacts, may suffer from Fermi-level pinning due to defects and interface states resulting in a significant tunneling barrier and hence an increased contact resistance.18 We analyze the experimental IDVBG (drain currentback-gate voltage) characteristics at source-to-drain voltage VD = 10 mV reported in ref 7 in order to estimate the Schottky barrier height for the AuMoS2 junction, which we use for simulating our nominal device. The total resistance of the device at any gate voltage RTOT(VBG), expressed as VD/ID, is composed of three different
Figure 2. Analysis of experimental back-gated characteristics. (a) Variation of effective mobility μeff with back-gate voltage VBG obtained from the analysis of experimental back-gated currentvoltage characteristics at VD = 10 mV reported in ref 7. Contact resistances are accounted for by using barrier height ΦB at the metalMoS2 junction as a parameter. For a given ID, a larger Schottky barrier height decreases the channel resistance resulting in a higher mobility and vice versa. A mobility of 217 cm2/(V s) calculated in ref 7 without accounting for contact resistance is also plotted with a black dotted line. (b) Variation of mean free path λ with VBG for ΦB = 0 and 0.1 eV.
resistance components: the intrinsic channel resistance Rch(VBG) stemming from momentum breaking in the transport direction; the ballistic resistance RBal(VBG) arising due to finite electron group velocity; the specific contact resistivity Rc.19 The resistance Rc (per unit thickness), for a given Schottky barrier height of ΦB, assuming only thermionic current for the sake of simplicity, can be written as18 h3 eΦB ð2Þ exp Rc ¼ 4πe2 mtkB T kB T where h, m*, and t are Planck’s constant, effective mass, and thickness of MoS2 monolayer, respectively. In order to ensure that 2Rc (factor of 2 to account for resistances on both source and drain sides) is less than RTOT for all values of VBG, ΦB has to be less than or equal to 0.1 eV. Thus, we use a barrier height of 0.1 eV for our nominal device. However, it must be noted that this value of ΦB represents an upper bound on the actual Schottky barrier height, as all other parasitic, gate-voltage-independent resistances have been lumped into metalsemiconductor (MS) junction resistance. We further analyze the IDVBG characteristics, following the approach outlined in ref 19 to extract information about mobility (μeff) and mean free path (λ). Figure 2 shows the variation of μeff and λ with VBG for two different values of Schottky barrier 3769
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Figure 3. Device characteristics of monolayer MoS2 transistors. (a) IDVG characteristics at VD = 0.05 and 0.5 V on logarithmic (left axis) and linear scales (right axis). For the nominal device simulated, a maximum ON current as high as 1.6 mA/μm and a subthreshold swing (SS = ∂VG/∂ log10(ID)) close to 60 mV/decade are achieved. Drain-induced barrier lowering (DIBL) is as small as 10 mV/V even with very short channel length. (b) IDVD characteristics at VG = 0.2, 0.3, and 0.4 V. Beyond VD = 0.4 V, MoS2 transistors show a clear saturation behavior with an output conductance (gd = ∂ID/ ∂VD) of 21, 51, and 133 μS/μm at VG = 0.2, 0.3, and 0.4 V, respectively. (c) ION versus ION/IOFF for VD = 0.4, 0.5, and 0.6 V. With VD = 0.5 V, ION is as high as 500 μA/μm with 4 orders of magnitude in ONOFF current ratio. For the same ON current, ION/IOFF > 105 can be achieved with 0.6 V of drain voltage. (d) Transconductance (gm = ∂ID/∂VG) vs VG at VD = 0.5 V. The gm is as large as 4.4 mS/μm for the nominal device within the voltage range considered in this study. (e) IDVG characteristics for a long channel device with Lch = 500 nm is projected (dashed line) by Iproj = Ibal λmax/ (Lch + λmax), where Ibal is the ballistic current adopted from our simulation results (solid line), Iproj is the projected current for larger size of devices taking scattering into account, λmax is peak mean free path, and Lch is channel length. (f) Variation of ION (defined at VON = 0.4 V) with channel length. As Lch increases, current is decreased since carriers are exposed to greater number of scattering events. When Lch = 100 nm, projected current is one-fifth of the ballistic current. The inset shows a similar plot for peak gm.
heights of ΦB = 0 and 0.1 eV. The extracted peak mobility is about 220 and 350 cm2/(V s) for ΦB = 0 and 0.1 eV, respectively. The corresponding mean free paths are 15 and 22 nm. We choose the gate length to be 15 nm so that the device operates away from the diffusive limit where the transport is predominantly limited by scattering, thereby making our performance projections realistic. An underlap of 2 nm each on the source and the drain sides is introduced to reduce the fringe capacitances without significantly increasing the series resistance. The key device characteristics of MoS2 transistors are shown in Figure 3. The transfer characteristics reveal that the maximum current (Imax) is ∼1.6 mA/μm. However, we note that in the case of reflectionless contacts, Imax can be even larger due to the nonparabolicity present in the conduction band of monolayer MoS2 wherein a satellite valley along K f Γ, which is only about 3kBT above the conduction band minima, contributes to enhanced density-of-states than what is predicted from our parabolic band approximation. The maximumminimum current ratio (Imax/Imin) can be more than 10 orders of magnitude ignoring the gate leakage (Figure 3a). Gate-induced drain leakage (GIDL), one of the main leakage mechanisms that limits Imin in a conventional metaloxidesemiconductor (MOS) geometry, is significantly less in the case of an MoS2 transistor than in its Si counterpart due to the larger band gap, and hence a smaller gate voltage can, in principle, further reduce Imin. It must be noted, however, that a more rigorous analysis to predict the maximum
achievable Imax/Imin requires a multiband Hamiltonian description (including valence band) to properly account for the effects of GIDL, which is beyond the scope of this study. In practical applications, what is more important than Imax/Imin is the ONOFF current ratio (ION/IOFF), where the voltage window between VON and VOFF is the same as power supply voltage (i.e., VON VOFF = VD). Therefore, ION/IOFF can be increased with a larger supply voltage for the same ON state current. For the simulated device structure (LG = 15 nm), drain-induced barrier lowering (DIBL) is negligibly small (10 mV/V, Figure 3a) due to excellent electrostatics of the 2-D geometry, and hence a larger VD can significantly increase the ION/IOFF ratio for a given ION (Figure 3c). In Figure 3b, we can also see that the output characteristics for a given VG show saturation beyond VD = 0.4 V with reasonably small output conductance (gd = 21, 51, and 133 μS/μm at VG = 0.2, 0.3, and 0.4 V, respectively). We have also plotted the intrinsic device transconductance (gm = ∂ID/ ∂VG) from the IDVG data at VD = 0.5 V (Figure 3d). The maximum gm is 4.4 mS/μm, which is still less in comparison to the peak gm that can be achieved, as gm is monotonically increasing over the entire range of VG considered. This implies that at the largest gate voltage applied (VG = 0.7 V), additional gate voltage could still significantly enhance current and the consequent voltage drop would mainly be across the semiconductor and not across the gate oxide. Therefore, for the simulated EOT, the operation of a monolayer MoS2 transistor is mainly 3770
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Figure 4. Capacitancevoltage (CV) characteristics of monolayer MoS2 transistors with VD = 0 V. (a) Gate capacitance (CG = ∂Q/∂VG) and quantum capacitance (CQ = ∂Q/∂ψs) vs VG. Oxide capacitance (Cox = kε0/tox) is shown by the dashed line. ∂ψs/∂VG and ∂Vox/∂VG are shown for the same VG range in the inset. (b) Density-of-states (DOS) vs energy (main panel) and surface plot of logarithmic local density-of-states (LDOS) (inset) at VG = 0.1 V. The CQ plot, shown in Figure 4a, can be understood herein by examining the average of DOS near the Fermi level (dotted line) at a given VG. For gate voltages up to about ∼0.1 V, the gate controls the channel potential efficiently, as shown by a large ∂ψs/∂VG in the inset of Figure 4a; subsequently CQ increases leading to a reduction in gate control. Due to the short channel length, the DOS is reminiscent of a 1-D material system, wherein the Van Hove peak at each sub-band energy is broadened to a different extent by the contact, rather than that of a 2-D system with constant DOS. (c) Conduction band (Ec) profile along the channel at VD = 0.5 V and VG = 0.2 to 0.5 V in steps of 0.1 V. When a considerable VD is applied, gate control over the channel potential can still be efficient even at high gate voltages, indicating the operation close to quantum capacitance regime at the ON state.
Figure 5. Variation of subthreshold swing with oxide thickness. Subthreshold swing (SS) vs oxide thickness (tox) with gate length of LG = 15 and 30 nm. Subthreshold swing increases linearly with oxide thickness due to the decrease in Cox. For the same tox, the subthreshold swing of a device with longer gate length is significantly smaller due to immunity to short channel effects. The cross shows the experimental data from ref 7, implying that the gate efficiency, in practice, could be significantly improved by optimization.
dictated by its quantum capacitance and not by the oxide capacitance, the details of which will be discussed later. The experimental characteristics in ref 7 show a maximum drive current of 2.5 μA/μm for a device with a 500 nm long gate. Therefore, it is important to estimate the transfer characteristics for an optimized device with a similar gate length. Using the mean free path extracted from the experimental characteristics (Figure 2b), we calculate the corresponding IDVG characteristics by multiplying the ballistic current from our simulations with λmax/(Lch + λmax) (where λmax and Lch are the peak mean free path and channel length, respectively) as shown in Figure 3e. The maximum current obtained in this case is 69 μA/μm. The difference between this value and the experimentally observed 2.5 μA/μm is then likely due to the underlap series resistances, and a significant performance boost may be expected by reducing them.
Figure 6. (a) Logarithmic LDOS for ΦB = 0 at VG = 0.15 V and VD = 0.5 V near the source. Conduction band profile is shown as a solid line. The channel electrostatic potential increases near the metal semiconductor interface, resulting in an effective barrier of ∼0.1 eV, due to metal-induced gap states (MIGS). The Ec in the case of ΦB = 0.1 eV is also plotted for comparison (dashed line). (b) DOS from the sourcechannel interface (x = 1 Å) for ΦB = 0 and 0.1 eV. At a given energy, the DOS is larger in the case of a smaller barrier height since carriers in metallic contact effectively see a smaller tunneling barrier.
The scaling behavior is similarly investigated by calculating ION (defined at VON = 0.4 V) and the peak gm as a function of Lch up to 100 nm, as shown in Figure 3f. Capacitancegate voltage (CVG) characteristics are explored by performing equilibrium simulations, i.e., with source 3771
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Table 1. Comparison of Key Device Performance Parameters of In0.7Ga0.3As Quantum-Well FET (ref 22) and Monolayer MoS2 FET of Identical EOT and Channel Length Lch (nm)
EOT (Å)
Imax (mA/μm)
peak gm (mS/μm)
max ION/IOFF
min SS (mV/decade)
In0.7Ga0.3As quantum-well FET (ref 22)
75
22
0.49
1.75
312
85
monolayer MoS2 FET
75
22
0.19
0.3
1.4 107
60
and drain terminals grounded. The total gate capacitance CG (=∂Q/∂VG) and the quantum capacitance CQ (=∂Q/∂ψs) are numerically calculated from self-consistent charge Q and surface potential ψs obtained at each gate voltage (Figure 4a). Our numerical simulation results are in accordance with the analytical capacitance model (i.e., 1/CG = 1/CQ + 1/Cox) and the principle of voltage division.20 At low values of VG, the total gate capacitance is very small due to negligible charge density in the device. However as VG increases, CQ, which is a measure of the average density-of-states (DOS) at equilibrium Fermi level,20 increases due to lowering of electrostatic potential in the channel (Figure 4b). The saturation in CQ to a value smaller than the theoretically expected quantum capacitance in 2-D systems 2 2 (C2-D Q = e m*/πp ) is a result of reduced DOS in the channel due to wave function reflections at the contacts. With increasing gate voltage, the gate efficiency (∂ψs/∂VG) decreases (inset of Figure 4a) due to charge accumulation and screening effect. It must, however, be noted that under nonequilibrium conditions (with finite VD), the gate control over channel electrostatics is good even at large gate voltages (∂(Ec/e)/∂VG = 0.78 at VG = 0.5 V as shown in Figure 4c) due to lack of charge accumulation - an indication of the fact that the device operates closer to the quantum capacitance regime than to the oxide capacitance regime. It has been reported that high-k dielectric plays an important role in improving the monolayer MoS2 mobility and hence the device performance.7 The gate oxide can also significantly affect the switching abruptness, and therefore we examine the effect of oxide thickness on subthreshold swing (SS). As shown in Figure 5, SS increases linearly with oxide thickness, which is also predicted by the analytical subthreshold swing model in a conventional MOSFET.21 At tox = 30 nm, our nominal device shows larger SS (79 mV/decade with LG = 15 nm) than the experimentally reported value for same oxide thickness (74 mV/decade with LG = 500 nm),7 owing to short channel behavior. However, with LG = 30 nm, SS improves considerably due to the suppression of short channel effects (71 mV/decade for tox = 30 nm). Our simulations predict that the reported value of SS = 74 mV/decade could be achieved at LG = 23 nm with tox = 30 nm. We also analyzed the electrostatics of the exact geometry reported in ref 7 at OFF state by solving the Laplace equation and confirmed ∂(Ec/e)/∂VG to be equal to 1, implying that SS is expected to be 60 mV/decade. Hence we believe that there exists considerable room for optimization of gate dielectrics in MoS2 transistors. In fabricating monolayer MoS2 transistors, gold (Au) has been used to create an Ohmic contactSchottky contact with negligible barrier height.7 Our simulations show that the Schottky barrier height can effectively increase (by up to 0.1 eV in the case of ΦB = 0 for intermediate values of gate voltage) as can be seen from the solid line in Figure 6a. This is due to enhanced polarization in the channel near the MS junction owing to localized states induced by the metallic contact (known as metalinduced gap states (MIGS), which are clearly shown in the local density-of-states (LDOS) plot in Figure 6a). We note that this increase in barrier height, at identical gate voltage, is smaller for
contacts with larger Schottky barriers (dashed line in Figure 6a). This is due to the fact that a larger barrier reduces the tunneling probability for carriers, resulting in a smaller penetration of contact states into the channel, which is confirmed by the density-of-states plot at the source end for ΦB = 0 and 0.1 eV shown in Figure 6b. However, this increase in effective barrier height vanishes as VG increases further. With the above analysis of monolayer MoS2 transistors, it is instructive to compare some of their key device performance parameters to those of some other nonconventional devices recently explored. Table 1 shows such a comparison with In0.7Ga0.3As quantum-well FETs reported in ref 22. It is evident that the strength of MoS2 transistors lies in their large band gap, which results in a significant ION/IOFF and the excellent electrostatic integrity due to the 2-D nature of the system. However, with mobility lower than most of the IIIV materials, MoS2 transistors are more suited for low standby and operating power applications than for high performance where the experimental results from the former outperform the best theoretical predictions for the latter. The other most widely investigated 2-D system a graphene transistor has a very poor ONOFF ratio despite a high ON current,23 due to lack of band gap, making it very difficult to use them for digital applications. Fabrication of very narrow graphene nanoribbons with a finite band gap still remains a challenge and is prone to edge roughness resulting in a variation in energy gap. While there have been several reports of high-quality graphene nanoribbon transistors with large ON current, poor subthreshold swing and small ONOFF ratio continue to remain problems.24,25 Hence monolayer MoS2 transistors, owing to their unique combination of exquisite electrostatic integrity and large band gap, can prove to be a better alternative for low power applications than several of the non-Si devices already explored. To summarize, we have projected the ultimate scaling limit of monolayer MoS2 transistors by performing self-consistent quantum transport simulations. The key features of MoS2 transistors are (i) large gm (4.4 mS/μm) due to low DOS, (ii) significant Imax/Imin (>1010) owing to a large band gap, and (iii) excellent short channel behavior (DIBL ∼10 mV/V and SS ∼60 mV/decade) resulting from enhanced gate control. Along with these very good electrical characteristics, planarity of MoS2 monolayer makes MoS2 transistors one of the most viable candidates for future low power applications. Further, the properties of monolayer MoS2 like high thermal stability, chemical inertness, transparency, flexibility, and relative inexpensiveness give MoS2 transistors a unique advantage for several low cost electronic applications.
’ AUTHOR INFORMATION Corresponding Author
*E-mail:
[email protected]. Author Contributions †
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These authors contributed equally to this work. dx.doi.org/10.1021/nl2018178 |Nano Lett. 2011, 11, 3768–3773
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’ ACKNOWLEDGMENT This work was supported in part by faculty startup funding from University of California. ’ REFERENCES (1) Wilson, J. A.; Yoffe, A. D. Adv. Phys. 1969, 18, 193. (2) Gourmelon, E.; Lignier, O.; Hadouda, H.; Couturier, G.; Bernede, J. C.; Tedd, J.; Pouzed, J.; Salardenne, J. Sol. Energy Mater. Sol. Cells 1997, 46, 115. (3) Ho, W. K.; Yu, J. C.; Lin, J.; Yu, J. G.; Li, P. S. Langmuir 2004, 20, 5865. (4) Zong, X.; Yan, H.; Wu, G.; Ma, G.; Wen, F.; Wang, L.; Li, C. J. Am. Chem. Soc. 2008, 130, 7176. (5) Mak, K. F.; Lee, C.; Hone, J.; Shan, J.; Heinz, T. F. Phys. Rev. Lett. 2010, 105, 136805. (6) Splendiani, A.; Sun, L.; Zhang, Y.; Li, T.; Kim, J.; Chim, C. Y.; Galli, G.; Wang, F. Nano Lett. 2010, 10, 1271. (7) Radisavljevic, B.; Radenovi, A.; Brivio, J.; Giacometti, V.; Kis, A. Nat. Nanotechnol. 2011, 6, 147. (8) Novoselov, K. S.; Jiang, D.; Schedin, F.; Booth, T. J.; Khotkevich, V. V.; Morozov, S. V.; Geim, A. K. Proc. Natl. Acad. Sci. U.S.A. 2005, 102, 10451. (9) Gmelin Handbook of Inorganic and Organometallic Chemistry, 8th ed.; Springer-Verlag: Berlin, 1995; Vol. B7. (10) Frindt, R. F. J. Appl. Phys. 1965, 37, 1928. (11) Lebegue, S.; Eriksson, E. Phys. Rev. B 2009, 79, 115409. (12) Bolotin, K. I.; Sikes, K. J.; Jiang, Z.; Klima, M.; Fudenberg, G.; Hone, J.; Kim, P.; Stormer, H. L. Solid State Commun. 2008, 146, 351. (13) Chen, F.; Xia, J.; Ferry, D. K.; Tao, N. Nano Lett. 2009, 9, 2571. (14) Jena, D.; Konar, A. Phys. Rev. Lett. 2007, 98, 136805. (15) Szczyrbowski, J. J. Phys. D 1986, 19, 1257. (16) Molybdenum Disulfide; Kee Hing Cheung Kee Co., Ltd: Hong Kong, http://www.khck.hk/adgoogle/Molybdenum-Disulfide.htm (accessed July 12, 2011). (17) We use the value of dielectric constant corresponding to that of bulk MoS2, as detailed electrical characterization data of monolayer MoS2 has not yet been reported. (18) Sze, S. M. Physics of Semiconductor Devices, 3rd ed.; WileyInterscience: Hoboken, NJ, 2006. (19) Lundstrom, M. Physics of Nanoscale MOSFETs, https://nanohub.org/resources/5306 (20) Datta, S. Quantum Transport: Atom to Transistor, 2nd ed.; Cambridge University Press: Cambridge and New York, 2005. (21) Taur, Y.; Ning, T. H Fundamentals of Modern VLSI Devices; Cambridge University Press: Cambridge and New York, 1998. (22) Radosavljevic, M.; Chu-Kung, B.; Corcoran, S.; Dewey, G.; Hudait, M. K.; Fastenau, J. M.; Kavalieros, J.; Liu, W. K.; Lubyshev, D.; Metz, M.; Millard, K.; Mukherjee, N.; Rachmady, W.; Shah, U.; Chau, Robert IEDM Tech. Dig. 2009, 319. (23) Schwierz, Frank Nat. Nanotechnol. 2010, 89, 487. (24) Wang, X.; Ouyang, Y.; Li, X.; Wang, H.; Guo, J.; Dai, H. Phys. Rev. Lett. 2008, 100, 206803. (25) Liao, L.; Bai, J.; Cheng, R.; Lin, Y.-C.; Jiang, S.; Huang, Y.; Duan, X. Nano Lett. 2010, 10, 1917.
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